board: add apalis-imx8x

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>

12 files changed, 921 insertions, 1 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cd506c2e7a..4f1d2104c8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -767,6 +767,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qm-mek-auto2.dtb \
 	imx8qm-rom7720-a1.dtb \
 	fsl-imx8qxp-ai_ml.dtb \
+	fsl-imx8qxp-apalis.dtb \
 	fsl-imx8qxp-colibri.dtb \
 	fsl-imx8qxp-mek.dtb \
 	fsl-imx8qxp-lpddr4-val.dtb \
diff --git a/arch/arm/dts/fsl-imx8qxp-apalis.dts b/arch/arm/dts/fsl-imx8qxp-apalis.dts
new file mode 100644
index 0000000000..1bfc129973
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-apalis.dts
@@ -0,0 +1,302 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+
+/ {
+	model = "Toradex Apalis iMX8X";
+	compatible = "toradex,apalis-imx8x", "fsl,imx8qxp";
+
+	chosen {
+		bootargs = "console=ttyLP1,115200";
+		stdout-path = &lpuart1;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>;
+
+	apalis-imx8x {
+		/* Apalis UART1 */
+		pinctrl_lpuart1: lpuart1grp {
+			fsl,pins = <
+				SC_P_UART1_RX_ADMA_UART1_RX		0x06000020	/* SODIMM 118 */
+				SC_P_UART1_TX_ADMA_UART1_TX		0x06000020	/* SODIMM 112 */
+			>;
+		};
+
+		/* On-module Gigabit Ethernet PHY Micrel KSZ9031 */
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x14a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x14a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x61
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x61
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x61
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x61
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x61
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x61
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x61
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x61
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x61
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x61
+				/* On-module ETH_RESET# */
+				SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04		0x06000020
+				/* On-module ETH_INT# */
+				SC_P_ADC_IN2_LSIO_GPIO1_IO12			0x21
+			>;
+		};
+
+		/* Apalis BKL_ON */
+		pinctrl_gpio_bkl_on: gpio-bkl-on {
+			fsl,pins = <
+				SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13			0x40		/* SODIMM 286 */
+			>;
+		};
+
+		pinctrl_hog0: hog0grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
+			>;
+		};
+
+		pinctrl_hog1: hog1grp {
+			fsl,pins = <
+				/* Apalis USBO1_EN */
+				SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16		0x41		/* SODIMM 274 */
+			>;
+		};
+
+		/* Apalis RESET_MOCI# */
+		pinctrl_reset_moci: gpioresetmocigrp {
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x21
+			>;
+		};
+
+		/* On-module eMMC */
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x21
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x21
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x21
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21
+			>;
+		};
+
+		/* Apalis MMC1_CD# */
+		pinctrl_usdhc2_gpio: mmc1gpiogrp {
+			fsl,pins = <
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22		0x06000021	/* SODIMM 164 */
+			>;
+		};
+
+		pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp {
+			fsl,pins = <
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22		0x60		/* SODIMM 164 */
+			>;
+		};
+
+		/* Apalis USBH_EN */
+		pinctrl_usbh_en: usbhen {
+			fsl,pins = <
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x40		/* SODIMM 84 */
+			>;
+		};
+
+		/* Apalis MMC1 */
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041	/* SODIMM 154 */
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x21		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041	/* SODIMM 154 */
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x21		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041	/* SODIMM 154 */
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x21		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+
+		pinctrl_usdhc2_sleep: usdhc2slpgrp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_LSIO_GPIO4_IO23			0x60		/* SODIMM 154 */
+				SC_P_USDHC1_CMD_LSIO_GPIO4_IO24			0x60		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+	};
+};
+
+/* Apalis Gigabit LAN */
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	fsl,magic-packet;
+	fsl,rgmii_rxc_dly;
+	fsl,rgmii_txc_dly;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii";
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+	phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+/* Apalis UART1 */
+&lpuart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	disable-over-current;
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbotg3 {
+	status = "okay";
+};
+
+/* On-module eMMC */
+&usdhc1 {
+	bus-width = <8>;
+	non-removable;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	status = "okay";
+};
+
+/* Apalis MMC1 */
+&usdhc2 {
+	bus-width = <4>;
+	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+	disable-wp;
+	status = "okay";
+};
\ No newline at end of file
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index ce17728602..fd2e3fd317 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -88,6 +88,11 @@ config TARGET_APALIS_IMX8
 	select BOARD_LATE_INIT
 	select IMX8QM
 
+config TARGET_APALIS_IMX8X
+	bool "Support Apalis iMX8X module"
+	select BOARD_LATE_INIT
+	select IMX8QXP
+
 config TARGET_COLIBRI_IMX8X
 	bool "Support Colibri iMX8X module"
 	select BOARD_LATE_INIT
@@ -175,6 +180,7 @@ source "board/freescale/imx8dxl_phantom_mek/Kconfig"
 source "board/freescale/imx8dxl_evk/Kconfig"
 source "board/advantech/imx8qm_rom7720_a1/Kconfig"
 source "board/toradex/apalis-imx8/Kconfig"
+source "board/toradex/apalis-imx8x/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
 source "board/siemens/capricorn/Kconfig"
 
diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig
new file mode 100644
index 0000000000..ee61e09736
--- /dev/null
+++ b/board/toradex/apalis-imx8x/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_APALIS_IMX8X
+
+config SYS_BOARD
+	default "apalis-imx8x"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis-imx8x"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS
new file mode 100644
index 0000000000..761863aee7
--- /dev/null
+++ b/board/toradex/apalis-imx8x/MAINTAINERS
@@ -0,0 +1,9 @@
+Apalis iMX8X
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+S:	Maintained
+F:	arch/arm/dts/fsl-imx8x-apalis.dts
+F:	arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi
+F:	board/toradex/apalis-imx8x/
+F:	configs/apalis-imx8qxp_defconfig
+F:	include/configs/apalis-imx8x.h
diff --git a/board/toradex/apalis-imx8x/Makefile b/board/toradex/apalis-imx8x/Makefile
new file mode 100644
index 0000000000..19025863e8
--- /dev/null
+++ b/board/toradex/apalis-imx8x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2018-2019 Toradex
+#
+
+obj-y += apalis-imx8x.o
diff --git a/board/toradex/apalis-imx8x/apalis-imx8qxp-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8qxp-imximage.cfg
new file mode 100644
index 0000000000..e8868cd8e3
--- /dev/null
+++ b/board/toradex/apalis-imx8x/apalis-imx8qxp-imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Toradex
+ *
+ * Refer doc/README.imx8image for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM EMMC_FASTBOOT 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND mx8qx-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-apalis-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
new file mode 100644
index 0000000000..e8868cd8e3
--- /dev/null
+++ b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Toradex
+ *
+ * Refer doc/README.imx8image for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM EMMC_FASTBOOT 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND mx8qx-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-apalis-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c
new file mode 100644
index 0000000000..d24ef313ae
--- /dev/null
+++ b/board/toradex/apalis-imx8x/apalis-imx8x.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 Toradex
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <linux/libfdt.h>
+#include <fsl_esdhc_imx.h>
+#include <fdt_support.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-imx8/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/snvs_security_sc.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+#include <power-domain.h>
+#include <usb.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart1_pads[] = {
+	SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/*
+	 * This works around that having only UART1 up the baudrate is 1.2M
+	 * instead of 115.2k. Set UART0 clock root to 80 MHz
+	 */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_1, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+
+#ifdef CONFIG_FEC_MXC
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#undef CONFIG_MXC_GPIO /* TODO */
+#ifdef CONFIG_MXC_GPIO
+#define IOEXP_RESET IMX_GPIO_NR(1, 1)
+
+static iomux_cfg_t board_gpios[] = {
+	SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static void board_gpio_init(void)
+{
+	int ret;
+	struct gpio_desc desc;
+
+	ret = dm_gpio_lookup_name("gpio@1a_3", &desc);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc, "bb_per_rst_b");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc, 0);
+	udelay(50);
+	dm_gpio_set_value(&desc, 1);
+
+	imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
+
+	/* enable i2c port expander assert reset line */
+	gpio_request(IOEXP_RESET, "ioexp_rst");
+	gpio_direction_output(IOEXP_RESET, 1);
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_MXC_GPIO
+	board_gpio_init();
+#endif
+
+#ifdef CONFIG_SNVS_SEC_SC_AUTO
+	{
+		int ret = snvs_security_sc_init();
+
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+/* With this function there is no console output in linux, drop that for now */
+#if 0
+void board_quiesce_devices(void)
+{
+	const char *power_on_devices[] = {
+		"dma_lpuart1",
+
+		/* HIFI DSP boot */
+		"audio_sai0",
+		"audio_ocram",
+	};
+
+	power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
+}
+#endif
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+	sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD);
+	while(1);
+
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+void board_late_mmc_env_init() {}
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* TODO move to common */
+	env_set("board_name", "Apalis iMX8QXP");
+	env_set("board_rev", "v1.0");
+#endif
+
+	build_info();
+
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#else
+	env_set("sec_boot", "no");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /*TODO*/
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c
index d57fe4d5ef..e6fffda57d 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -134,7 +134,6 @@ int checkboard(void)
 {
 	puts("Board: Colibri iMX8QXP \n");
 
-	build_info();
 	print_bootinfo();
 
 	return 0;
@@ -228,6 +227,8 @@ int board_late_init(void)
 	env_set("board_rev", "v1.0");
 #endif
 
+	build_info();
+
 #ifdef CONFIG_AHAB_BOOT
 	env_set("sec_boot", "yes");
 #else
diff --git a/configs/apalis-imx8qxp_defconfig b/configs/apalis-imx8qxp_defconfig
new file mode 100644
index 0000000000..0592318c3f
--- /dev/null
+++ b/configs/apalis-imx8qxp_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+CONFIG_TARGET_APALIS_IMX8X=y
+CONFIG_SNVS_SEC_SC=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_IMX_BOOTAUX=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8x/apalis-imx8qxp-imximage.cfg"
+CONFIG_BOOTDELAY=1
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x08000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PHY=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x80400000
+CONFIG_PANIC_HANG=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h
new file mode 100644
index 0000000000..c9f77e70d0
--- /dev/null
+++ b/include/configs/apalis-imx8x.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Toradex
+ */
+
+#ifndef __APALIS_IMX8X_H
+#define __APALIS_IMX8X_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define USDHC1_BASE_ADDR                0x5B010000
+#define USDHC2_BASE_ADDR                0x5B020000
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_SKIP_RESOURCE_CHECKING
+
+/* Networking */
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_TFTP_TSIZE
+
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_SERVERIP			192.168.10.1
+
+/**
+ * SYS_SDRAM_BASE	0x80000000	0.125MiB
+ * SYS_TEXT_BASE	0x80020000	2.375MiB
+ * kernel_addr_r	0x80280000	45.5MiB
+ * fdt_addr_r		0x83000000	1MiB
+ * scriptaddr		0x83100000	15MiB
+ * __RESERVED__		0x84000000	48MiB
+ * loadaddr		0x87000000	48MiB
+ * ramdisk_addr_r	0x8a000000	288MiB
+ * SYS_MEMTEST_START	0x90000000
+ * SYS_MEMTEST_END	0xC0000000
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"kernel_addr_r=0x80280000\0" \
+	"fdt_addr_r=0x83000000\0" \
+	"ramdisk_addr_r=0x8a000000\0" \
+	"scriptaddr=0x83100000\0"
+
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${m4_0_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define FDT_FILE			"imx8qxp-apalis-eval.dtb"
+
+#include <config_distro_bootcmd.h>
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
+	AHAB_ENV \
+	M4_BOOT_ENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"boot_file=Image\0" \
+	"console=ttyLP1,115200\0" \
+	"fdt_addr=0x83000000\0"	\
+	"fdtfile=" FDT_FILE "\0" \
+	"fdt_high=\0" \
+	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"image=Image\0" \
+	"initrd_addr=0x83800000\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=PARTUUID=${uuid} rootwait " \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
+		"${vidargs}\0" \
+	"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
+		"apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \
+		"${fdt_addr}\0" \
+	"panel=NULL\0" \
+	"script=boot.scr\0" \
+	"setup=run mmcargs\0" \
+	"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
+		"if test \"$confirm\" = \"y\"; then " \
+		"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
+		"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
+		"${blkcnt}; fi\0" \
+	"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
+
+#define CONFIG_SYS_MEMTEST_START	0x90000000
+#define CONFIG_SYS_MEMTEST_END		0xc0000000
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC1 eMMC */
+#define CONFIG_SYS_MMC_ENV_PART		1
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M /* Increase max gunzip size */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		SZ_2G		/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		SZ_2K
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+/* USB Config */
+#define CONFIG_USBD_HS
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
+/* Networking */
+#define CONFIG_FEC_ENET_DEV 0
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			0x5B040000
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+#define CONFIG_ETHPRIME                 "eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			0x5B050000
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+#define CONFIG_ETHPRIME                 "eth1"
+#endif
+
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define FEC_QUIRK_ENET_MAC
+#define PHY_ANEG_TIMEOUT 20000
+
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#endif /* __APALIS_IMX8X_H */