apalis-imx8: clean-up device tree

Clean-up device tree syncing with Linux one as well.
Delete nodes not used by U-Boot.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

1 files changed, 71 insertions, 164 deletions

diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts
index b92838a2e9..a8773b2f33 100644
--- a/arch/arm/dts/fsl-imx8qm-apalis.dts
+++ b/arch/arm/dts/fsl-imx8qm-apalis.dts
@@ -44,7 +44,6 @@
 		};
 
 	};
-
 };
 
 &iomuxc {
@@ -60,51 +59,35 @@
 
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
-				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
-				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
-				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000048
-				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000048
-				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000048
-				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000048
-				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000048
-				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000048
-				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
-				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000048
-				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000048
-				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000048
-				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000048
-			>;
-		};
-
-		pinctrl_fec2: fec2grp {
-			fsl,pins = <
-				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x06000048
-				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x06000048
-				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x06000048
-				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x06000048
-				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x06000048
-				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x06000048
-				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x06000048
-				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x06000048
-				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x06000048
-				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x06000048
-				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x06000048
-				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x06000048
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
 			>;
 		};
 
-		pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
-			fsl,pins = <
-				SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
-				SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
-			>;
-		};
-
-		pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+		pinctrl_lpi2c1: lpi2c1grp {
 			fsl,pins = <
-				SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c
-				SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
+				SC_P_GPT0_CLK_DMA_I2C1_SCL		0x06000020
+				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0x06000020
+				/*
+				 * Change the default alt function from SCL/SDA to others,
+				 * to avoid select input conflict with GPT0
+				 */
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x0700004c
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x0700004c
+				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x0700004c
+				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x0700004c
 			>;
 		};
 
@@ -239,89 +222,9 @@
 				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000021
 			>;
 		};
-
-		pinctrl_lpi2c1: lpi2c1grp {
-			fsl,pins = <
-				SC_P_GPT0_CLK_DMA_I2C1_SCL		0x06000020
-				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0x06000020
-				/*
-				 * Change the default alt function from SCL/SDA to others,
-				 * to avoid select input conflict with GPT0
-				 */
-				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x0700004c
-				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x0700004c
-				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x0700004c
-				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x0700004c
-			>;
-		};
-
-		pinctrl_lpspi0: lpspi0grp {
-			fsl,pins = <
-				SC_P_SPI0_SCK_DMA_SPI0_SCK		0x0600004c
-				SC_P_SPI0_SDO_DMA_SPI0_SDO		0x0600004c
-				SC_P_SPI0_SDI_DMA_SPI0_SDI		0x0600004c
-				SC_P_SPI0_CS0_DMA_SPI0_CS0		0x0600004c
-				SC_P_SPI0_CS1_DMA_SPI0_CS1		0x0600004c
-			>;
-		};
 	};
 };
 
-&gpio2 {
-	status = "okay";
-};
-
-&gpio4 {
-	status = "okay";
-};
-
-&gpio5 {
-	status = "okay";
-};
-
-&usdhc1 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	bus-width = <8>;
-	non-removable;
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	bus-width = <4>;
-	cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
-	vmmc-supply = <&reg_usdhc2_vmmc>;
-	status = "okay";
-};
-
-&usdhc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	bus-width = <4>;
-	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
-	status = "okay";
-
-};
-
-&usbotg1 {
-	vbus-supply = <&reg_usb_otg1_vbus>;
-	srp-disable;
-	hnp-disable;
-	adp-disable;
-	disable-over-current;
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
-
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
@@ -347,67 +250,71 @@
 	};
 };
 
-&fec2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec2>;
-	phy-mode = "rgmii";
-	phy-handle = <&ethphy1>;
-	fsl,ar8031-phy-fixup;
-	fsl,magic-packet;
+&gpio2 {
 	status = "okay";
 };
 
-&i2c1_lvds0 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
-	clock-frequency = <100000>;
+&gpio4 {
 	status = "okay";
+};
 
-	it6263-0@4c {
-		compatible = "ITE,it6263";
-		reg = <0x4c>;
-	};
+&gpio5 {
+	status = "okay";
 };
 
-&i2c1_lvds1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
+&lpuart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
-	clock-frequency = <100000>;
+	pinctrl-0 = <&pinctrl_lpuart0>;
 	status = "okay";
-
-	it6263-1@4c {
-		compatible = "ITE,it6263";
-		reg = <0x4c>;
-	};
 };
 
-&lpspi0 {
-	#address-cells = <1>;
-	#size-cells = <0>;
+&lpuart1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpspi0>;
+	pinctrl-0 = <&pinctrl_lpuart1>;
 	status = "okay";
+};
 
-	spidev0: spi@0 {
-		reg = <0>;
-		compatible = "rohm,dh2228fv";
-		spi-max-frequency = <4000000>;
-	};
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	disable-over-current;
+	dr_mode = "peripheral";
+	status = "okay";
 };
 
-&lpuart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart0>;
+&usb2 {
+	dr_mode = "host";
 	status = "okay";
 };
 
-&lpuart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart1>;
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
 	status = "okay";
 };
 
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <4>;
+	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+};