MLK-19183-14: iMX8QXP SPL: Add ARM2 board support

Add implementation for ARM2 LPDDR4 board

Signed-off-by: Teo Hall <teo.hall@nxp.com>
(cherry picked from commit a6b6fd8aa69c2f8a9a4c8b5a15de6aa044b39fba)

5 files changed, 278 insertions, 2 deletions

diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 51c88f2f8c..3773732547 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -57,6 +57,7 @@ config TARGET_IMX8QM_MEK
 config TARGET_IMX8QXP_LPDDR4_ARM2
 	bool "Support i.MX8QXP lpddr4 validation board"
 	select BOARD_LATE_INIT
+        select SUPPORT_SPL
 	select IMX8QXP
 
 config TARGET_IMX8QXP_DDR3_ARM2
diff --git a/board/freescale/imx8qxp_arm2/Makefile b/board/freescale/imx8qxp_arm2/Makefile
index d947c6bfa5..62348c6d59 100644
--- a/board/freescale/imx8qxp_arm2/Makefile
+++ b/board/freescale/imx8qxp_arm2/Makefile
@@ -1,7 +1,11 @@
 #
-# Copyright 2017 NXP
+# Copyright 2017-2018 NXP
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
 obj-y += imx8qxp_arm2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
index ef4599facc..0847c3ba11 100644
--- a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
+++ b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
@@ -103,6 +103,7 @@ int board_early_init_f(void)
 
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 22)
 
+#ifndef CONFIG_SPL_BUILD
 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 	{USDHC1_BASE_ADDR, 0, 8},
 #ifndef CONFIG_TARGET_IMX8DX_DDR3_ARM2 
@@ -204,7 +205,7 @@ int board_mmc_getcd(struct mmc *mmc)
 }
 
 #endif /* CONFIG_FSL_ESDHC */
-
+#endif /* CONFIG_SPL_BUILD */
 
 #ifdef CONFIG_FEC_MXC
 #include <miiphy.h>
diff --git a/board/freescale/imx8qxp_arm2/spl.c b/board/freescale/imx8qxp_arm2/spl.c
new file mode 100644
index 0000000000..38258044e3
--- /dev/null
+++ b/board/freescale/imx8qxp_arm2/spl.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <environment.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include "pca953x.h"
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <dm.h>
+#include <imx8_hsio.h>
+#include <usb.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/video.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/arch/video_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPMI_NAND_PAD_CTRL	 ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \
+				  | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 22)
+
+static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+#ifndef CONFIG_TARGET_IMX8DX_DDR3_ARM2 
+	{USDHC2_BASE_ADDR, 0, 4},
+#endif
+};
+
+static iomux_cfg_t emmc0[] = {
+	SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t usdhc1_sd[] = {
+	SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_WP    | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */
+	SC_P_USDHC1_CD_B  | MUX_MODE_ALT(4) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD,  GPIO4 IO22 */
+	SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+void spl_dram_init(void)
+{
+    /* do nothing for now */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	sc_ipc_t ipcHndl = 0;
+
+#ifdef CONFIG_NAND_MXS
+	return 0;
+#endif
+        ipcHndl = gd->arch.ipc_channel_handle;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
+                        if (ret != SC_ERR_NONE)
+                                return ret;
+
+			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
+			init_clk_usdhc(0);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+	                ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_1, SC_PM_PW_MODE_ON);
+                        if (ret != SC_ERR_NONE)
+                                return ret;
+                        ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_GPIO_3, SC_PM_PW_MODE_ON);
+                        if (ret != SC_ERR_NONE)
+                                return ret;
+
+			imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd));
+			init_clk_usdhc(1);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			gpio_request(USDHC1_CD_GPIO, "sd1_cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1; /* eMMC */
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_FSL_ESDHC */
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_QSPI_BOOT)
+        sc_ipc_t ipcHndl = 0;
+
+        ipcHndl = gd->arch.ipc_channel_handle;
+        if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
+                puts("Warning: failed to initialize FSPI0\n");
+        }
+#endif
+        /* DDR initialization */
+        spl_dram_init();
+
+        puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+#if defined(CONFIG_QSPI_BOOT)
+        sc_ipc_t ipcHndl = 0;
+
+        ipcHndl = gd->arch.ipc_channel_handle;
+        if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
+                puts("Warning: failed to turn off FSPI0\n");
+        }
+#endif
+}
+
+void board_init_f(ulong dummy)
+{
+        /* Clear global data */
+        memset((void *)gd, 0, sizeof(gd_t));
+
+        arch_cpu_init();
+
+        board_early_init_f();
+
+        timer_init();
+
+        preloader_console_init();
+
+        /* Clear the BSS. */
+        memset(__bss_start, 0, __bss_end - __bss_start);
+
+        board_init_r(NULL, 0);
+}
+
diff --git a/include/configs/imx8qxp_arm2.h b/include/configs/imx8qxp_arm2.h
index 042bad8be9..f0c72f36a7 100644
--- a/include/configs/imx8qxp_arm2.h
+++ b/include/configs/imx8qxp_arm2.h
@@ -12,6 +12,50 @@
 
 #include "imx_env.h"
 
+#ifdef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SPL_SPI_LOAD
+#endif
+
+#define CONFIG_SPL_TEXT_BASE            0x0
+#define CONFIG_SPL_MAX_SIZE             (124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN          (1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0x1040 /* (32K + 2Mb)/sector_size */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION              0
+
+
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK                0x013E000
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR      0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x1000   /* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x3000   /* 12 KB */
+#define CONFIG_SERIAL_LPUART_BASE      0x5a060000
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_MALLOC_F_ADDR            0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#define CONFIG_OF_EMBED
+#define CONFIG_ATF_TEXT_BASE 0x80000000
+#define CONFIG_SYS_ATF_START 0x80000000
+/* #define CONFIG_FIT */
+
+/* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */
+#define SC_IPC_CH                       SC_IPC_AP_CH0
+
+#endif
+
 #define CONFIG_REMAKE_ELF
 
 #define CONFIG_BOARD_EARLY_INIT_F