diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-10-12 13:39:25 +0800 |
|---|---|---|
| committer | Bai Ping <ping.bai@nxp.com> | 2018-10-12 15:04:57 +0800 |
| commit | 7e7d6b34d209ad0e82c91bca4c082cb82e8a6d71 (patch) | |
| tree | f0e20657d5fba780b9cbfc4bb1175b907e321ecc | |
| parent | 0ede884b92ba342725528f8e2dcc44bf5a6a7d8d (diff) | |
MLK-19904 imx8mm_ddr4_evk: Update the mr value setting
Update the DDR4 MR value on i.MX8MM DDR4 EVK board.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 0db8f9bc6ee7e087515573f79bc406edf9b36f9f)
| -rw-r--r-- | board/freescale/imx8mm_evk/ddr4_timing.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/board/freescale/imx8mm_evk/ddr4_timing.c b/board/freescale/imx8mm_evk/ddr4_timing.c index a2bc6a860f..8b622a9040 100644 --- a/board/freescale/imx8mm_evk/ddr4_timing.c +++ b/board/freescale/imx8mm_evk/ddr4_timing.c @@ -24,7 +24,7 @@ struct dram_cfg_param ddr4_ddrc_cfg[] = { { DDRC_INIT1(0), 0x00020009 }, { DDRC_INIT2(0), 0x0000350f }, { DDRC_INIT3(0), (0xa34 << 16) | 0x105 }, - { DDRC_INIT4(0), (0x1028 << 16) | 0x240 }, + { DDRC_INIT4(0), (0x1028 << 16) | 0x200 }, { DDRC_INIT5(0), 0x001103cb }, { DDRC_INIT6(0), (0x200 << 16) | 0x200 }, { DDRC_INIT7(0), 0x814 }, @@ -102,7 +102,7 @@ struct dram_cfg_param ddr4_ddrc_cfg[] = { { DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0 }, { DDRC_FREQ1_RFSHTMG(0), 0x0018001a }, { DDRC_FREQ1_INIT3(0), (0x204 << 16) | 0x104 }, - { DDRC_FREQ1_INIT4(0), (0x1000 << 16) | 0x40 }, + { DDRC_FREQ1_INIT4(0), (0x1000 << 16) }, { DDRC_FREQ1_INIT6(0), (0x200 << 16) | 0x200 }, { DDRC_FREQ1_INIT7(0), 0x14 }, { DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604 }, /* t_ras_max=9*7.8us, t_ras_min=35ns */ @@ -133,7 +133,7 @@ struct dram_cfg_param ddr4_ddrc_cfg[] = { { DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0 }, { DDRC_FREQ2_RFSHTMG(0), 0x0006000e }, /* tREFI=7.8us */ { DDRC_FREQ2_INIT3(0), (0x204 << 16) | 0x104 }, - { DDRC_FREQ2_INIT4(0), (0x1000 << 16) | 0x40 }, + { DDRC_FREQ2_INIT4(0), (0x1000 << 16) }, { DDRC_FREQ2_INIT6(0), (0x200 << 16) | 0x200 }, { DDRC_FREQ2_INIT7(0), 0x14 }, { DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101 }, /* t_ras_max=9*7.8us, t_ras_min=35ns */ @@ -1099,7 +1099,7 @@ struct dram_cfg_param ddr4_fsp0_cfg[] = { { 0x5402f, 0xa34 }, { 0x54030, 0x105 }, { 0x54031, 0x1028 }, - { 0x54032, 0x240 }, + { 0x54032, 0x200 }, { 0x54033, 0x200 }, { 0x54034, 0x200 }, { 0x54035, 0x814 }, @@ -1142,7 +1142,7 @@ struct dram_cfg_param ddr4_fsp1_cfg[] = { { 0x5402f, 0x204 }, { 0x54030, 0x104 }, { 0x54031, 0x1000 }, - { 0x54032, 0x40 }, + { 0x54032, 0x0 }, { 0x54033, 0x200 }, { 0x54034, 0x200 }, { 0x54035, 0x14 }, @@ -1185,7 +1185,7 @@ struct dram_cfg_param ddr4_fsp2_cfg[] = { { 0x5402f, 0x204 }, { 0x54030, 0x104 }, { 0x54031, 0x1000 }, - { 0x54032, 0x40 }, + { 0x54032, 0x0 }, { 0x54033, 0x200 }, { 0x54034, 0x200 }, { 0x54035, 0x14 }, @@ -1229,7 +1229,7 @@ struct dram_cfg_param ddr4_fsp0_2d_cfg[] = { { 0x5402f, 0xa34 }, { 0x54030, 0x105 }, { 0x54031, 0x1028 }, - { 0x54032, 0x240 }, + { 0x54032, 0x200 }, { 0x54033, 0x200 }, { 0x54034, 0x200 }, { 0x54035, 0x814 }, |