colibri-imx8qxp: move debug uart to lpuart3

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 969f430f983d602afd83b6dd75b299e51463eae9)

3 files changed, 39 insertions, 13 deletions

diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts
index a365871200..514a14f681 100644
--- a/arch/arm/dts/fsl-imx8qxp-colibri.dts
+++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
@@ -25,8 +25,8 @@
 	compatible = "toradex,imx8qxp-colibri", "fsl,imx8qxp";
 
 	chosen {
-		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
-		stdout-path = &lpuart0;
+		bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
+		stdout-path = &lpuart3;
 	};
 
 	regulators {
@@ -70,6 +70,13 @@
 			>;
 		};
 
+		pinctrl_lpuart3: lpuart3grp {
+			fsl,pins = <
+				SC_P_FLEXCAN2_RX_ADMA_UART3_RX	0x06000020
+				SC_P_FLEXCAN2_TX_ADMA_UART3_TX	0x06000020
+			>;
+		};
+
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
 				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
@@ -243,6 +250,12 @@
 &lpuart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "disabled";
+};
+
+&lpuart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart3>;
 	status = "okay";
 };
 
diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
index 4ab7ff6612..6bd7ca19db 100644
--- a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
+++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
@@ -52,37 +52,50 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
 						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
-
+#if 0
 static iomux_cfg_t uart0_pads[] = {
 	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
+#endif
+static iomux_cfg_t uart3_pads[] = {
+	SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
 
 static void setup_iomux_uart(void)
 {
-	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+	imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 }
 
 int board_early_init_f(void)
 {
 	sc_ipc_t ipcHndl = 0;
+	sc_pm_clock_rate_t rate;
 	sc_err_t sciErr = 0;
 
 	ipcHndl = gd->arch.ipc_channel_handle;
 
-	/* Power up UART0 */
-	sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON);
+	/* This works around that having only UART3 up the baudrate is 1.2M
+	 * instead of 115.2k. Set UART0 clock root to 80 MHz */
+	rate = 80000000;
+	sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, SC_PM_CLK_PER, &rate);
+	if (sciErr != SC_ERR_NONE)
+		return 0;
+
+	/* Power up UART3 */
+	sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_3, SC_PM_PW_MODE_ON);
 	if (sciErr != SC_ERR_NONE)
 		return 0;
 
-	/* Set UART0 clock root to 80 MHz */
-	sc_pm_clock_rate_t rate = 80000000;
-	sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate);
+	/* Set UART3 clock root to 80 MHz */
+	rate = 80000000;
+	sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_3, SC_PM_CLK_PER, &rate);
 	if (sciErr != SC_ERR_NONE)
 		return 0;
 
-	/* Enable UART0 clock root */
-	sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false);
+	/* Enable UART3 clock root */
+	sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_3, SC_PM_CLK_PER, true, false);
 	if (sciErr != SC_ERR_NONE)
 		return 0;
 
@@ -365,7 +378,7 @@ int board_init(void)
 void board_quiesce_devices()
 {
 	const char *power_on_devices[] = {
-		"dma_lpuart0",
+		"dma_lpuart3",
 
 		/* HIFI DSP boot */
 		"audio_sai0",
diff --git a/include/configs/colibri-imx8qxp.h b/include/configs/colibri-imx8qxp.h
index bdab3b9952..4148c698fd 100644
--- a/include/configs/colibri-imx8qxp.h
+++ b/include/configs/colibri-imx8qxp.h
@@ -103,7 +103,7 @@
 	"script=boot.scr\0" \
 	"image=Image\0" \
 	"panel=NULL\0" \
-	"console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200\0" \
+	"console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200\0" \
 	"fdt_addr=0x83000000\0"			\
 	"fdt_high=0xffffffffffffffff\0"		\
 	"boot_fdt=try\0" \