MLK-16795 imx8mq_evk: Rename SPL DDR files and public functions

Change to use more generic name for DDR files and public functions used in SPL,
not specified to LPDDR4.

Signed-off-by: Ye Li <ye.li@nxp.com>

6 files changed, 16 insertions, 16 deletions

diff --git a/board/freescale/imx8mq_evk/Makefile b/board/freescale/imx8mq_evk/Makefile
index 273b60a296..a7a4e9a540 100644
--- a/board/freescale/imx8mq_evk/Makefile
+++ b/board/freescale/imx8mq_evk/Makefile
@@ -8,5 +8,5 @@ obj-y += imx8m_evk.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
-obj-y += ddr/lpddr4_pub_train_0608_simple.o ddr/train1d.o ddr/helper.o
+obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
 endif
diff --git a/board/freescale/imx8mq_evk/ddr/lpddr4.h b/board/freescale/imx8mq_evk/ddr/ddr.h
index 349f5925a0..bf55355556 100644
--- a/board/freescale/imx8mq_evk/ddr/lpddr4.h
+++ b/board/freescale/imx8mq_evk/ddr/ddr.h
@@ -9,8 +9,8 @@ enum fw_type {
 	FW_2D_IMAGE,
 };
 
-void lpddr4_pub_train(void);
-void ddr4_load_train_code(enum fw_type type);
+void ddr_init(void);
+void ddr_load_train_code(enum fw_type type);
 void lpddr4_800M_cfg_phy(void);
 extern void dram_pll_init(void);
 
diff --git a/board/freescale/imx8mq_evk/ddr/lpddr4_pub_train_0608_simple.c b/board/freescale/imx8mq_evk/ddr/ddr_init.c
index a3398e43b7..be547580c3 100644
--- a/board/freescale/imx8mq_evk/ddr/lpddr4_pub_train_0608_simple.c
+++ b/board/freescale/imx8mq_evk/ddr/ddr_init.c
@@ -9,7 +9,7 @@
 #include <asm/io.h>
 #include <asm/arch/ddr_memory_map.h>
 #include <asm/arch/clock.h>
-#include "lpddr4.h"
+#include "ddr.h"
 
 #ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
 #define ddr_printf(args...) printf(args)
@@ -135,7 +135,7 @@ void lpddr4_25MHz_cfg_umctl2(void)
 	reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000);
 }
 
-void lpddr4_pub_train(void)
+void ddr_init(void)
 {
 	/* change the clock source of dram_apb_clk_root  */
 	reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
@@ -149,7 +149,7 @@ void lpddr4_pub_train(void)
 	dram_pll_init();
 
 	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
-   
+
 	/* Configure uMCTL2's registers */
 	lpddr4_800MHz_cfg_umctl2();
 
@@ -170,8 +170,8 @@ void lpddr4_pub_train(void)
 	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
 	reg32_write(DDRC_SWCTL(0), 0x0000);
 	/*
-	 * ------------------- 9 -------------------  
-	 * Set DFIMISC.dfi_init_start to 1 
+	 * ------------------- 9 -------------------
+	 * Set DFIMISC.dfi_init_start to 1
 	 *  -----------------------------------------
 	 */
 	reg32_write(DDRC_DFIMISC(0), 0x00000030);
diff --git a/board/freescale/imx8mq_evk/ddr/train1d.c b/board/freescale/imx8mq_evk/ddr/ddrphy_train.c
index 60909f5001..c4e4378bd5 100644
--- a/board/freescale/imx8mq_evk/ddr/train1d.c
+++ b/board/freescale/imx8mq_evk/ddr/ddrphy_train.c
@@ -8,7 +8,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/ddr_memory_map.h>
-#include "lpddr4.h"
+#include "ddr.h"
 
 void ddr_pll_bypass_100mts(void) {
 	/* change the clock source of dram_alt_clk_root to source 2 --100MHz */
@@ -248,7 +248,7 @@ void lpddr4_800M_cfg_phy(void) {
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20060, 0x2);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	/* load the 1D training image */
-	ddr4_load_train_code(FW_1D_IMAGE);
+	ddr_load_train_code(FW_1D_IMAGE);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
 
@@ -482,7 +482,7 @@ wait_ddrphy_training_complete();
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	/* load the 2D training image */
-	ddr4_load_train_code(FW_2D_IMAGE);
+	ddr_load_train_code(FW_2D_IMAGE);
 
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
 	dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
diff --git a/board/freescale/imx8mq_evk/ddr/helper.c b/board/freescale/imx8mq_evk/ddr/helper.c
index 8c593dc463..782009eb39 100644
--- a/board/freescale/imx8mq_evk/ddr/helper.c
+++ b/board/freescale/imx8mq_evk/ddr/helper.c
@@ -12,7 +12,7 @@
 #include <asm/arch/ddr_memory_map.h>
 #include <asm/sections.h>
 
-#include "lpddr4.h"
+#include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
 
 /* We need PHY iMEM PHY is 32KB padded */
-void ddr4_load_train_code(enum fw_type type)
+void ddr_load_train_code(enum fw_type type)
 {
 	u32 tmp32, i;
 	u32 error = 0;
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index 580448a62f..6e8837878d 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -21,14 +21,14 @@
 #include <asm/imx-common/mxc_i2c.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
-#include "ddr/lpddr4.h"
+#include "ddr/ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 void spl_dram_init(void)
 {
-	/* ddr train */
-	lpddr4_pub_train();
+	/* ddr init */
+	ddr_init();
 }
 
 #define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)