diff options
| author | Jian Li <jian.li@nxp.com> | 2017-12-04 10:30:46 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2017-12-04 10:48:40 +0800 |
| commit | 696326cba50890331370e18ef41a7f63293def8f (patch) | |
| tree | 31a4127dfa2bd8f07b3b41ad913a37abbdf4f4d7 | |
| parent | db2dbf622d3c711b2fbd85e6814992e023479dad (diff) | |
MLK-17055 imx8mq: evk: update DDR seting for display flickering issue
1. With this change, no flickering when LCDIF + MIPI-DSI
in 720p60 single display case
2. With this change, no flickering when DCSS in 4kp60
while running 4x memtester at the same time
side effect:
GPU resolve performance downgrade ~20%, no obvious impact
to non-resolve GPU cases.
Signed-off-by: Jian Li <jian.li@nxp.com>
| -rw-r--r-- | board/freescale/imx8mq_evk/ddr/ddr_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/imx8mq_evk/ddr/ddr_init.c b/board/freescale/imx8mq_evk/ddr/ddr_init.c index 8572a6f1f3..ba46201209 100644 --- a/board/freescale/imx8mq_evk/ddr/ddr_init.c +++ b/board/freescale/imx8mq_evk/ddr/ddr_init.c @@ -90,7 +90,7 @@ void lpddr4_800MHz_cfg_umctl2(void) dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505); dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c); dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b); - dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x900093e7); + dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009); dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574); dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016); dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000); |