diff options
| author | Ye Li <ye.li@nxp.com> | 2017-11-15 00:58:18 -0600 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-12-08 07:00:45 -0600 |
| commit | 31d29dd181d1db5bc56a6c5d7d0e035f3c5c36f1 (patch) | |
| tree | 538f94ca50e3c2487fcc957b3f3c36afea11fa4f | |
| parent | 6cb839cabb42b81e37214e00448fc5dac89fd1f1 (diff) | |
MLK-17109-4 imx8mq_arm2: Add i.MX8MQ DDR3L and DDR4 ARM2 boards support
Add board codes, configurations, DTS and DDR initialization codes for the
DDR3L and DDR4 ARM2 boards.
Supported modules
- DDR3L ARM2: Two RANK DDR3L, QSPI B, eMMC/SD, RMII ENET, UART.
- DDR4 ARM2: Two RANK DDR4, SD, NAND, RGMII ENET, UART.
NAND read/write/erase is ok in u-boot, NAND SPL boot will be tested later
when tool is ready.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
20 files changed, 4504 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/imx8m/Kconfig b/arch/arm/cpu/armv8/imx8m/Kconfig index 1764ec68b6..0c23db3c83 100644 --- a/arch/arm/cpu/armv8/imx8m/Kconfig +++ b/arch/arm/cpu/armv8/imx8m/Kconfig @@ -12,11 +12,22 @@ config TARGET_IMX8MQ_EVK select IMX8M select SUPPORT_SPL +config TARGET_IMX8MQ_DDR3L_ARM2 + bool "imx8mq_ddr3l_arm2" + select IMX8M + select SUPPORT_SPL + +config TARGET_IMX8MQ_DDR4_ARM2 + bool "imx8mq_ddr4_arm2" + select IMX8M + select SUPPORT_SPL + endchoice config SYS_SOC default "imx8m" source "board/freescale/imx8mq_evk/Kconfig" +source "board/freescale/imx8mq_arm2/Kconfig" endif diff --git a/arch/arm/cpu/armv8/imx8m/clock.c b/arch/arm/cpu/armv8/imx8m/clock.c index cf4e5977f8..7953d59635 100644 --- a/arch/arm/cpu/armv8/imx8m/clock.c +++ b/arch/arm/cpu/armv8/imx8m/clock.c @@ -625,6 +625,14 @@ int clock_init() clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7)); clock_enable(CCGR_QSPI, 1); + /* + * set rawnand root + * sys pll1 400M + */ + clock_enable(CCGR_RAWNAND, 0); + clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */ + clock_enable(CCGR_RAWNAND, 1); + if (!is_usb_boot()) { clock_enable(CCGR_USB_CTRL1, 0); clock_enable(CCGR_USB_CTRL2, 0); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 54c3dfc323..c5e280384a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -386,7 +386,9 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \ imx7ulp-10x10-arm2.dtb \ imx7ulp-14x14-arm2.dtb -dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb +dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \ + fsl-imx8mq-ddr3l-arm2.dtb \ + fsl-imx8mq-ddr4-arm2.dtb dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qm-mek.dtb \ diff --git a/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts b/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts new file mode 100644 index 0000000000..0234ee2f76 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts @@ -0,0 +1,542 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ DDR3L ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-arm2 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16 + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts b/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts new file mode 100644 index 0000000000..0b6136de64 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts @@ -0,0 +1,492 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ DDR4 ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-arm2 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16 + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/board/freescale/imx8mq_arm2/Kconfig b/board/freescale/imx8mq_arm2/Kconfig new file mode 100644 index 0000000000..41757ccd32 --- /dev/null +++ b/board/freescale/imx8mq_arm2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MQ_DDR3L_ARM2 || TARGET_IMX8MQ_DDR4_ARM2 + +config SYS_BOARD + default "imx8mq_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mq_arm2" + +endif diff --git a/board/freescale/imx8mq_arm2/Makefile b/board/freescale/imx8mq_arm2/Makefile new file mode 100644 index 0000000000..828701f96c --- /dev/null +++ b/board/freescale/imx8mq_arm2/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2017 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8m_arm2.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr/helper.o +ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 +obj-y += ddr/ddr3l/ddr_init.o ddr/ddr3l/ddrphy_train.o +else +obj-y += ddr/ddr4/ddr_init.o ddr/ddr4/ddrphy_train.o +endif +endif diff --git a/board/freescale/imx8mq_arm2/ddr/ddr.h b/board/freescale/imx8mq_arm2/ddr/ddr.h new file mode 100644 index 0000000000..4f3b65afe3 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr.h @@ -0,0 +1,49 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SRC_DDRC_RCR_ADDR +#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000 +#endif +#ifndef DDR_CSD1_BASE_ADDR +#define DDR_CSD1_BASE_ADDR 0x40000000 +#endif + +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +void ddr_init(void); +void ddr_load_train_code(enum fw_type type); +void wait_ddrphy_training_complete(void); +void ddr3_phyinit_train_1600mts(void); +void ddr4_phyinit_train_2400mts(void); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline uint32_t reg32_read(unsigned long addr) +{ + return readl(addr); +} +/* +static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val) +{ + writel(val, addr); +} +*/ + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +static inline void reg32clrbit(unsigned long addr, u32 bit) +{ + clrbits_le32(addr, (1 << bit)); +} diff --git a/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c new file mode 100644 index 0000000000..9d62cab634 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c @@ -0,0 +1,188 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr_memory_map.h> +#include <asm/arch/clock.h> +#include "../ddr.h" + +#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG +#define ddr_printf(args...) printf(args) +#else +#define ddr_printf(args...) +#endif + +#include "../wait_ddrphy_training_complete.c" + +volatile unsigned int tmp; +void umctl2_cfg(void){ + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + do{ + tmp = 0x7 & (reg32_read(DDRC_STAT(0))); + } while (tmp);/* wait init state */ + + reg32_write(DDRC_MSTR(0), 0x83040001);/* two rank */ + + reg32_write(DDRC_MRCTRL0(0), 0x40004030); + reg32_write(DDRC_MRCTRL1(0), 0x0001c68e); + reg32_write(DDRC_MRCTRL2(0), 0x921b7e95); + reg32_write(DDRC_DERATEEN(0), 0x00000506); + reg32_write(DDRC_DERATEINT(0), 0x9a4fbdf1); + reg32_write(DDRC_MSTR2(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + reg32_write(DDRC_PWRTMG(0), 0x00532203); + reg32_write(DDRC_HWLPCTL(0), 0x0b6d0000); + reg32_write(DDRC_HWFFCCTL(0), 0x00000030); + reg32_write(DDRC_RFSHCTL0(0), 0x00203020); + reg32_write(DDRC_RFSHCTL1(0), 0x0001000d); + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + reg32_write(DDRC_RFSHTMG(0), 0x0061008c); + reg32_write(DDRC_CRCPARCTL0(0), 0x00000000); + reg32_write(DDRC_CRCPARCTL1(0), 0x00000000); + reg32_write(DDRC_INIT0(0), 0xc0030002); + reg32_write(DDRC_INIT1(0), 0x0001000b); + reg32_write(DDRC_INIT2(0), 0x00006303); + reg32_write(DDRC_INIT3(0), 0x0d700044);/* MR1, MR0 */ + reg32_write(DDRC_INIT4(0), 0x00180000);/* MR2 */ + reg32_write(DDRC_INIT5(0), 0x00090071); + reg32_write(DDRC_INIT6(0), 0x00000000); + reg32_write(DDRC_INIT7(0), 0x00000000); + reg32_write(DDRC_DIMMCTL(0), 0x00000032); + reg32_write(DDRC_RANKCTL(0), 0x00000ee5); + reg32_write(DDRC_DRAMTMG0(0), 0x0c101a0e); + reg32_write(DDRC_DRAMTMG1(0), 0x000a0314); + reg32_write(DDRC_DRAMTMG2(0), 0x04060509); + reg32_write(DDRC_DRAMTMG3(0), 0x00002006); + reg32_write(DDRC_DRAMTMG4(0), 0x06020306); + reg32_write(DDRC_DRAMTMG5(0), 0x0b060202); + reg32_write(DDRC_DRAMTMG6(0), 0x060a0009); + reg32_write(DDRC_DRAMTMG7(0), 0x0000060b); + reg32_write(DDRC_DRAMTMG8(0), 0x01017c0a); + reg32_write(DDRC_DRAMTMG9(0), 0x4000000e); + reg32_write(DDRC_DRAMTMG10(0), 0x00070803); + reg32_write(DDRC_DRAMTMG11(0), 0x0101000b); + reg32_write(DDRC_DRAMTMG12(0), 0x00000000); + reg32_write(DDRC_DRAMTMG13(0), 0x5d000000); + reg32_write(DDRC_DRAMTMG14(0), 0x00000b39); + reg32_write(DDRC_DRAMTMG15(0), 0x80000000); + reg32_write(DDRC_DRAMTMG17(0), 0x00f1006a); + reg32_write(DDRC_ZQCTL0(0), 0x50800020); + reg32_write(DDRC_ZQCTL1(0), 0x00000070); + reg32_write(DDRC_ZQCTL2(0), 0x00000000); + reg32_write(DDRC_DFITMG0(0), 0x03868203); + reg32_write(DDRC_DFITMG1(0), 0x00020103); + reg32_write(DDRC_DFILPCFG0(0), 0x07713121); + reg32_write(DDRC_DFILPCFG1(0), 0x00000010); + reg32_write(DDRC_DFIUPD0(0), 0xe0400018); + reg32_write(DDRC_DFIUPD1(0), 0x0005003c); + reg32_write(DDRC_DFIUPD2(0), 0x00000000); + reg32_write(DDRC_DFIMISC(0), 0x00000011); + reg32_write(DDRC_DFITMG2(0), 0x00000603); + reg32_write(DDRC_DFITMG3(0), 0x00000001); + reg32_write(DDRC_DBICTL(0), 0x00000001); + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000); + + reg32_write(DDRC_ADDRMAP0(0), 0x00000016); /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */ + reg32_write(DDRC_ADDRMAP1(0), 0x00080808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */ + reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2; [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */ + reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6; [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */ + reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6; [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */ + reg32_write(DDRC_ADDRMAP6(0), 0x0f070707); /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */ + reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); + reg32_write(DDRC_ADDRMAP8(0), 0x00000000); /* [5:0] bg-b0; [13:8]bg-b1 */ + reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP11(0), 0x00000000); + + + reg32_write(DDRC_ODTCFG(0), 0x041d0f5c); + reg32_write(DDRC_ODTMAP(0), 0x00000201); + reg32_write(DDRC_SCHED(0), 0x7ab50b07); + reg32_write(DDRC_SCHED1(0), 0x00000022); + reg32_write(DDRC_PERFHPR1(0), 0x7b00665e); + reg32_write(DDRC_PERFLPR1(0), 0x2b00c4e1); + reg32_write(DDRC_PERFWR1(0), 0xb700c9fe); + reg32_write(DDRC_DBG0(0), 0x00000017); + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_DBGCMD(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x00000001); + reg32_write(DDRC_POISONCFG(0), 0x00010000); + reg32_write(DDRC_PCCFG(0), 0x00000100); + reg32_write(DDRC_PCFGR_0(0), 0x00003051); + reg32_write(DDRC_PCFGW_0(0), 0x000061d2); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + reg32_write(DDRC_PCFGQOS0_0(0), 0x02100b04); + reg32_write(DDRC_PCFGQOS1_0(0), 0x003f0353); + reg32_write(DDRC_PCFGWQOS0_0(0), 0x00000002); + reg32_write(DDRC_PCFGWQOS1_0(0), 0x000005fd); +} + +void ddr_init(void) +{ + /* change the clock source of dram_apb_clk_root */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16)); + + /* disable the clock gating */ + reg32_write(0x303A00EC,0x0000ffff); + reg32setbit(0x303A00F8,5); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + + dram_pll_init(SSCG_PLL_OUT_400M); + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /* Configure uMCTL2's registers */ + umctl2_cfg(); + + reg32setbit(DDRC_RFSHCTL3(0),0); /* dis_auto_refresh */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + ddr_load_train_code(FW_1D_IMAGE); + + reg32_write(DDRC_DBG1(0), 0x00000000); /* ('b00000000_00000000_00000000_00000000) ('d0) */ + reg32setbit(DDRC_PWRCTL(0),5); /* selfref_sw=1, self-refresh */ + reg32clrbit(DDRC_SWCTL(0), 0); /* sw_done=0, enable quasi-dynamic programming */ + reg32_write(DDRC_DFIMISC(0), 0x00000000); + + /* Configure DDR3L PHY's registers */ + ddr3_phyinit_train_1600mts(); + + do { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097); + } while (tmp != 0); + + reg32setbit(DDRC_DFIMISC(0),5);/* dfi_init_start=1 */ + do{ + tmp = 0x1 & (reg32_read(DDRC_DFISTAT(0))); + } while (!tmp);/* wait DFISTAT.dfi_init_complete to 1 */ + + reg32clrbit(DDRC_DFIMISC(0),5);/* dfi_init_start=0 */ + reg32setbit(DDRC_DFIMISC(0),0);/* dfi_init_complete_en=1 */ + + reg32clrbit(DDRC_PWRCTL(0),5);/* selfref_sw=0, exit self-refresh */ + + reg32setbit(DDRC_SWCTL(0), 0);/* sw_done=1, disable quasi-dynamic programming */ + + /* wait SWSTAT.sw_done_ack to 1 */ + do{ + tmp = 0x1 & (reg32_read(DDRC_SWSTAT(0))); + } while (!tmp); + + /* wait STAT to normal state */ + do{ + tmp = 0x7 & (reg32_read(DDRC_STAT(0))); + } while (tmp != 0x1); + + reg32_write(DDRC_PCTRL_0(0), 0x00000001); /* enable port 0 */ + + reg32clrbit(DDRC_RFSHCTL3(0), 0); /* auto-refresh enable */ + +} diff --git a/board/freescale/imx8mq_arm2/ddr/ddr3l/ddrphy_train.c b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddrphy_train.c new file mode 100644 index 0000000000..5d5e5cecf7 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddrphy_train.c @@ -0,0 +1,355 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr_memory_map.h> +#include "../ddr.h" + +#define DDR3_MR1_RTT120_RON40 ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=00:40ohm */ +#define DDR3_MR1_RTT120_RON34 ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=01:34ohm */ +#define DDR3_MR1_RTT60_RON40 ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=00:40ohm */ +#define DDR3_MR1_RTT60_RON34 ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=01:34ohm */ +#define DDR3_MR1_RTT40_RON34 ((0L << 9) | (1L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=011:40ohm;Ron:M[5,1]=01:34ohm */ +#define DDR3_MR1_RTT_DIS_RON40 ((0L << 9) | (0L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=000:disable;Ron:M[5,1]=00:40ohm */ + +#define DDR3_PHY_RON40 40 /* 40ohm */ +#define DDR3_PHY_RON34 34 /* 34ohm */ + +#define DDR3_PHY_RTT120 120 /* 120ohm */ +#define DDR3_PHY_RTT60 60 /* 60ohm */ +#define DDR3_PHY_RTT40 40 /* 40ohm */ +#define DDR3_PHY_RTT48 48 /* 48ohm */ + +#define DDR3_RTT_WR_DIS 0UL +#define DDR3_RTT_WR_60 1UL +#define DDR3_RTT_WR_120 2UL + +#define DDR3_MR1_VAL DDR3_MR1_RTT120_RON40 +#define DDR3_MR2_RTT_WR_VAL DDR3_RTT_WR_DIS + +#define DDR3_PHY_RON DDR3_PHY_RON40 +#define DDR3_PHY_RTT DDR3_PHY_RTT120 + + +#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr), data) +#define dwc_ddrphy_apb_rd(addr) (reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr))) + +void ddr3_phyinit_train_1600mts(void){ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x1005f,0x3ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1015f,0x3ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1105f,0x3ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1115f,0x3ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1205f,0x3ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1215f,0x3ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1305f,0x3ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1315f,0x3ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ + + dwc_ddrphy_apb_wr(0x55,0x3ff); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x1055,0x3ff); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x2055,0x3ff); /* DWC_DDRPHYA_ANIB2_ATxSlewRat */ + dwc_ddrphy_apb_wr(0x3055,0x3ff); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x4055,0xff); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x5055,0xff); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x6055,0x3ff); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x7055,0x3ff); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x8055,0x3ff); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x9055,0x3ff); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x200c5,0xb); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ + dwc_ddrphy_apb_wr(0x2002e,0x1); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ + + dwc_ddrphy_apb_wr(0x20024,0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ + dwc_ddrphy_apb_wr(0x2003a,0x0); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + dwc_ddrphy_apb_wr(0x20056,0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ + dwc_ddrphy_apb_wr(0x1004d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1014d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1104d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1114d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1204d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1214d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1304d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1314d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x10049,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x10149,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x11049,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x11149,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x12049,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x12149,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x13049,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x13149,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x43,0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */ + dwc_ddrphy_apb_wr(0x1043,0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */ + dwc_ddrphy_apb_wr(0x2043,0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */ + dwc_ddrphy_apb_wr(0x3043,0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */ + dwc_ddrphy_apb_wr(0x4043,0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */ + dwc_ddrphy_apb_wr(0x5043,0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */ + dwc_ddrphy_apb_wr(0x6043,0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */ + dwc_ddrphy_apb_wr(0x7043,0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */ + dwc_ddrphy_apb_wr(0x8043,0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */ + dwc_ddrphy_apb_wr(0x9043,0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */ + dwc_ddrphy_apb_wr(0x20018,0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */ + dwc_ddrphy_apb_wr(0x20075,0x0); /* DWC_DDRPHYA_MASTER0_DfiCAMode */ + dwc_ddrphy_apb_wr(0x20050,0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ + dwc_ddrphy_apb_wr(0x20008,0x190); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ + dwc_ddrphy_apb_wr(0x20088,0x9); /* DWC_DDRPHYA_MASTER0_CalRate */ + dwc_ddrphy_apb_wr(0x200b2,0xf8); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ + dwc_ddrphy_apb_wr(0x10043,0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x10143,0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x11043,0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x11143,0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x12043,0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x12143,0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x13043,0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x13143,0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x200fa,0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ + dwc_ddrphy_apb_wr(0x20019,0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ + dwc_ddrphy_apb_wr(0x200f0,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ + dwc_ddrphy_apb_wr(0x200f1,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ + dwc_ddrphy_apb_wr(0x200f2,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ + dwc_ddrphy_apb_wr(0x200f3,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ + dwc_ddrphy_apb_wr(0x200f4,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ + dwc_ddrphy_apb_wr(0x200f5,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ + dwc_ddrphy_apb_wr(0x200f6,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ + dwc_ddrphy_apb_wr(0x200f7,0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ + dwc_ddrphy_apb_wr(0x2000b,0x33); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + dwc_ddrphy_apb_wr(0x2000c,0x65); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + dwc_ddrphy_apb_wr(0x2000d,0x3e9); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + dwc_ddrphy_apb_wr(0x2000e,0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + dwc_ddrphy_apb_wr(0x20025,0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */ + dwc_ddrphy_apb_wr(0x2002d,0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */ + + dwc_ddrphy_apb_wr(0x20060,0x2); /* DWC_DDRPHYA_MASTER0_MemResetL */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x54000,0x0); + dwc_ddrphy_apb_wr(0x54001,0x0); + dwc_ddrphy_apb_wr(0x54002,0x0); + dwc_ddrphy_apb_wr(0x54003,0x640); + dwc_ddrphy_apb_wr(0x54004,0x2); + dwc_ddrphy_apb_wr(0x54005,((DDR3_PHY_RON << 8) | (DDR3_PHY_RTT << 0))); + dwc_ddrphy_apb_wr(0x54006,0x13b); + dwc_ddrphy_apb_wr(0x54007,0x2000); + + dwc_ddrphy_apb_wr(0x54008,0x303); /* two ranks */ + + dwc_ddrphy_apb_wr(0x54009,0x200); + dwc_ddrphy_apb_wr(0x5400a,0x0); + dwc_ddrphy_apb_wr(0x5400b,0x31f); + dwc_ddrphy_apb_wr(0x5400c,0xc8); + + dwc_ddrphy_apb_wr(0x54012,0x1); + dwc_ddrphy_apb_wr(0x5402f,0xd70); /* MR0 */ + dwc_ddrphy_apb_wr(0x54030,DDR3_MR1_VAL); /* MR1=6:Ron=34ohm/Rtt(NOM)=60ohm */ + dwc_ddrphy_apb_wr(0x54031,(0x18 | (DDR3_MR2_RTT_WR_VAL << 9))); /*MR2 */ + dwc_ddrphy_apb_wr(0x5403a,0x1221); + dwc_ddrphy_apb_wr(0x5403b,0x4884); + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099,0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + + wait_ddrphy_training_complete(); + + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x90000,0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90001,0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90002,0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90003,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x90004,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x90005,0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x90029,0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x9002a,0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x9002b,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x9002c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9002d,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9002e,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x9002f,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + dwc_ddrphy_apb_wr(0x90030,0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + dwc_ddrphy_apb_wr(0x90031,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + dwc_ddrphy_apb_wr(0x90032,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + dwc_ddrphy_apb_wr(0x90033,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + dwc_ddrphy_apb_wr(0x90034,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + dwc_ddrphy_apb_wr(0x90035,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + dwc_ddrphy_apb_wr(0x90036,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + dwc_ddrphy_apb_wr(0x90037,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + dwc_ddrphy_apb_wr(0x90038,0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + dwc_ddrphy_apb_wr(0x90039,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + dwc_ddrphy_apb_wr(0x9003a,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + dwc_ddrphy_apb_wr(0x9003b,0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + dwc_ddrphy_apb_wr(0x9003c,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + dwc_ddrphy_apb_wr(0x9003d,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + dwc_ddrphy_apb_wr(0x9003e,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + dwc_ddrphy_apb_wr(0x9003f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + dwc_ddrphy_apb_wr(0x90040,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + dwc_ddrphy_apb_wr(0x90041,0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + dwc_ddrphy_apb_wr(0x90042,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + dwc_ddrphy_apb_wr(0x90043,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + dwc_ddrphy_apb_wr(0x90044,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + dwc_ddrphy_apb_wr(0x90045,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + dwc_ddrphy_apb_wr(0x90046,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + dwc_ddrphy_apb_wr(0x90047,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + dwc_ddrphy_apb_wr(0x90048,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + dwc_ddrphy_apb_wr(0x90049,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + dwc_ddrphy_apb_wr(0x9004a,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + dwc_ddrphy_apb_wr(0x9004b,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + dwc_ddrphy_apb_wr(0x9004c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + dwc_ddrphy_apb_wr(0x9004d,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + dwc_ddrphy_apb_wr(0x9004e,0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + dwc_ddrphy_apb_wr(0x9004f,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + dwc_ddrphy_apb_wr(0x90050,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + dwc_ddrphy_apb_wr(0x90051,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + dwc_ddrphy_apb_wr(0x90052,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + dwc_ddrphy_apb_wr(0x90053,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + dwc_ddrphy_apb_wr(0x90054,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + dwc_ddrphy_apb_wr(0x90055,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + dwc_ddrphy_apb_wr(0x90056,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + dwc_ddrphy_apb_wr(0x90057,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + dwc_ddrphy_apb_wr(0x90058,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + dwc_ddrphy_apb_wr(0x90059,0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + dwc_ddrphy_apb_wr(0x9005a,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + dwc_ddrphy_apb_wr(0x9005b,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + dwc_ddrphy_apb_wr(0x9005c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + dwc_ddrphy_apb_wr(0x9005d,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + dwc_ddrphy_apb_wr(0x9005e,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + dwc_ddrphy_apb_wr(0x9005f,0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + dwc_ddrphy_apb_wr(0x90060,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + dwc_ddrphy_apb_wr(0x90061,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + dwc_ddrphy_apb_wr(0x90062,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + dwc_ddrphy_apb_wr(0x90063,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + dwc_ddrphy_apb_wr(0x90064,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + dwc_ddrphy_apb_wr(0x90065,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + dwc_ddrphy_apb_wr(0x90066,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + dwc_ddrphy_apb_wr(0x90067,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + dwc_ddrphy_apb_wr(0x90068,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + dwc_ddrphy_apb_wr(0x90069,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + dwc_ddrphy_apb_wr(0x9006a,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + dwc_ddrphy_apb_wr(0x9006b,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + dwc_ddrphy_apb_wr(0x9006c,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + dwc_ddrphy_apb_wr(0x9006d,0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + dwc_ddrphy_apb_wr(0x9006e,0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + dwc_ddrphy_apb_wr(0x9006f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + dwc_ddrphy_apb_wr(0x90070,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + dwc_ddrphy_apb_wr(0x90071,0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + dwc_ddrphy_apb_wr(0x90072,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + dwc_ddrphy_apb_wr(0x90073,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + dwc_ddrphy_apb_wr(0x90074,0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + dwc_ddrphy_apb_wr(0x90075,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + dwc_ddrphy_apb_wr(0x90076,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + dwc_ddrphy_apb_wr(0x90077,0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + dwc_ddrphy_apb_wr(0x90078,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + dwc_ddrphy_apb_wr(0x90079,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + dwc_ddrphy_apb_wr(0x9007a,0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + dwc_ddrphy_apb_wr(0x9007b,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + dwc_ddrphy_apb_wr(0x9007c,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + dwc_ddrphy_apb_wr(0x9007d,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + dwc_ddrphy_apb_wr(0x9007e,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + dwc_ddrphy_apb_wr(0x9007f,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + dwc_ddrphy_apb_wr(0x90080,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + dwc_ddrphy_apb_wr(0x90081,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + dwc_ddrphy_apb_wr(0x90082,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + dwc_ddrphy_apb_wr(0x90083,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + dwc_ddrphy_apb_wr(0x90084,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + dwc_ddrphy_apb_wr(0x90085,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + dwc_ddrphy_apb_wr(0x90086,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + dwc_ddrphy_apb_wr(0x90087,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + dwc_ddrphy_apb_wr(0x90088,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + dwc_ddrphy_apb_wr(0x90089,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + dwc_ddrphy_apb_wr(0x9008a,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + dwc_ddrphy_apb_wr(0x9008b,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + dwc_ddrphy_apb_wr(0x9008c,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + dwc_ddrphy_apb_wr(0x9008d,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + dwc_ddrphy_apb_wr(0x9008e,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + dwc_ddrphy_apb_wr(0x9008f,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + dwc_ddrphy_apb_wr(0x90090,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + dwc_ddrphy_apb_wr(0x90091,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + dwc_ddrphy_apb_wr(0x90092,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + dwc_ddrphy_apb_wr(0x90093,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + dwc_ddrphy_apb_wr(0x90094,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + dwc_ddrphy_apb_wr(0x90095,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + dwc_ddrphy_apb_wr(0x90096,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + dwc_ddrphy_apb_wr(0x90097,0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + dwc_ddrphy_apb_wr(0x90098,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + dwc_ddrphy_apb_wr(0x90099,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + dwc_ddrphy_apb_wr(0x9009a,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + dwc_ddrphy_apb_wr(0x9009b,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + dwc_ddrphy_apb_wr(0x9009c,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + dwc_ddrphy_apb_wr(0x9009d,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + dwc_ddrphy_apb_wr(0x9009e,0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + dwc_ddrphy_apb_wr(0x9009f,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + dwc_ddrphy_apb_wr(0x900a0,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + dwc_ddrphy_apb_wr(0x900a1,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + dwc_ddrphy_apb_wr(0x900a2,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + dwc_ddrphy_apb_wr(0x900a3,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + dwc_ddrphy_apb_wr(0x900a4,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + dwc_ddrphy_apb_wr(0x900a5,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + dwc_ddrphy_apb_wr(0x900a6,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + dwc_ddrphy_apb_wr(0x900a7,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + dwc_ddrphy_apb_wr(0x900a8,0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + dwc_ddrphy_apb_wr(0x900a9,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + dwc_ddrphy_apb_wr(0x900aa,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + dwc_ddrphy_apb_wr(0x900ab,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + dwc_ddrphy_apb_wr(0x900ac,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + dwc_ddrphy_apb_wr(0x900ad,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + dwc_ddrphy_apb_wr(0x900ae,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + dwc_ddrphy_apb_wr(0x900af,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + dwc_ddrphy_apb_wr(0x900b0,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + dwc_ddrphy_apb_wr(0x900b1,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + dwc_ddrphy_apb_wr(0x900b2,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + dwc_ddrphy_apb_wr(0x900b3,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + dwc_ddrphy_apb_wr(0x900b4,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + dwc_ddrphy_apb_wr(0x900b5,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + dwc_ddrphy_apb_wr(0x900b6,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + dwc_ddrphy_apb_wr(0x900b7,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + dwc_ddrphy_apb_wr(0x900b8,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + dwc_ddrphy_apb_wr(0x900b9,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + dwc_ddrphy_apb_wr(0x900ba,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + dwc_ddrphy_apb_wr(0x900bb,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + dwc_ddrphy_apb_wr(0x900bc,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + dwc_ddrphy_apb_wr(0x900bd,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + dwc_ddrphy_apb_wr(0x900be,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + dwc_ddrphy_apb_wr(0x900bf,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + dwc_ddrphy_apb_wr(0x900c0,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + dwc_ddrphy_apb_wr(0x900c1,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + dwc_ddrphy_apb_wr(0x900c2,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + dwc_ddrphy_apb_wr(0x900c3,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + dwc_ddrphy_apb_wr(0x900c4,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + dwc_ddrphy_apb_wr(0x900c5,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + dwc_ddrphy_apb_wr(0x900c6,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + dwc_ddrphy_apb_wr(0x900c7,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + dwc_ddrphy_apb_wr(0x900c8,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + dwc_ddrphy_apb_wr(0x900c9,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + dwc_ddrphy_apb_wr(0x900ca,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + dwc_ddrphy_apb_wr(0x900cb,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + dwc_ddrphy_apb_wr(0x900cc,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + dwc_ddrphy_apb_wr(0x900cd,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + dwc_ddrphy_apb_wr(0x90006,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90007,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90008,0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90009,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9000a,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9000b,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0xd00e7,0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + dwc_ddrphy_apb_wr(0x90017,0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + dwc_ddrphy_apb_wr(0x90026,0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + dwc_ddrphy_apb_wr(0x9000c,0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + dwc_ddrphy_apb_wr(0x9000d,0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + dwc_ddrphy_apb_wr(0x9000e,0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + dwc_ddrphy_apb_wr(0x9000f,0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + dwc_ddrphy_apb_wr(0x90010,0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + dwc_ddrphy_apb_wr(0x90011,0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + dwc_ddrphy_apb_wr(0x90012,0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + dwc_ddrphy_apb_wr(0x90013,0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + dwc_ddrphy_apb_wr(0xc0080,0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +} diff --git a/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c b/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c new file mode 100644 index 0000000000..bb6c90a203 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c @@ -0,0 +1,226 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr_memory_map.h> +#include <asm/arch/clock.h> +#include "../ddr.h" + +#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG +#define ddr_printf(args...) printf(args) +#else +#define ddr_printf(args...) +#endif + +#include "../wait_ddrphy_training_complete.c" + +volatile unsigned int tmp, tmp_t; +void umctl2_cfg(void){ + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + tmp = reg32_read(DDRC_STAT(0)); + while (tmp_t == 0x00000001){ + tmp = reg32_read(DDRC_STAT(0)); + tmp_t = tmp && 0x00000001; + } + + reg32_write(DDRC_MSTR(0), 0x83040010); /* Two ranks */ + + reg32_write(DDRC_MRCTRL0(0), 0x40007030); + reg32_write(DDRC_MRCTRL1(0), 0x000170df); + reg32_write(DDRC_MRCTRL2(0), 0x97d37be3); + reg32_write(DDRC_DERATEEN(0), 0x00000302); + reg32_write(DDRC_DERATEINT(0), 0xbc808cc7); + reg32_write(DDRC_MSTR2(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x000001ae); + reg32_write(DDRC_PWRTMG(0), 0x000d2800); + reg32_write(DDRC_HWLPCTL(0), 0x000c0000); + reg32_write(DDRC_HWFFCCTL(0), 0x00000010); + reg32_write(DDRC_RFSHCTL0(0), 0x007090b0); + reg32_write(DDRC_RFSHCTL1(0), 0x00420019); + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); + reg32_write(DDRC_RFSHTMG(0), 0x0049009d); + reg32_write(DDRC_CRCPARCTL0(0), 0x00000000); + reg32_write(DDRC_CRCPARCTL1(0), 0x00001011); + reg32_write(DDRC_INIT0(0), 0xc0030002); + reg32_write(DDRC_INIT1(0), 0x00030006); + reg32_write(DDRC_INIT2(0), 0x00000305); + reg32_write(DDRC_INIT3(0), 0x0a300001); + reg32_write(DDRC_INIT4(0), 0x10180240); + reg32_write(DDRC_INIT5(0), 0x0011008a); + reg32_write(DDRC_INIT6(0), 0x0a000042); + reg32_write(DDRC_INIT7(0), 0x00000800); + reg32_write(DDRC_DIMMCTL(0), 0x00000032); /* [1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram. */ + reg32_write(DDRC_RANKCTL(0), 0x00000530); + reg32_write(DDRC_DRAMTMG0(0), 0x14132813); + reg32_write(DDRC_DRAMTMG1(0), 0x0007051b); + reg32_write(DDRC_DRAMTMG2(0), 0x090a050f); + reg32_write(DDRC_DRAMTMG3(0), 0x0000f00f); + reg32_write(DDRC_DRAMTMG4(0), 0x08030409); + reg32_write(DDRC_DRAMTMG5(0), 0x0c0d0504); + reg32_write(DDRC_DRAMTMG6(0), 0x00000003); + reg32_write(DDRC_DRAMTMG7(0), 0x00000d0c); + reg32_write(DDRC_DRAMTMG8(0), 0x05051f09); + reg32_write(DDRC_DRAMTMG9(0), 0x0002040c); + reg32_write(DDRC_DRAMTMG10(0), 0x000e0d0b); + reg32_write(DDRC_DRAMTMG11(0), 0x1409011e); + reg32_write(DDRC_DRAMTMG12(0), 0x0000000d); + reg32_write(DDRC_DRAMTMG13(0), 0x09000000); + reg32_write(DDRC_DRAMTMG14(0), 0x00000371); + reg32_write(DDRC_DRAMTMG15(0), 0x80000000); + reg32_write(DDRC_DRAMTMG17(0), 0x0076006e); + reg32_write(DDRC_ZQCTL0(0), 0x51000040); + reg32_write(DDRC_ZQCTL1(0), 0x00000070); + reg32_write(DDRC_ZQCTL2(0), 0x00000000); + reg32_write(DDRC_DFITMG0(0), 0x038f820c); + reg32_write(DDRC_DFITMG1(0), 0x00020103); + reg32_write(DDRC_DFILPCFG0(0), 0x07e1b011); + reg32_write(DDRC_DFILPCFG1(0), 0x00000030); + reg32_write(DDRC_DFIUPD0(0), 0xe0400018); + reg32_write(DDRC_DFIUPD1(0), 0x004e00c3); + reg32_write(DDRC_DFIUPD2(0), 0x00000000); + reg32_write(DDRC_DFIMISC(0), 0x00000001); + reg32_write(DDRC_DFITMG2(0), 0x00000f0c); + reg32_write(DDRC_DFITMG3(0), 0x00000001); + reg32_write(DDRC_DBICTL(0), 0x00000000); + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000); + + reg32_write(DDRC_ADDRMAP0(0), 0x00001F17); /* [4:0]cs0: 6+23 */ + reg32_write(DDRC_ADDRMAP1(0), 0x003F0808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+, unused */ + reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2; [11:8] col-b3: 3+0; [19:16] col-b4: 4+0 ; [27:24] col-b5: 5+0 */ + reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6+0; [11:8] col-b7: 7+0; [19:16] col-b8: 8+0 ; [27:24] col-b9: 9+0 */ + reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6+7; [11:8] row-b1: 7+7; [19:16] row-b2_b10: 8~16+7; [27:24] row-b11: 17+7 */ + reg32_write(DDRC_ADDRMAP6(0), 0x07070707); /* [3:0] row-b12:18+7; [11:8] row-b13: 19+7; [19:16] row-b14:20+7 */ + reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP8(0), 0x00003F0A); /* [5:0] bg-b0: 2+10; [13:8]bg-b1:3+, unused */ + reg32_write(DDRC_ADDRMAP9(0), 0x00000000); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP10(0), 0x00000000);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP11(0), 0x00000000); + + + reg32_write(DDRC_ODTCFG(0), 0x05170558); + reg32_write(DDRC_ODTMAP(0), 0x00002113); + reg32_write(DDRC_SCHED(0), 0x0d6f0705); + reg32_write(DDRC_SCHED1(0), 0x00000000); + reg32_write(DDRC_PERFHPR1(0), 0xe500558b); + reg32_write(DDRC_PERFLPR1(0), 0x75001fea); + reg32_write(DDRC_PERFWR1(0), 0x880026c7); + reg32_write(DDRC_DBG0(0), 0x00000011); + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_DBGCMD(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x00000001); + reg32_write(DDRC_POISONCFG(0), 0x00100011); + reg32_write(DDRC_PCCFG(0), 0x00000100); + reg32_write(DDRC_PCFGR_0(0), 0x00015313); + reg32_write(DDRC_PCFGW_0(0), 0x000050dc); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + reg32_write(DDRC_PCFGQOS0_0(0), 0x01100200); + reg32_write(DDRC_PCFGQOS1_0(0), 0x01ba023a); + reg32_write(DDRC_PCFGWQOS0_0(0), 0x00110000); + reg32_write(DDRC_PCFGWQOS1_0(0), 0x0000001e); +} + +void ddr_init(void) +{ + /* change the clock source of dram_apb_clk_root */ + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16)); + + /* disable the clock gating */ + reg32_write(0x303A00EC,0x0000ffff); + reg32setbit(0x303A00F8,5); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + + dram_pll_init(SSCG_PLL_OUT_600M); + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /* Configure uMCTL2's registers */ + umctl2_cfg(); + + tmp = reg32_read(DDRC_RFSHCTL3(0)); + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + ddr_load_train_code(FW_1D_IMAGE); + + reg32_write(DDRC_DBG1(0), 0x00000000); + tmp = reg32_read(DDRC_PWRCTL(0)); + reg32_write(DDRC_PWRCTL(0), 0x000001ae); + tmp = reg32_read(DDRC_PWRCTL(0)); + reg32_write(DDRC_PWRCTL(0), 0x000001ac); + reg32_write(DDRC_SWCTL(0), 0x00000000); + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + + reg32_write(DDRC_DFIMISC(0), 0x00000000); + reg32_write(DDRC_DFIMISC(0), 0x00000000); + + tmp = reg32_read(DDRC_DBICTL(0)); + tmp = reg32_read(DDRC_MSTR(0)); + tmp = reg32_read(DDRC_INIT3(0)); + tmp = reg32_read(DDRC_INIT4(0)); + tmp = reg32_read(DDRC_INIT6(0)); + tmp = reg32_read(DDRC_INIT7(0)); + tmp = reg32_read(DDRC_INIT0(0)); + + ddr4_phyinit_train_2400mts(); + + do { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*0x00020097); + } while (tmp_t != 0); + + + reg32_write(DDRC_DFIMISC(0), 0x00000020); + + /* wait DFISTAT.dfi_init_complete to 1 */ + tmp_t = 0; + while(tmp_t == 0){ + tmp = reg32_read(DDRC_DFISTAT(0)); + tmp_t = tmp & 0x01; + } + + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000000); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x0000018c); + + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset .*/ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* wait SWSTAT.sw_done_ack to 1 */ + tmp_t = 0; + while(tmp_t==0){ + tmp = reg32_read(DDRC_SWSTAT(0)); + tmp_t = tmp & 0x01; + } + + /* wait STAT to normal state */ + tmp_t = 0; + while(tmp_t==0){ + tmp = reg32_read(DDRC_STAT(0)); + tmp_t = tmp & 0x01; + } + + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + + reg32_write(DDRC_PWRCTL(0), 0x0000018c); + + reg32_write(DDRC_DERATEEN(0), 0x00000302); + + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); /* dis_auto-refresh is set to 0 */ + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0xd0000), 0); + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54030)); + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54035)); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0xd0000), 1); +} diff --git a/board/freescale/imx8mq_arm2/ddr/ddr4/ddrphy_train.c b/board/freescale/imx8mq_arm2/ddr/ddr4/ddrphy_train.c new file mode 100644 index 0000000000..18e2c49c51 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/ddr4/ddrphy_train.c @@ -0,0 +1,1366 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr_memory_map.h> +#include "../ddr.h" + +#define DDR_RON 2 +#define PHY_RTT 48 +#define PHYREF_VALUE 0x3b + +#define PHY_RON 40 +#define DDR_RTT 5 +#define MR6_VALUE 0x1f + + +#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr), data) +#define dwc_ddrphy_apb_rd(addr) (reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr))) + +void ddr4_phyinit_train_2400mts(){ + dwc_ddrphy_apb_wr(0x1005f,0x2ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1015f,0x2ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1105f,0x2ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1115f,0x2ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1205f,0x2ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1215f,0x2ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1305f,0x2ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1315f,0x2ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ + + dwc_ddrphy_apb_wr(0x55,0x3ff); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x1055,0x3ff); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x2055,0x3ff); /* DWC_DDRPHYA_ANIB2_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x3055,0x3ff); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x4055,0xff); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x5055,0xff); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x6055,0x3ff); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x7055,0x3ff); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x8055,0x3ff); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ + + dwc_ddrphy_apb_wr(0x9055,0x3ff); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x200c5,0xa); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ + dwc_ddrphy_apb_wr(0x2002e,0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ + dwc_ddrphy_apb_wr(0x20024,0x9); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ + dwc_ddrphy_apb_wr(0x2003a,0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + dwc_ddrphy_apb_wr(0x20056,0x2); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ + dwc_ddrphy_apb_wr(0x1004d,0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1014d,0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1104d,0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1114d,0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1204d,0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1214d,0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1304d,0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1314d,0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x10049,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x10149,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x11049,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x11149,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x12049,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x12149,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x13049,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x13149,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x43,0x3ff); /* DWC_DDRPHYA_ANIB0_ATxImpedance */ + dwc_ddrphy_apb_wr(0x1043,0x3ff); /* DWC_DDRPHYA_ANIB1_ATxImpedance */ + dwc_ddrphy_apb_wr(0x2043,0x3ff); /* DWC_DDRPHYA_ANIB2_ATxImpedance */ + dwc_ddrphy_apb_wr(0x3043,0x3ff); /* DWC_DDRPHYA_ANIB3_ATxImpedance */ + dwc_ddrphy_apb_wr(0x4043,0x3ff); /* DWC_DDRPHYA_ANIB4_ATxImpedance */ + dwc_ddrphy_apb_wr(0x5043,0x3ff); /* DWC_DDRPHYA_ANIB5_ATxImpedance */ + dwc_ddrphy_apb_wr(0x6043,0x3ff); /* DWC_DDRPHYA_ANIB6_ATxImpedance */ + dwc_ddrphy_apb_wr(0x7043,0x3ff); /* DWC_DDRPHYA_ANIB7_ATxImpedance */ + dwc_ddrphy_apb_wr(0x8043,0x3ff); /* DWC_DDRPHYA_ANIB8_ATxImpedance */ + dwc_ddrphy_apb_wr(0x9043,0x3ff); /* DWC_DDRPHYA_ANIB9_ATxImpedance */ + dwc_ddrphy_apb_wr(0x20018,0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */ + dwc_ddrphy_apb_wr(0x20075,0x2); /* DWC_DDRPHYA_MASTER0_DfiCAMode */ + dwc_ddrphy_apb_wr(0x20050,0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ + dwc_ddrphy_apb_wr(0x20008,0x258); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ + dwc_ddrphy_apb_wr(0x20088,0x9); /* DWC_DDRPHYA_MASTER0_CalRate */ + dwc_ddrphy_apb_wr(0x200b2,0x288); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ + dwc_ddrphy_apb_wr(0x10043,0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x10143,0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x11043,0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x11143,0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x12043,0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x12143,0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x13043,0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x13143,0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x200fa,0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ + dwc_ddrphy_apb_wr(0x20019,0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ + dwc_ddrphy_apb_wr(0x200f0,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ + dwc_ddrphy_apb_wr(0x200f1,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ + dwc_ddrphy_apb_wr(0x200f2,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ + dwc_ddrphy_apb_wr(0x200f3,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ + dwc_ddrphy_apb_wr(0x200f4,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ + dwc_ddrphy_apb_wr(0x200f5,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ + dwc_ddrphy_apb_wr(0x200f6,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ + dwc_ddrphy_apb_wr(0x200f7,0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ + dwc_ddrphy_apb_wr(0x2000b,0x4c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + dwc_ddrphy_apb_wr(0x2000c,0x97); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + dwc_ddrphy_apb_wr(0x2000d,0x5dd); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + dwc_ddrphy_apb_wr(0x2000e,0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + dwc_ddrphy_apb_wr(0x20025,0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */ + dwc_ddrphy_apb_wr(0x2002d,0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */ + dwc_ddrphy_apb_wr(0x20060,0x2); /* DWC_DDRPHYA_MASTER0_MemResetL */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x54000,0x80);/* should be 0x80 in silicon */ + dwc_ddrphy_apb_wr(0x54001,0x0); + dwc_ddrphy_apb_wr(0x54002,0x0); + dwc_ddrphy_apb_wr(0x54003,0x960); + dwc_ddrphy_apb_wr(0x54004,0x2); + + dwc_ddrphy_apb_wr(0x54005,((PHY_RON<<8)|(PHY_RTT<<0))/*0x2830*/); + dwc_ddrphy_apb_wr(0x54006,(0x200|PHYREF_VALUE)/*0x23b*/); + dwc_ddrphy_apb_wr(0x54007,0x2000); + + dwc_ddrphy_apb_wr(0x54008,0x303); /* Two ranks */ + + dwc_ddrphy_apb_wr(0x54009,0x200);/* no addr mirror, 0x200 addr mirror */ + dwc_ddrphy_apb_wr(0x5400a,0x0); + dwc_ddrphy_apb_wr(0x5400b,0x31f);/* should be 0x31f in silicon */ + + dwc_ddrphy_apb_wr(0x5400c,0xc8); /* 0xc8 indicates stage completion messages showed */ + + dwc_ddrphy_apb_wr(0x5400d,0x0); + dwc_ddrphy_apb_wr(0x5400e,0x0); + dwc_ddrphy_apb_wr(0x5400f,0x0); + dwc_ddrphy_apb_wr(0x54010,0x0); + dwc_ddrphy_apb_wr(0x54011,0x0); + dwc_ddrphy_apb_wr(0x54012,0x1); + dwc_ddrphy_apb_wr(0x54013,0x0); + dwc_ddrphy_apb_wr(0x54014,0x0); + dwc_ddrphy_apb_wr(0x54015,0x0); + dwc_ddrphy_apb_wr(0x54016,0x0); + dwc_ddrphy_apb_wr(0x54017,0x0); + dwc_ddrphy_apb_wr(0x54018,0x0); + dwc_ddrphy_apb_wr(0x54019,0x0); + dwc_ddrphy_apb_wr(0x5401a,0x0); + dwc_ddrphy_apb_wr(0x5401b,0x0); + dwc_ddrphy_apb_wr(0x5401c,0x0); + dwc_ddrphy_apb_wr(0x5401d,0x0); + dwc_ddrphy_apb_wr(0x5401e,0x0); + dwc_ddrphy_apb_wr(0x5401f,0x0); + dwc_ddrphy_apb_wr(0x54020,0x0); + dwc_ddrphy_apb_wr(0x54021,0x0); + dwc_ddrphy_apb_wr(0x54022,0x0); + dwc_ddrphy_apb_wr(0x54023,0x0); + dwc_ddrphy_apb_wr(0x54024,0x0); + dwc_ddrphy_apb_wr(0x54025,0x0); + dwc_ddrphy_apb_wr(0x54026,0x0); + dwc_ddrphy_apb_wr(0x54027,0x0); + dwc_ddrphy_apb_wr(0x54028,0x0); + dwc_ddrphy_apb_wr(0x54029,0x0); + dwc_ddrphy_apb_wr(0x5402a,0x0); + dwc_ddrphy_apb_wr(0x5402b,0x0); + dwc_ddrphy_apb_wr(0x5402c,0x0); + dwc_ddrphy_apb_wr(0x5402d,0x0); + dwc_ddrphy_apb_wr(0x5402e,0x0); + + dwc_ddrphy_apb_wr(0x5402f,0xa30);/* MR0 */ + dwc_ddrphy_apb_wr(0x54030, ((DDR_RTT<<8)|(DDR_RON<<1)|0x1)/*0x1*/);/* MR1 */ + dwc_ddrphy_apb_wr(0x54031,0x1018);/* MR2 */ + dwc_ddrphy_apb_wr(0x54032,0x240);/* MR3 */ + dwc_ddrphy_apb_wr(0x54033,0xa00);/* MR4 */ + dwc_ddrphy_apb_wr(0x54034,0x42);/* MR5 */ + dwc_ddrphy_apb_wr(0x54035,(0x800|MR6_VALUE)/*0x800*/);/* MR6 */ + + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54030)); + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54035)); + + dwc_ddrphy_apb_wr(0x54036,0x103); + dwc_ddrphy_apb_wr(0x54037,0x0); + dwc_ddrphy_apb_wr(0x54038,0x0); + dwc_ddrphy_apb_wr(0x54039,0x0); + dwc_ddrphy_apb_wr(0x5403a,0x0); + dwc_ddrphy_apb_wr(0x5403b,0x0); + dwc_ddrphy_apb_wr(0x5403c,0x0); + dwc_ddrphy_apb_wr(0x5403d,0x0); + dwc_ddrphy_apb_wr(0x5403e,0x0); + dwc_ddrphy_apb_wr(0x5403f,0x1221); + dwc_ddrphy_apb_wr(0x54040,0x0); + dwc_ddrphy_apb_wr(0x54041,0x0); + dwc_ddrphy_apb_wr(0x54042,0x0); + dwc_ddrphy_apb_wr(0x54043,0x0); + dwc_ddrphy_apb_wr(0x54044,0x0); + dwc_ddrphy_apb_wr(0x54045,0x0); + dwc_ddrphy_apb_wr(0x54046,0x0); + dwc_ddrphy_apb_wr(0x54047,0x0); + dwc_ddrphy_apb_wr(0x54048,0x0); + dwc_ddrphy_apb_wr(0x54049,0x0); + dwc_ddrphy_apb_wr(0x5404a,0x0); + dwc_ddrphy_apb_wr(0x5404b,0x0); + dwc_ddrphy_apb_wr(0x5404c,0x0); + dwc_ddrphy_apb_wr(0x5404d,0x0); + dwc_ddrphy_apb_wr(0x5404e,0x0); + dwc_ddrphy_apb_wr(0x5404f,0x0); + dwc_ddrphy_apb_wr(0x54050,0x0); + dwc_ddrphy_apb_wr(0x54051,0x0); + dwc_ddrphy_apb_wr(0x54052,0x0); + dwc_ddrphy_apb_wr(0x54053,0x0); + dwc_ddrphy_apb_wr(0x54054,0x0); + dwc_ddrphy_apb_wr(0x54055,0x0); + dwc_ddrphy_apb_wr(0x54056,0x0); + dwc_ddrphy_apb_wr(0x54057,0x0); + dwc_ddrphy_apb_wr(0x54058,0x0); + dwc_ddrphy_apb_wr(0x54059,0x0); + dwc_ddrphy_apb_wr(0x5405a,0x0); + dwc_ddrphy_apb_wr(0x5405b,0x0); + dwc_ddrphy_apb_wr(0x5405c,0x0); + dwc_ddrphy_apb_wr(0x5405d,0x0); + dwc_ddrphy_apb_wr(0x5405e,0x0); + dwc_ddrphy_apb_wr(0x5405f,0x0); + dwc_ddrphy_apb_wr(0x54060,0x0); + dwc_ddrphy_apb_wr(0x54061,0x0); + dwc_ddrphy_apb_wr(0x54062,0x0); + dwc_ddrphy_apb_wr(0x54063,0x0); + dwc_ddrphy_apb_wr(0x54064,0x0); + dwc_ddrphy_apb_wr(0x54065,0x0); + dwc_ddrphy_apb_wr(0x54066,0x0); + dwc_ddrphy_apb_wr(0x54067,0x0); + dwc_ddrphy_apb_wr(0x54068,0x0); + dwc_ddrphy_apb_wr(0x54069,0x0); + dwc_ddrphy_apb_wr(0x5406a,0x0); + dwc_ddrphy_apb_wr(0x5406b,0x0); + dwc_ddrphy_apb_wr(0x5406c,0x0); + dwc_ddrphy_apb_wr(0x5406d,0x0); + dwc_ddrphy_apb_wr(0x5406e,0x0); + dwc_ddrphy_apb_wr(0x5406f,0x0); + dwc_ddrphy_apb_wr(0x54070,0x0); + dwc_ddrphy_apb_wr(0x54071,0x0); + dwc_ddrphy_apb_wr(0x54072,0x0); + dwc_ddrphy_apb_wr(0x54073,0x0); + dwc_ddrphy_apb_wr(0x54074,0x0); + dwc_ddrphy_apb_wr(0x54075,0x0); + dwc_ddrphy_apb_wr(0x54076,0x0); + dwc_ddrphy_apb_wr(0x54077,0x0); + dwc_ddrphy_apb_wr(0x54078,0x0); + dwc_ddrphy_apb_wr(0x54079,0x0); + dwc_ddrphy_apb_wr(0x5407a,0x0); + dwc_ddrphy_apb_wr(0x5407b,0x0); + dwc_ddrphy_apb_wr(0x5407c,0x0); + dwc_ddrphy_apb_wr(0x5407d,0x0); + dwc_ddrphy_apb_wr(0x5407e,0x0); + dwc_ddrphy_apb_wr(0x5407f,0x0); + dwc_ddrphy_apb_wr(0x54080,0x0); + dwc_ddrphy_apb_wr(0x54081,0x0); + dwc_ddrphy_apb_wr(0x54082,0x0); + dwc_ddrphy_apb_wr(0x54083,0x0); + dwc_ddrphy_apb_wr(0x54084,0x0); + dwc_ddrphy_apb_wr(0x54085,0x0); + dwc_ddrphy_apb_wr(0x54086,0x0); + dwc_ddrphy_apb_wr(0x54087,0x0); + dwc_ddrphy_apb_wr(0x54088,0x0); + dwc_ddrphy_apb_wr(0x54089,0x0); + dwc_ddrphy_apb_wr(0x5408a,0x0); + dwc_ddrphy_apb_wr(0x5408b,0x0); + dwc_ddrphy_apb_wr(0x5408c,0x0); + dwc_ddrphy_apb_wr(0x5408d,0x0); + dwc_ddrphy_apb_wr(0x5408e,0x0); + dwc_ddrphy_apb_wr(0x5408f,0x0); + dwc_ddrphy_apb_wr(0x54090,0x0); + dwc_ddrphy_apb_wr(0x54091,0x0); + dwc_ddrphy_apb_wr(0x54092,0x0); + dwc_ddrphy_apb_wr(0x54093,0x0); + dwc_ddrphy_apb_wr(0x54094,0x0); + dwc_ddrphy_apb_wr(0x54095,0x0); + dwc_ddrphy_apb_wr(0x54096,0x0); + dwc_ddrphy_apb_wr(0x54097,0x0); + dwc_ddrphy_apb_wr(0x54098,0x0); + dwc_ddrphy_apb_wr(0x54099,0x0); + dwc_ddrphy_apb_wr(0x5409a,0x0); + dwc_ddrphy_apb_wr(0x5409b,0x0); + dwc_ddrphy_apb_wr(0x5409c,0x0); + dwc_ddrphy_apb_wr(0x5409d,0x0); + dwc_ddrphy_apb_wr(0x5409e,0x0); + dwc_ddrphy_apb_wr(0x5409f,0x0); + dwc_ddrphy_apb_wr(0x540a0,0x0); + dwc_ddrphy_apb_wr(0x540a1,0x0); + dwc_ddrphy_apb_wr(0x540a2,0x0); + dwc_ddrphy_apb_wr(0x540a3,0x0); + dwc_ddrphy_apb_wr(0x540a4,0x0); + dwc_ddrphy_apb_wr(0x540a5,0x0); + dwc_ddrphy_apb_wr(0x540a6,0x0); + dwc_ddrphy_apb_wr(0x540a7,0x0); + dwc_ddrphy_apb_wr(0x540a8,0x0); + dwc_ddrphy_apb_wr(0x540a9,0x0); + dwc_ddrphy_apb_wr(0x540aa,0x0); + dwc_ddrphy_apb_wr(0x540ab,0x0); + dwc_ddrphy_apb_wr(0x540ac,0x0); + dwc_ddrphy_apb_wr(0x540ad,0x0); + dwc_ddrphy_apb_wr(0x540ae,0x0); + dwc_ddrphy_apb_wr(0x540af,0x0); + dwc_ddrphy_apb_wr(0x540b0,0x0); + dwc_ddrphy_apb_wr(0x540b1,0x0); + dwc_ddrphy_apb_wr(0x540b2,0x0); + dwc_ddrphy_apb_wr(0x540b3,0x0); + dwc_ddrphy_apb_wr(0x540b4,0x0); + dwc_ddrphy_apb_wr(0x540b5,0x0); + dwc_ddrphy_apb_wr(0x540b6,0x0); + dwc_ddrphy_apb_wr(0x540b7,0x0); + dwc_ddrphy_apb_wr(0x540b8,0x0); + dwc_ddrphy_apb_wr(0x540b9,0x0); + dwc_ddrphy_apb_wr(0x540ba,0x0); + dwc_ddrphy_apb_wr(0x540bb,0x0); + dwc_ddrphy_apb_wr(0x540bc,0x0); + dwc_ddrphy_apb_wr(0x540bd,0x0); + dwc_ddrphy_apb_wr(0x540be,0x0); + dwc_ddrphy_apb_wr(0x540bf,0x0); + dwc_ddrphy_apb_wr(0x540c0,0x0); + dwc_ddrphy_apb_wr(0x540c1,0x0); + dwc_ddrphy_apb_wr(0x540c2,0x0); + dwc_ddrphy_apb_wr(0x540c3,0x0); + dwc_ddrphy_apb_wr(0x540c4,0x0); + dwc_ddrphy_apb_wr(0x540c5,0x0); + dwc_ddrphy_apb_wr(0x540c6,0x0); + dwc_ddrphy_apb_wr(0x540c7,0x0); + dwc_ddrphy_apb_wr(0x540c8,0x0); + dwc_ddrphy_apb_wr(0x540c9,0x0); + dwc_ddrphy_apb_wr(0x540ca,0x0); + dwc_ddrphy_apb_wr(0x540cb,0x0); + dwc_ddrphy_apb_wr(0x540cc,0x0); + dwc_ddrphy_apb_wr(0x540cd,0x0); + dwc_ddrphy_apb_wr(0x540ce,0x0); + dwc_ddrphy_apb_wr(0x540cf,0x0); + dwc_ddrphy_apb_wr(0x540d0,0x0); + dwc_ddrphy_apb_wr(0x540d1,0x0); + dwc_ddrphy_apb_wr(0x540d2,0x0); + dwc_ddrphy_apb_wr(0x540d3,0x0); + dwc_ddrphy_apb_wr(0x540d4,0x0); + dwc_ddrphy_apb_wr(0x540d5,0x0); + dwc_ddrphy_apb_wr(0x540d6,0x0); + dwc_ddrphy_apb_wr(0x540d7,0x0); + dwc_ddrphy_apb_wr(0x540d8,0x0); + dwc_ddrphy_apb_wr(0x540d9,0x0); + dwc_ddrphy_apb_wr(0x540da,0x0); + dwc_ddrphy_apb_wr(0x540db,0x0); + dwc_ddrphy_apb_wr(0x540dc,0x0); + dwc_ddrphy_apb_wr(0x540dd,0x0); + dwc_ddrphy_apb_wr(0x540de,0x0); + dwc_ddrphy_apb_wr(0x540df,0x0); + dwc_ddrphy_apb_wr(0x540e0,0x0); + dwc_ddrphy_apb_wr(0x540e1,0x0); + dwc_ddrphy_apb_wr(0x540e2,0x0); + dwc_ddrphy_apb_wr(0x540e3,0x0); + dwc_ddrphy_apb_wr(0x540e4,0x0); + dwc_ddrphy_apb_wr(0x540e5,0x0); + dwc_ddrphy_apb_wr(0x540e6,0x0); + dwc_ddrphy_apb_wr(0x540e7,0x0); + dwc_ddrphy_apb_wr(0x540e8,0x0); + dwc_ddrphy_apb_wr(0x540e9,0x0); + dwc_ddrphy_apb_wr(0x540ea,0x0); + dwc_ddrphy_apb_wr(0x540eb,0x0); + dwc_ddrphy_apb_wr(0x540ec,0x0); + dwc_ddrphy_apb_wr(0x540ed,0x0); + dwc_ddrphy_apb_wr(0x540ee,0x0); + dwc_ddrphy_apb_wr(0x540ef,0x0); + dwc_ddrphy_apb_wr(0x540f0,0x0); + dwc_ddrphy_apb_wr(0x540f1,0x0); + dwc_ddrphy_apb_wr(0x540f2,0x0); + dwc_ddrphy_apb_wr(0x540f3,0x0); + dwc_ddrphy_apb_wr(0x540f4,0x0); + dwc_ddrphy_apb_wr(0x540f5,0x0); + dwc_ddrphy_apb_wr(0x540f6,0x0); + dwc_ddrphy_apb_wr(0x540f7,0x0); + dwc_ddrphy_apb_wr(0x540f8,0x0); + dwc_ddrphy_apb_wr(0x540f9,0x0); + dwc_ddrphy_apb_wr(0x540fa,0x0); + dwc_ddrphy_apb_wr(0x540fb,0x0); + dwc_ddrphy_apb_wr(0x540fc,0x0); + dwc_ddrphy_apb_wr(0x540fd,0x0); + dwc_ddrphy_apb_wr(0x540fe,0x0); + dwc_ddrphy_apb_wr(0x540ff,0x0); + dwc_ddrphy_apb_wr(0x54100,0x0); + dwc_ddrphy_apb_wr(0x54101,0x0); + dwc_ddrphy_apb_wr(0x54102,0x0); + dwc_ddrphy_apb_wr(0x54103,0x0); + dwc_ddrphy_apb_wr(0x54104,0x0); + dwc_ddrphy_apb_wr(0x54105,0x0); + dwc_ddrphy_apb_wr(0x54106,0x0); + dwc_ddrphy_apb_wr(0x54107,0x0); + dwc_ddrphy_apb_wr(0x54108,0x0); + dwc_ddrphy_apb_wr(0x54109,0x0); + dwc_ddrphy_apb_wr(0x5410a,0x0); + dwc_ddrphy_apb_wr(0x5410b,0x0); + dwc_ddrphy_apb_wr(0x5410c,0x0); + dwc_ddrphy_apb_wr(0x5410d,0x0); + dwc_ddrphy_apb_wr(0x5410e,0x0); + dwc_ddrphy_apb_wr(0x5410f,0x0); + dwc_ddrphy_apb_wr(0x54110,0x0); + dwc_ddrphy_apb_wr(0x54111,0x0); + dwc_ddrphy_apb_wr(0x54112,0x0); + dwc_ddrphy_apb_wr(0x54113,0x0); + dwc_ddrphy_apb_wr(0x54114,0x0); + dwc_ddrphy_apb_wr(0x54115,0x0); + dwc_ddrphy_apb_wr(0x54116,0x0); + dwc_ddrphy_apb_wr(0x54117,0x0); + dwc_ddrphy_apb_wr(0x54118,0x0); + dwc_ddrphy_apb_wr(0x54119,0x0); + dwc_ddrphy_apb_wr(0x5411a,0x0); + dwc_ddrphy_apb_wr(0x5411b,0x0); + dwc_ddrphy_apb_wr(0x5411c,0x0); + dwc_ddrphy_apb_wr(0x5411d,0x0); + dwc_ddrphy_apb_wr(0x5411e,0x0); + dwc_ddrphy_apb_wr(0x5411f,0x0); + dwc_ddrphy_apb_wr(0x54120,0x0); + dwc_ddrphy_apb_wr(0x54121,0x0); + dwc_ddrphy_apb_wr(0x54122,0x0); + dwc_ddrphy_apb_wr(0x54123,0x0); + dwc_ddrphy_apb_wr(0x54124,0x0); + dwc_ddrphy_apb_wr(0x54125,0x0); + dwc_ddrphy_apb_wr(0x54126,0x0); + dwc_ddrphy_apb_wr(0x54127,0x0); + dwc_ddrphy_apb_wr(0x54128,0x0); + dwc_ddrphy_apb_wr(0x54129,0x0); + dwc_ddrphy_apb_wr(0x5412a,0x0); + dwc_ddrphy_apb_wr(0x5412b,0x0); + dwc_ddrphy_apb_wr(0x5412c,0x0); + dwc_ddrphy_apb_wr(0x5412d,0x0); + dwc_ddrphy_apb_wr(0x5412e,0x0); + dwc_ddrphy_apb_wr(0x5412f,0x0); + dwc_ddrphy_apb_wr(0x54130,0x0); + dwc_ddrphy_apb_wr(0x54131,0x0); + dwc_ddrphy_apb_wr(0x54132,0x0); + dwc_ddrphy_apb_wr(0x54133,0x0); + dwc_ddrphy_apb_wr(0x54134,0x0); + dwc_ddrphy_apb_wr(0x54135,0x0); + dwc_ddrphy_apb_wr(0x54136,0x0); + dwc_ddrphy_apb_wr(0x54137,0x0); + dwc_ddrphy_apb_wr(0x54138,0x0); + dwc_ddrphy_apb_wr(0x54139,0x0); + dwc_ddrphy_apb_wr(0x5413a,0x0); + dwc_ddrphy_apb_wr(0x5413b,0x0); + dwc_ddrphy_apb_wr(0x5413c,0x0); + dwc_ddrphy_apb_wr(0x5413d,0x0); + dwc_ddrphy_apb_wr(0x5413e,0x0); + dwc_ddrphy_apb_wr(0x5413f,0x0); + dwc_ddrphy_apb_wr(0x54140,0x0); + dwc_ddrphy_apb_wr(0x54141,0x0); + dwc_ddrphy_apb_wr(0x54142,0x0); + dwc_ddrphy_apb_wr(0x54143,0x0); + dwc_ddrphy_apb_wr(0x54144,0x0); + dwc_ddrphy_apb_wr(0x54145,0x0); + dwc_ddrphy_apb_wr(0x54146,0x0); + dwc_ddrphy_apb_wr(0x54147,0x0); + dwc_ddrphy_apb_wr(0x54148,0x0); + dwc_ddrphy_apb_wr(0x54149,0x0); + dwc_ddrphy_apb_wr(0x5414a,0x0); + dwc_ddrphy_apb_wr(0x5414b,0x0); + dwc_ddrphy_apb_wr(0x5414c,0x0); + dwc_ddrphy_apb_wr(0x5414d,0x0); + dwc_ddrphy_apb_wr(0x5414e,0x0); + dwc_ddrphy_apb_wr(0x5414f,0x0); + dwc_ddrphy_apb_wr(0x54150,0x0); + dwc_ddrphy_apb_wr(0x54151,0x0); + dwc_ddrphy_apb_wr(0x54152,0x0); + dwc_ddrphy_apb_wr(0x54153,0x0); + dwc_ddrphy_apb_wr(0x54154,0x0); + dwc_ddrphy_apb_wr(0x54155,0x0); + dwc_ddrphy_apb_wr(0x54156,0x0); + dwc_ddrphy_apb_wr(0x54157,0x0); + dwc_ddrphy_apb_wr(0x54158,0x0); + dwc_ddrphy_apb_wr(0x54159,0x0); + dwc_ddrphy_apb_wr(0x5415a,0x0); + dwc_ddrphy_apb_wr(0x5415b,0x0); + dwc_ddrphy_apb_wr(0x5415c,0x0); + dwc_ddrphy_apb_wr(0x5415d,0x0); + dwc_ddrphy_apb_wr(0x5415e,0x0); + dwc_ddrphy_apb_wr(0x5415f,0x0); + dwc_ddrphy_apb_wr(0x54160,0x0); + dwc_ddrphy_apb_wr(0x54161,0x0); + dwc_ddrphy_apb_wr(0x54162,0x0); + dwc_ddrphy_apb_wr(0x54163,0x0); + dwc_ddrphy_apb_wr(0x54164,0x0); + dwc_ddrphy_apb_wr(0x54165,0x0); + dwc_ddrphy_apb_wr(0x54166,0x0); + dwc_ddrphy_apb_wr(0x54167,0x0); + dwc_ddrphy_apb_wr(0x54168,0x0); + dwc_ddrphy_apb_wr(0x54169,0x0); + dwc_ddrphy_apb_wr(0x5416a,0x0); + dwc_ddrphy_apb_wr(0x5416b,0x0); + dwc_ddrphy_apb_wr(0x5416c,0x0); + dwc_ddrphy_apb_wr(0x5416d,0x0); + dwc_ddrphy_apb_wr(0x5416e,0x0); + dwc_ddrphy_apb_wr(0x5416f,0x0); + dwc_ddrphy_apb_wr(0x54170,0x0); + dwc_ddrphy_apb_wr(0x54171,0x0); + dwc_ddrphy_apb_wr(0x54172,0x0); + dwc_ddrphy_apb_wr(0x54173,0x0); + dwc_ddrphy_apb_wr(0x54174,0x0); + dwc_ddrphy_apb_wr(0x54175,0x0); + dwc_ddrphy_apb_wr(0x54176,0x0); + dwc_ddrphy_apb_wr(0x54177,0x0); + dwc_ddrphy_apb_wr(0x54178,0x0); + dwc_ddrphy_apb_wr(0x54179,0x0); + dwc_ddrphy_apb_wr(0x5417a,0x0); + dwc_ddrphy_apb_wr(0x5417b,0x0); + dwc_ddrphy_apb_wr(0x5417c,0x0); + dwc_ddrphy_apb_wr(0x5417d,0x0); + dwc_ddrphy_apb_wr(0x5417e,0x0); + dwc_ddrphy_apb_wr(0x5417f,0x0); + dwc_ddrphy_apb_wr(0x54180,0x0); + dwc_ddrphy_apb_wr(0x54181,0x0); + dwc_ddrphy_apb_wr(0x54182,0x0); + dwc_ddrphy_apb_wr(0x54183,0x0); + dwc_ddrphy_apb_wr(0x54184,0x0); + dwc_ddrphy_apb_wr(0x54185,0x0); + dwc_ddrphy_apb_wr(0x54186,0x0); + dwc_ddrphy_apb_wr(0x54187,0x0); + dwc_ddrphy_apb_wr(0x54188,0x0); + dwc_ddrphy_apb_wr(0x54189,0x0); + dwc_ddrphy_apb_wr(0x5418a,0x0); + dwc_ddrphy_apb_wr(0x5418b,0x0); + dwc_ddrphy_apb_wr(0x5418c,0x0); + dwc_ddrphy_apb_wr(0x5418d,0x0); + dwc_ddrphy_apb_wr(0x5418e,0x0); + dwc_ddrphy_apb_wr(0x5418f,0x0); + dwc_ddrphy_apb_wr(0x54190,0x0); + dwc_ddrphy_apb_wr(0x54191,0x0); + dwc_ddrphy_apb_wr(0x54192,0x0); + dwc_ddrphy_apb_wr(0x54193,0x0); + dwc_ddrphy_apb_wr(0x54194,0x0); + dwc_ddrphy_apb_wr(0x54195,0x0); + dwc_ddrphy_apb_wr(0x54196,0x0); + dwc_ddrphy_apb_wr(0x54197,0x0); + dwc_ddrphy_apb_wr(0x54198,0x0); + dwc_ddrphy_apb_wr(0x54199,0x0); + dwc_ddrphy_apb_wr(0x5419a,0x0); + dwc_ddrphy_apb_wr(0x5419b,0x0); + dwc_ddrphy_apb_wr(0x5419c,0x0); + dwc_ddrphy_apb_wr(0x5419d,0x0); + dwc_ddrphy_apb_wr(0x5419e,0x0); + dwc_ddrphy_apb_wr(0x5419f,0x0); + dwc_ddrphy_apb_wr(0x541a0,0x0); + dwc_ddrphy_apb_wr(0x541a1,0x0); + dwc_ddrphy_apb_wr(0x541a2,0x0); + dwc_ddrphy_apb_wr(0x541a3,0x0); + dwc_ddrphy_apb_wr(0x541a4,0x0); + dwc_ddrphy_apb_wr(0x541a5,0x0); + dwc_ddrphy_apb_wr(0x541a6,0x0); + dwc_ddrphy_apb_wr(0x541a7,0x0); + dwc_ddrphy_apb_wr(0x541a8,0x0); + dwc_ddrphy_apb_wr(0x541a9,0x0); + dwc_ddrphy_apb_wr(0x541aa,0x0); + dwc_ddrphy_apb_wr(0x541ab,0x0); + dwc_ddrphy_apb_wr(0x541ac,0x0); + dwc_ddrphy_apb_wr(0x541ad,0x0); + dwc_ddrphy_apb_wr(0x541ae,0x0); + dwc_ddrphy_apb_wr(0x541af,0x0); + dwc_ddrphy_apb_wr(0x541b0,0x0); + dwc_ddrphy_apb_wr(0x541b1,0x0); + dwc_ddrphy_apb_wr(0x541b2,0x0); + dwc_ddrphy_apb_wr(0x541b3,0x0); + dwc_ddrphy_apb_wr(0x541b4,0x0); + dwc_ddrphy_apb_wr(0x541b5,0x0); + dwc_ddrphy_apb_wr(0x541b6,0x0); + dwc_ddrphy_apb_wr(0x541b7,0x0); + dwc_ddrphy_apb_wr(0x541b8,0x0); + dwc_ddrphy_apb_wr(0x541b9,0x0); + dwc_ddrphy_apb_wr(0x541ba,0x0); + dwc_ddrphy_apb_wr(0x541bb,0x0); + dwc_ddrphy_apb_wr(0x541bc,0x0); + dwc_ddrphy_apb_wr(0x541bd,0x0); + dwc_ddrphy_apb_wr(0x541be,0x0); + dwc_ddrphy_apb_wr(0x541bf,0x0); + dwc_ddrphy_apb_wr(0x541c0,0x0); + dwc_ddrphy_apb_wr(0x541c1,0x0); + dwc_ddrphy_apb_wr(0x541c2,0x0); + dwc_ddrphy_apb_wr(0x541c3,0x0); + dwc_ddrphy_apb_wr(0x541c4,0x0); + dwc_ddrphy_apb_wr(0x541c5,0x0); + dwc_ddrphy_apb_wr(0x541c6,0x0); + dwc_ddrphy_apb_wr(0x541c7,0x0); + dwc_ddrphy_apb_wr(0x541c8,0x0); + dwc_ddrphy_apb_wr(0x541c9,0x0); + dwc_ddrphy_apb_wr(0x541ca,0x0); + dwc_ddrphy_apb_wr(0x541cb,0x0); + dwc_ddrphy_apb_wr(0x541cc,0x0); + dwc_ddrphy_apb_wr(0x541cd,0x0); + dwc_ddrphy_apb_wr(0x541ce,0x0); + dwc_ddrphy_apb_wr(0x541cf,0x0); + dwc_ddrphy_apb_wr(0x541d0,0x0); + dwc_ddrphy_apb_wr(0x541d1,0x0); + dwc_ddrphy_apb_wr(0x541d2,0x0); + dwc_ddrphy_apb_wr(0x541d3,0x0); + dwc_ddrphy_apb_wr(0x541d4,0x0); + dwc_ddrphy_apb_wr(0x541d5,0x0); + dwc_ddrphy_apb_wr(0x541d6,0x0); + dwc_ddrphy_apb_wr(0x541d7,0x0); + dwc_ddrphy_apb_wr(0x541d8,0x0); + dwc_ddrphy_apb_wr(0x541d9,0x0); + dwc_ddrphy_apb_wr(0x541da,0x0); + dwc_ddrphy_apb_wr(0x541db,0x0); + dwc_ddrphy_apb_wr(0x541dc,0x0); + dwc_ddrphy_apb_wr(0x541dd,0x0); + dwc_ddrphy_apb_wr(0x541de,0x0); + dwc_ddrphy_apb_wr(0x541df,0x0); + dwc_ddrphy_apb_wr(0x541e0,0x0); + dwc_ddrphy_apb_wr(0x541e1,0x0); + dwc_ddrphy_apb_wr(0x541e2,0x0); + dwc_ddrphy_apb_wr(0x541e3,0x0); + dwc_ddrphy_apb_wr(0x541e4,0x0); + dwc_ddrphy_apb_wr(0x541e5,0x0); + dwc_ddrphy_apb_wr(0x541e6,0x0); + dwc_ddrphy_apb_wr(0x541e7,0x0); + dwc_ddrphy_apb_wr(0x541e8,0x0); + dwc_ddrphy_apb_wr(0x541e9,0x0); + dwc_ddrphy_apb_wr(0x541ea,0x0); + dwc_ddrphy_apb_wr(0x541eb,0x0); + dwc_ddrphy_apb_wr(0x541ec,0x0); + dwc_ddrphy_apb_wr(0x541ed,0x0); + dwc_ddrphy_apb_wr(0x541ee,0x0); + dwc_ddrphy_apb_wr(0x541ef,0x0); + dwc_ddrphy_apb_wr(0x541f0,0x0); + dwc_ddrphy_apb_wr(0x541f1,0x0); + dwc_ddrphy_apb_wr(0x541f2,0x0); + dwc_ddrphy_apb_wr(0x541f3,0x0); + dwc_ddrphy_apb_wr(0x541f4,0x0); + dwc_ddrphy_apb_wr(0x541f5,0x0); + dwc_ddrphy_apb_wr(0x541f6,0x0); + dwc_ddrphy_apb_wr(0x541f7,0x0); + dwc_ddrphy_apb_wr(0x541f8,0x0); + dwc_ddrphy_apb_wr(0x541f9,0x0); + dwc_ddrphy_apb_wr(0x541fa,0x0); + dwc_ddrphy_apb_wr(0x541fb,0x0); + dwc_ddrphy_apb_wr(0x541fc,0x100); + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099,0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + + wait_ddrphy_training_complete(); + + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + + ddr_load_train_code(FW_2D_IMAGE); + + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x54000,0x80);/* should be 0x80 in silicon */ + dwc_ddrphy_apb_wr(0x54001,0x0); + dwc_ddrphy_apb_wr(0x54002,0x0); + dwc_ddrphy_apb_wr(0x54003,0x960); + dwc_ddrphy_apb_wr(0x54004,0x2); + + dwc_ddrphy_apb_wr(0x54005,((PHY_RON<<8)|(PHY_RTT<<0))/*0x2830*/); + dwc_ddrphy_apb_wr(0x54006,(0x200|PHYREF_VALUE)/*0x23b*/); + dwc_ddrphy_apb_wr(0x54007,0x2000); + + dwc_ddrphy_apb_wr(0x54008,0x303); + + dwc_ddrphy_apb_wr(0x54009,0x200); + dwc_ddrphy_apb_wr(0x5400a,0x0); + dwc_ddrphy_apb_wr(0x5400b,0x61);/* should be 0x61 in silicon */ + + dwc_ddrphy_apb_wr(0x5400c,0xc8); /* 0xc8 indicates stage completion messages showed */ + + dwc_ddrphy_apb_wr(0x5400d,0x0); + dwc_ddrphy_apb_wr(0x5400e,0x8020); + dwc_ddrphy_apb_wr(0x5400f,0x0); + dwc_ddrphy_apb_wr(0x54010,0x0); + dwc_ddrphy_apb_wr(0x54011,0x0); + dwc_ddrphy_apb_wr(0x54012,0x1); + dwc_ddrphy_apb_wr(0x54013,0x0); + dwc_ddrphy_apb_wr(0x54014,0x0); + dwc_ddrphy_apb_wr(0x54015,0x0); + dwc_ddrphy_apb_wr(0x54016,0x0); + dwc_ddrphy_apb_wr(0x54017,0x0); + dwc_ddrphy_apb_wr(0x54018,0x0); + dwc_ddrphy_apb_wr(0x54019,0x0); + dwc_ddrphy_apb_wr(0x5401a,0x0); + dwc_ddrphy_apb_wr(0x5401b,0x0); + dwc_ddrphy_apb_wr(0x5401c,0x0); + dwc_ddrphy_apb_wr(0x5401d,0x0); + dwc_ddrphy_apb_wr(0x5401e,0x0); + dwc_ddrphy_apb_wr(0x5401f,0x0); + dwc_ddrphy_apb_wr(0x54020,0x0); + dwc_ddrphy_apb_wr(0x54021,0x0); + dwc_ddrphy_apb_wr(0x54022,0x0); + dwc_ddrphy_apb_wr(0x54023,0x0); + dwc_ddrphy_apb_wr(0x54024,0x0); + dwc_ddrphy_apb_wr(0x54025,0x0); + dwc_ddrphy_apb_wr(0x54026,0x0); + dwc_ddrphy_apb_wr(0x54027,0x0); + dwc_ddrphy_apb_wr(0x54028,0x0); + dwc_ddrphy_apb_wr(0x54029,0x0); + dwc_ddrphy_apb_wr(0x5402a,0x0); + dwc_ddrphy_apb_wr(0x5402b,0x0); + dwc_ddrphy_apb_wr(0x5402c,0x0); + dwc_ddrphy_apb_wr(0x5402d,0x0); + dwc_ddrphy_apb_wr(0x5402e,0x0); + + dwc_ddrphy_apb_wr(0x5402f,0xa30);/* MR0 */ + dwc_ddrphy_apb_wr(0x54030, ((DDR_RTT<<8)|(DDR_RON<<1)|0x1)/*0x1*/);/* MR1 */ + dwc_ddrphy_apb_wr(0x54031,0x1018);/* MR2 */ + dwc_ddrphy_apb_wr(0x54032,0x240);/* MR3 */ + dwc_ddrphy_apb_wr(0x54033,0xa00);/* MR4 */ + dwc_ddrphy_apb_wr(0x54034,0x42);/* MR5 */ + dwc_ddrphy_apb_wr(0x54035,(0x800|MR6_VALUE)/*0x800*/);/* MR6 */ + + dwc_ddrphy_apb_wr(0x54036,0x103); + dwc_ddrphy_apb_wr(0x54037,0x0); + dwc_ddrphy_apb_wr(0x54038,0x0); + dwc_ddrphy_apb_wr(0x54039,0x0); + dwc_ddrphy_apb_wr(0x5403a,0x0); + dwc_ddrphy_apb_wr(0x5403b,0x0); + dwc_ddrphy_apb_wr(0x5403c,0x0); + dwc_ddrphy_apb_wr(0x5403d,0x0); + dwc_ddrphy_apb_wr(0x5403e,0x0); + dwc_ddrphy_apb_wr(0x5403f,0x1221); + dwc_ddrphy_apb_wr(0x54040,0x0); + dwc_ddrphy_apb_wr(0x54041,0x0); + dwc_ddrphy_apb_wr(0x54042,0x0); + dwc_ddrphy_apb_wr(0x54043,0x0); + dwc_ddrphy_apb_wr(0x54044,0x0); + dwc_ddrphy_apb_wr(0x54045,0x0); + dwc_ddrphy_apb_wr(0x54046,0x0); + dwc_ddrphy_apb_wr(0x54047,0x0); + dwc_ddrphy_apb_wr(0x54048,0x0); + dwc_ddrphy_apb_wr(0x54049,0x0); + dwc_ddrphy_apb_wr(0x5404a,0x0); + dwc_ddrphy_apb_wr(0x5404b,0x0); + dwc_ddrphy_apb_wr(0x5404c,0x0); + dwc_ddrphy_apb_wr(0x5404d,0x0); + dwc_ddrphy_apb_wr(0x5404e,0x0); + dwc_ddrphy_apb_wr(0x5404f,0x0); + dwc_ddrphy_apb_wr(0x54050,0x0); + dwc_ddrphy_apb_wr(0x54051,0x0); + dwc_ddrphy_apb_wr(0x54052,0x0); + dwc_ddrphy_apb_wr(0x54053,0x0); + dwc_ddrphy_apb_wr(0x54054,0x0); + dwc_ddrphy_apb_wr(0x54055,0x0); + dwc_ddrphy_apb_wr(0x54056,0x0); + dwc_ddrphy_apb_wr(0x54057,0x0); + dwc_ddrphy_apb_wr(0x54058,0x0); + dwc_ddrphy_apb_wr(0x54059,0x0); + dwc_ddrphy_apb_wr(0x5405a,0x0); + dwc_ddrphy_apb_wr(0x5405b,0x0); + dwc_ddrphy_apb_wr(0x5405c,0x0); + dwc_ddrphy_apb_wr(0x5405d,0x0); + dwc_ddrphy_apb_wr(0x5405e,0x0); + dwc_ddrphy_apb_wr(0x5405f,0x0); + dwc_ddrphy_apb_wr(0x54060,0x0); + dwc_ddrphy_apb_wr(0x54061,0x0); + dwc_ddrphy_apb_wr(0x54062,0x0); + dwc_ddrphy_apb_wr(0x54063,0x0); + dwc_ddrphy_apb_wr(0x54064,0x0); + dwc_ddrphy_apb_wr(0x54065,0x0); + dwc_ddrphy_apb_wr(0x54066,0x0); + dwc_ddrphy_apb_wr(0x54067,0x0); + dwc_ddrphy_apb_wr(0x54068,0x0); + dwc_ddrphy_apb_wr(0x54069,0x0); + dwc_ddrphy_apb_wr(0x5406a,0x0); + dwc_ddrphy_apb_wr(0x5406b,0x0); + dwc_ddrphy_apb_wr(0x5406c,0x0); + dwc_ddrphy_apb_wr(0x5406d,0x0); + dwc_ddrphy_apb_wr(0x5406e,0x0); + dwc_ddrphy_apb_wr(0x5406f,0x0); + dwc_ddrphy_apb_wr(0x54070,0x0); + dwc_ddrphy_apb_wr(0x54071,0x0); + dwc_ddrphy_apb_wr(0x54072,0x0); + dwc_ddrphy_apb_wr(0x54073,0x0); + dwc_ddrphy_apb_wr(0x54074,0x0); + dwc_ddrphy_apb_wr(0x54075,0x0); + dwc_ddrphy_apb_wr(0x54076,0x0); + dwc_ddrphy_apb_wr(0x54077,0x0); + dwc_ddrphy_apb_wr(0x54078,0x0); + dwc_ddrphy_apb_wr(0x54079,0x0); + dwc_ddrphy_apb_wr(0x5407a,0x0); + dwc_ddrphy_apb_wr(0x5407b,0x0); + dwc_ddrphy_apb_wr(0x5407c,0x0); + dwc_ddrphy_apb_wr(0x5407d,0x0); + dwc_ddrphy_apb_wr(0x5407e,0x0); + dwc_ddrphy_apb_wr(0x5407f,0x0); + dwc_ddrphy_apb_wr(0x54080,0x0); + dwc_ddrphy_apb_wr(0x54081,0x0); + dwc_ddrphy_apb_wr(0x54082,0x0); + dwc_ddrphy_apb_wr(0x54083,0x0); + dwc_ddrphy_apb_wr(0x54084,0x0); + dwc_ddrphy_apb_wr(0x54085,0x0); + dwc_ddrphy_apb_wr(0x54086,0x0); + dwc_ddrphy_apb_wr(0x54087,0x0); + dwc_ddrphy_apb_wr(0x54088,0x0); + dwc_ddrphy_apb_wr(0x54089,0x0); + dwc_ddrphy_apb_wr(0x5408a,0x0); + dwc_ddrphy_apb_wr(0x5408b,0x0); + dwc_ddrphy_apb_wr(0x5408c,0x0); + dwc_ddrphy_apb_wr(0x5408d,0x0); + dwc_ddrphy_apb_wr(0x5408e,0x0); + dwc_ddrphy_apb_wr(0x5408f,0x0); + dwc_ddrphy_apb_wr(0x54090,0x0); + dwc_ddrphy_apb_wr(0x54091,0x0); + dwc_ddrphy_apb_wr(0x54092,0x0); + dwc_ddrphy_apb_wr(0x54093,0x0); + dwc_ddrphy_apb_wr(0x54094,0x0); + dwc_ddrphy_apb_wr(0x54095,0x0); + dwc_ddrphy_apb_wr(0x54096,0x0); + dwc_ddrphy_apb_wr(0x54097,0x0); + dwc_ddrphy_apb_wr(0x54098,0x0); + dwc_ddrphy_apb_wr(0x54099,0x0); + dwc_ddrphy_apb_wr(0x5409a,0x0); + dwc_ddrphy_apb_wr(0x5409b,0x0); + dwc_ddrphy_apb_wr(0x5409c,0x0); + dwc_ddrphy_apb_wr(0x5409d,0x0); + dwc_ddrphy_apb_wr(0x5409e,0x0); + dwc_ddrphy_apb_wr(0x5409f,0x0); + dwc_ddrphy_apb_wr(0x540a0,0x0); + dwc_ddrphy_apb_wr(0x540a1,0x0); + dwc_ddrphy_apb_wr(0x540a2,0x0); + dwc_ddrphy_apb_wr(0x540a3,0x0); + dwc_ddrphy_apb_wr(0x540a4,0x0); + dwc_ddrphy_apb_wr(0x540a5,0x0); + dwc_ddrphy_apb_wr(0x540a6,0x0); + dwc_ddrphy_apb_wr(0x540a7,0x0); + dwc_ddrphy_apb_wr(0x540a8,0x0); + dwc_ddrphy_apb_wr(0x540a9,0x0); + dwc_ddrphy_apb_wr(0x540aa,0x0); + dwc_ddrphy_apb_wr(0x540ab,0x0); + dwc_ddrphy_apb_wr(0x540ac,0x0); + dwc_ddrphy_apb_wr(0x540ad,0x0); + dwc_ddrphy_apb_wr(0x540ae,0x0); + dwc_ddrphy_apb_wr(0x540af,0x0); + dwc_ddrphy_apb_wr(0x540b0,0x0); + dwc_ddrphy_apb_wr(0x540b1,0x0); + dwc_ddrphy_apb_wr(0x540b2,0x0); + dwc_ddrphy_apb_wr(0x540b3,0x0); + dwc_ddrphy_apb_wr(0x540b4,0x0); + dwc_ddrphy_apb_wr(0x540b5,0x0); + dwc_ddrphy_apb_wr(0x540b6,0x0); + dwc_ddrphy_apb_wr(0x540b7,0x0); + dwc_ddrphy_apb_wr(0x540b8,0x0); + dwc_ddrphy_apb_wr(0x540b9,0x0); + dwc_ddrphy_apb_wr(0x540ba,0x0); + dwc_ddrphy_apb_wr(0x540bb,0x0); + dwc_ddrphy_apb_wr(0x540bc,0x0); + dwc_ddrphy_apb_wr(0x540bd,0x0); + dwc_ddrphy_apb_wr(0x540be,0x0); + dwc_ddrphy_apb_wr(0x540bf,0x0); + dwc_ddrphy_apb_wr(0x540c0,0x0); + dwc_ddrphy_apb_wr(0x540c1,0x0); + dwc_ddrphy_apb_wr(0x540c2,0x0); + dwc_ddrphy_apb_wr(0x540c3,0x0); + dwc_ddrphy_apb_wr(0x540c4,0x0); + dwc_ddrphy_apb_wr(0x540c5,0x0); + dwc_ddrphy_apb_wr(0x540c6,0x0); + dwc_ddrphy_apb_wr(0x540c7,0x0); + dwc_ddrphy_apb_wr(0x540c8,0x0); + dwc_ddrphy_apb_wr(0x540c9,0x0); + dwc_ddrphy_apb_wr(0x540ca,0x0); + dwc_ddrphy_apb_wr(0x540cb,0x0); + dwc_ddrphy_apb_wr(0x540cc,0x0); + dwc_ddrphy_apb_wr(0x540cd,0x0); + dwc_ddrphy_apb_wr(0x540ce,0x0); + dwc_ddrphy_apb_wr(0x540cf,0x0); + dwc_ddrphy_apb_wr(0x540d0,0x0); + dwc_ddrphy_apb_wr(0x540d1,0x0); + dwc_ddrphy_apb_wr(0x540d2,0x0); + dwc_ddrphy_apb_wr(0x540d3,0x0); + dwc_ddrphy_apb_wr(0x540d4,0x0); + dwc_ddrphy_apb_wr(0x540d5,0x0); + dwc_ddrphy_apb_wr(0x540d6,0x0); + dwc_ddrphy_apb_wr(0x540d7,0x0); + dwc_ddrphy_apb_wr(0x540d8,0x0); + dwc_ddrphy_apb_wr(0x540d9,0x0); + dwc_ddrphy_apb_wr(0x540da,0x0); + dwc_ddrphy_apb_wr(0x540db,0x0); + dwc_ddrphy_apb_wr(0x540dc,0x0); + dwc_ddrphy_apb_wr(0x540dd,0x0); + dwc_ddrphy_apb_wr(0x540de,0x0); + dwc_ddrphy_apb_wr(0x540df,0x0); + dwc_ddrphy_apb_wr(0x540e0,0x0); + dwc_ddrphy_apb_wr(0x540e1,0x0); + dwc_ddrphy_apb_wr(0x540e2,0x0); + dwc_ddrphy_apb_wr(0x540e3,0x0); + dwc_ddrphy_apb_wr(0x540e4,0x0); + dwc_ddrphy_apb_wr(0x540e5,0x0); + dwc_ddrphy_apb_wr(0x540e6,0x0); + dwc_ddrphy_apb_wr(0x540e7,0x0); + dwc_ddrphy_apb_wr(0x540e8,0x0); + dwc_ddrphy_apb_wr(0x540e9,0x0); + dwc_ddrphy_apb_wr(0x540ea,0x0); + dwc_ddrphy_apb_wr(0x540eb,0x0); + dwc_ddrphy_apb_wr(0x540ec,0x0); + dwc_ddrphy_apb_wr(0x540ed,0x0); + dwc_ddrphy_apb_wr(0x540ee,0x0); + dwc_ddrphy_apb_wr(0x540ef,0x0); + dwc_ddrphy_apb_wr(0x540f0,0x0); + dwc_ddrphy_apb_wr(0x540f1,0x0); + dwc_ddrphy_apb_wr(0x540f2,0x0); + dwc_ddrphy_apb_wr(0x540f3,0x0); + dwc_ddrphy_apb_wr(0x540f4,0x0); + dwc_ddrphy_apb_wr(0x540f5,0x0); + dwc_ddrphy_apb_wr(0x540f6,0x0); + dwc_ddrphy_apb_wr(0x540f7,0x0); + dwc_ddrphy_apb_wr(0x540f8,0x0); + dwc_ddrphy_apb_wr(0x540f9,0x0); + dwc_ddrphy_apb_wr(0x540fa,0x0); + dwc_ddrphy_apb_wr(0x540fb,0x0); + dwc_ddrphy_apb_wr(0x540fc,0x0); + dwc_ddrphy_apb_wr(0x540fd,0x0); + dwc_ddrphy_apb_wr(0x540fe,0x0); + dwc_ddrphy_apb_wr(0x540ff,0x0); + dwc_ddrphy_apb_wr(0x54100,0x0); + dwc_ddrphy_apb_wr(0x54101,0x0); + dwc_ddrphy_apb_wr(0x54102,0x0); + dwc_ddrphy_apb_wr(0x54103,0x0); + dwc_ddrphy_apb_wr(0x54104,0x0); + dwc_ddrphy_apb_wr(0x54105,0x0); + dwc_ddrphy_apb_wr(0x54106,0x0); + dwc_ddrphy_apb_wr(0x54107,0x0); + dwc_ddrphy_apb_wr(0x54108,0x0); + dwc_ddrphy_apb_wr(0x54109,0x0); + dwc_ddrphy_apb_wr(0x5410a,0x0); + dwc_ddrphy_apb_wr(0x5410b,0x0); + dwc_ddrphy_apb_wr(0x5410c,0x0); + dwc_ddrphy_apb_wr(0x5410d,0x0); + dwc_ddrphy_apb_wr(0x5410e,0x0); + dwc_ddrphy_apb_wr(0x5410f,0x0); + dwc_ddrphy_apb_wr(0x54110,0x0); + dwc_ddrphy_apb_wr(0x54111,0x0); + dwc_ddrphy_apb_wr(0x54112,0x0); + dwc_ddrphy_apb_wr(0x54113,0x0); + dwc_ddrphy_apb_wr(0x54114,0x0); + dwc_ddrphy_apb_wr(0x54115,0x0); + dwc_ddrphy_apb_wr(0x54116,0x0); + dwc_ddrphy_apb_wr(0x54117,0x0); + dwc_ddrphy_apb_wr(0x54118,0x0); + dwc_ddrphy_apb_wr(0x54119,0x0); + dwc_ddrphy_apb_wr(0x5411a,0x0); + dwc_ddrphy_apb_wr(0x5411b,0x0); + dwc_ddrphy_apb_wr(0x5411c,0x0); + dwc_ddrphy_apb_wr(0x5411d,0x0); + dwc_ddrphy_apb_wr(0x5411e,0x0); + dwc_ddrphy_apb_wr(0x5411f,0x0); + dwc_ddrphy_apb_wr(0x54120,0x0); + dwc_ddrphy_apb_wr(0x54121,0x0); + dwc_ddrphy_apb_wr(0x54122,0x0); + dwc_ddrphy_apb_wr(0x54123,0x0); + dwc_ddrphy_apb_wr(0x54124,0x0); + dwc_ddrphy_apb_wr(0x54125,0x0); + dwc_ddrphy_apb_wr(0x54126,0x0); + dwc_ddrphy_apb_wr(0x54127,0x0); + dwc_ddrphy_apb_wr(0x54128,0x0); + dwc_ddrphy_apb_wr(0x54129,0x0); + dwc_ddrphy_apb_wr(0x5412a,0x0); + dwc_ddrphy_apb_wr(0x5412b,0x0); + dwc_ddrphy_apb_wr(0x5412c,0x0); + dwc_ddrphy_apb_wr(0x5412d,0x0); + dwc_ddrphy_apb_wr(0x5412e,0x0); + dwc_ddrphy_apb_wr(0x5412f,0x0); + dwc_ddrphy_apb_wr(0x54130,0x0); + dwc_ddrphy_apb_wr(0x54131,0x0); + dwc_ddrphy_apb_wr(0x54132,0x0); + dwc_ddrphy_apb_wr(0x54133,0x0); + dwc_ddrphy_apb_wr(0x54134,0x0); + dwc_ddrphy_apb_wr(0x54135,0x0); + dwc_ddrphy_apb_wr(0x54136,0x0); + dwc_ddrphy_apb_wr(0x54137,0x0); + dwc_ddrphy_apb_wr(0x54138,0x0); + dwc_ddrphy_apb_wr(0x54139,0x0); + dwc_ddrphy_apb_wr(0x5413a,0x0); + dwc_ddrphy_apb_wr(0x5413b,0x0); + dwc_ddrphy_apb_wr(0x5413c,0x0); + dwc_ddrphy_apb_wr(0x5413d,0x0); + dwc_ddrphy_apb_wr(0x5413e,0x0); + dwc_ddrphy_apb_wr(0x5413f,0x0); + dwc_ddrphy_apb_wr(0x54140,0x0); + dwc_ddrphy_apb_wr(0x54141,0x0); + dwc_ddrphy_apb_wr(0x54142,0x0); + dwc_ddrphy_apb_wr(0x54143,0x0); + dwc_ddrphy_apb_wr(0x54144,0x0); + dwc_ddrphy_apb_wr(0x54145,0x0); + dwc_ddrphy_apb_wr(0x54146,0x0); + dwc_ddrphy_apb_wr(0x54147,0x0); + dwc_ddrphy_apb_wr(0x54148,0x0); + dwc_ddrphy_apb_wr(0x54149,0x0); + dwc_ddrphy_apb_wr(0x5414a,0x0); + dwc_ddrphy_apb_wr(0x5414b,0x0); + dwc_ddrphy_apb_wr(0x5414c,0x0); + dwc_ddrphy_apb_wr(0x5414d,0x0); + dwc_ddrphy_apb_wr(0x5414e,0x0); + dwc_ddrphy_apb_wr(0x5414f,0x0); + dwc_ddrphy_apb_wr(0x54150,0x0); + dwc_ddrphy_apb_wr(0x54151,0x0); + dwc_ddrphy_apb_wr(0x54152,0x0); + dwc_ddrphy_apb_wr(0x54153,0x0); + dwc_ddrphy_apb_wr(0x54154,0x0); + dwc_ddrphy_apb_wr(0x54155,0x0); + dwc_ddrphy_apb_wr(0x54156,0x0); + dwc_ddrphy_apb_wr(0x54157,0x0); + dwc_ddrphy_apb_wr(0x54158,0x0); + dwc_ddrphy_apb_wr(0x54159,0x0); + dwc_ddrphy_apb_wr(0x5415a,0x0); + dwc_ddrphy_apb_wr(0x5415b,0x0); + dwc_ddrphy_apb_wr(0x5415c,0x0); + dwc_ddrphy_apb_wr(0x5415d,0x0); + dwc_ddrphy_apb_wr(0x5415e,0x0); + dwc_ddrphy_apb_wr(0x5415f,0x0); + dwc_ddrphy_apb_wr(0x54160,0x0); + dwc_ddrphy_apb_wr(0x54161,0x0); + dwc_ddrphy_apb_wr(0x54162,0x0); + dwc_ddrphy_apb_wr(0x54163,0x0); + dwc_ddrphy_apb_wr(0x54164,0x0); + dwc_ddrphy_apb_wr(0x54165,0x0); + dwc_ddrphy_apb_wr(0x54166,0x0); + dwc_ddrphy_apb_wr(0x54167,0x0); + dwc_ddrphy_apb_wr(0x54168,0x0); + dwc_ddrphy_apb_wr(0x54169,0x0); + dwc_ddrphy_apb_wr(0x5416a,0x0); + dwc_ddrphy_apb_wr(0x5416b,0x0); + dwc_ddrphy_apb_wr(0x5416c,0x0); + dwc_ddrphy_apb_wr(0x5416d,0x0); + dwc_ddrphy_apb_wr(0x5416e,0x0); + dwc_ddrphy_apb_wr(0x5416f,0x0); + dwc_ddrphy_apb_wr(0x54170,0x0); + dwc_ddrphy_apb_wr(0x54171,0x0); + dwc_ddrphy_apb_wr(0x54172,0x0); + dwc_ddrphy_apb_wr(0x54173,0x0); + dwc_ddrphy_apb_wr(0x54174,0x0); + dwc_ddrphy_apb_wr(0x54175,0x0); + dwc_ddrphy_apb_wr(0x54176,0x0); + dwc_ddrphy_apb_wr(0x54177,0x0); + dwc_ddrphy_apb_wr(0x54178,0x0); + dwc_ddrphy_apb_wr(0x54179,0x0); + dwc_ddrphy_apb_wr(0x5417a,0x0); + dwc_ddrphy_apb_wr(0x5417b,0x0); + dwc_ddrphy_apb_wr(0x5417c,0x0); + dwc_ddrphy_apb_wr(0x5417d,0x0); + dwc_ddrphy_apb_wr(0x5417e,0x0); + dwc_ddrphy_apb_wr(0x5417f,0x0); + dwc_ddrphy_apb_wr(0x54180,0x0); + dwc_ddrphy_apb_wr(0x54181,0x0); + dwc_ddrphy_apb_wr(0x54182,0x0); + dwc_ddrphy_apb_wr(0x54183,0x0); + dwc_ddrphy_apb_wr(0x54184,0x0); + dwc_ddrphy_apb_wr(0x54185,0x0); + dwc_ddrphy_apb_wr(0x54186,0x0); + dwc_ddrphy_apb_wr(0x54187,0x0); + dwc_ddrphy_apb_wr(0x54188,0x0); + dwc_ddrphy_apb_wr(0x54189,0x0); + dwc_ddrphy_apb_wr(0x5418a,0x0); + dwc_ddrphy_apb_wr(0x5418b,0x0); + dwc_ddrphy_apb_wr(0x5418c,0x0); + dwc_ddrphy_apb_wr(0x5418d,0x0); + dwc_ddrphy_apb_wr(0x5418e,0x0); + dwc_ddrphy_apb_wr(0x5418f,0x0); + dwc_ddrphy_apb_wr(0x54190,0x0); + dwc_ddrphy_apb_wr(0x54191,0x0); + dwc_ddrphy_apb_wr(0x54192,0x0); + dwc_ddrphy_apb_wr(0x54193,0x0); + dwc_ddrphy_apb_wr(0x54194,0x0); + dwc_ddrphy_apb_wr(0x54195,0x0); + dwc_ddrphy_apb_wr(0x54196,0x0); + dwc_ddrphy_apb_wr(0x54197,0x0); + dwc_ddrphy_apb_wr(0x54198,0x0); + dwc_ddrphy_apb_wr(0x54199,0x0); + dwc_ddrphy_apb_wr(0x5419a,0x0); + dwc_ddrphy_apb_wr(0x5419b,0x0); + dwc_ddrphy_apb_wr(0x5419c,0x0); + dwc_ddrphy_apb_wr(0x5419d,0x0); + dwc_ddrphy_apb_wr(0x5419e,0x0); + dwc_ddrphy_apb_wr(0x5419f,0x0); + dwc_ddrphy_apb_wr(0x541a0,0x0); + dwc_ddrphy_apb_wr(0x541a1,0x0); + dwc_ddrphy_apb_wr(0x541a2,0x0); + dwc_ddrphy_apb_wr(0x541a3,0x0); + dwc_ddrphy_apb_wr(0x541a4,0x0); + dwc_ddrphy_apb_wr(0x541a5,0x0); + dwc_ddrphy_apb_wr(0x541a6,0x0); + dwc_ddrphy_apb_wr(0x541a7,0x0); + dwc_ddrphy_apb_wr(0x541a8,0x0); + dwc_ddrphy_apb_wr(0x541a9,0x0); + dwc_ddrphy_apb_wr(0x541aa,0x0); + dwc_ddrphy_apb_wr(0x541ab,0x0); + dwc_ddrphy_apb_wr(0x541ac,0x0); + dwc_ddrphy_apb_wr(0x541ad,0x0); + dwc_ddrphy_apb_wr(0x541ae,0x0); + dwc_ddrphy_apb_wr(0x541af,0x0); + dwc_ddrphy_apb_wr(0x541b0,0x0); + dwc_ddrphy_apb_wr(0x541b1,0x0); + dwc_ddrphy_apb_wr(0x541b2,0x0); + dwc_ddrphy_apb_wr(0x541b3,0x0); + dwc_ddrphy_apb_wr(0x541b4,0x0); + dwc_ddrphy_apb_wr(0x541b5,0x0); + dwc_ddrphy_apb_wr(0x541b6,0x0); + dwc_ddrphy_apb_wr(0x541b7,0x0); + dwc_ddrphy_apb_wr(0x541b8,0x0); + dwc_ddrphy_apb_wr(0x541b9,0x0); + dwc_ddrphy_apb_wr(0x541ba,0x0); + dwc_ddrphy_apb_wr(0x541bb,0x0); + dwc_ddrphy_apb_wr(0x541bc,0x0); + dwc_ddrphy_apb_wr(0x541bd,0x0); + dwc_ddrphy_apb_wr(0x541be,0x0); + dwc_ddrphy_apb_wr(0x541bf,0x0); + dwc_ddrphy_apb_wr(0x541c0,0x0); + dwc_ddrphy_apb_wr(0x541c1,0x0); + dwc_ddrphy_apb_wr(0x541c2,0x0); + dwc_ddrphy_apb_wr(0x541c3,0x0); + dwc_ddrphy_apb_wr(0x541c4,0x0); + dwc_ddrphy_apb_wr(0x541c5,0x0); + dwc_ddrphy_apb_wr(0x541c6,0x0); + dwc_ddrphy_apb_wr(0x541c7,0x0); + dwc_ddrphy_apb_wr(0x541c8,0x0); + dwc_ddrphy_apb_wr(0x541c9,0x0); + dwc_ddrphy_apb_wr(0x541ca,0x0); + dwc_ddrphy_apb_wr(0x541cb,0x0); + dwc_ddrphy_apb_wr(0x541cc,0x0); + dwc_ddrphy_apb_wr(0x541cd,0x0); + dwc_ddrphy_apb_wr(0x541ce,0x0); + dwc_ddrphy_apb_wr(0x541cf,0x0); + dwc_ddrphy_apb_wr(0x541d0,0x0); + dwc_ddrphy_apb_wr(0x541d1,0x0); + dwc_ddrphy_apb_wr(0x541d2,0x0); + dwc_ddrphy_apb_wr(0x541d3,0x0); + dwc_ddrphy_apb_wr(0x541d4,0x0); + dwc_ddrphy_apb_wr(0x541d5,0x0); + dwc_ddrphy_apb_wr(0x541d6,0x0); + dwc_ddrphy_apb_wr(0x541d7,0x0); + dwc_ddrphy_apb_wr(0x541d8,0x0); + dwc_ddrphy_apb_wr(0x541d9,0x0); + dwc_ddrphy_apb_wr(0x541da,0x0); + dwc_ddrphy_apb_wr(0x541db,0x0); + dwc_ddrphy_apb_wr(0x541dc,0x0); + dwc_ddrphy_apb_wr(0x541dd,0x0); + dwc_ddrphy_apb_wr(0x541de,0x0); + dwc_ddrphy_apb_wr(0x541df,0x0); + dwc_ddrphy_apb_wr(0x541e0,0x0); + dwc_ddrphy_apb_wr(0x541e1,0x0); + dwc_ddrphy_apb_wr(0x541e2,0x0); + dwc_ddrphy_apb_wr(0x541e3,0x0); + dwc_ddrphy_apb_wr(0x541e4,0x0); + dwc_ddrphy_apb_wr(0x541e5,0x0); + dwc_ddrphy_apb_wr(0x541e6,0x0); + dwc_ddrphy_apb_wr(0x541e7,0x0); + dwc_ddrphy_apb_wr(0x541e8,0x0); + dwc_ddrphy_apb_wr(0x541e9,0x0); + dwc_ddrphy_apb_wr(0x541ea,0x0); + dwc_ddrphy_apb_wr(0x541eb,0x0); + dwc_ddrphy_apb_wr(0x541ec,0x0); + dwc_ddrphy_apb_wr(0x541ed,0x0); + dwc_ddrphy_apb_wr(0x541ee,0x0); + dwc_ddrphy_apb_wr(0x541ef,0x0); + dwc_ddrphy_apb_wr(0x541f0,0x0); + dwc_ddrphy_apb_wr(0x541f1,0x0); + dwc_ddrphy_apb_wr(0x541f2,0x0); + dwc_ddrphy_apb_wr(0x541f3,0x0); + dwc_ddrphy_apb_wr(0x541f4,0x0); + dwc_ddrphy_apb_wr(0x541f5,0x0); + dwc_ddrphy_apb_wr(0x541f6,0x0); + dwc_ddrphy_apb_wr(0x541f7,0x0); + dwc_ddrphy_apb_wr(0x541f8,0x0); + dwc_ddrphy_apb_wr(0x541f9,0x0); + dwc_ddrphy_apb_wr(0x541fa,0x0); + dwc_ddrphy_apb_wr(0x541fb,0x0); + dwc_ddrphy_apb_wr(0x541fc,0x100); + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099,0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + + wait_ddrphy_training_complete(); + + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x90000,0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90001,0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90002,0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90003,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x90004,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x90005,0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x90029,0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x9002a,0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x9002b,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x9002c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9002d,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9002e,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x9002f,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + dwc_ddrphy_apb_wr(0x90030,0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + dwc_ddrphy_apb_wr(0x90031,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + dwc_ddrphy_apb_wr(0x90032,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + dwc_ddrphy_apb_wr(0x90033,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + dwc_ddrphy_apb_wr(0x90034,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + dwc_ddrphy_apb_wr(0x90035,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + dwc_ddrphy_apb_wr(0x90036,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + dwc_ddrphy_apb_wr(0x90037,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + dwc_ddrphy_apb_wr(0x90038,0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + dwc_ddrphy_apb_wr(0x90039,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + dwc_ddrphy_apb_wr(0x9003a,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + dwc_ddrphy_apb_wr(0x9003b,0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + dwc_ddrphy_apb_wr(0x9003c,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + dwc_ddrphy_apb_wr(0x9003d,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + dwc_ddrphy_apb_wr(0x9003e,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + dwc_ddrphy_apb_wr(0x9003f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + dwc_ddrphy_apb_wr(0x90040,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + dwc_ddrphy_apb_wr(0x90041,0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + dwc_ddrphy_apb_wr(0x90042,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + dwc_ddrphy_apb_wr(0x90043,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + dwc_ddrphy_apb_wr(0x90044,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + dwc_ddrphy_apb_wr(0x90045,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + dwc_ddrphy_apb_wr(0x90046,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + dwc_ddrphy_apb_wr(0x90047,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + dwc_ddrphy_apb_wr(0x90048,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + dwc_ddrphy_apb_wr(0x90049,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + dwc_ddrphy_apb_wr(0x9004a,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + dwc_ddrphy_apb_wr(0x9004b,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + dwc_ddrphy_apb_wr(0x9004c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + dwc_ddrphy_apb_wr(0x9004d,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + dwc_ddrphy_apb_wr(0x9004e,0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + dwc_ddrphy_apb_wr(0x9004f,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + dwc_ddrphy_apb_wr(0x90050,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + dwc_ddrphy_apb_wr(0x90051,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + dwc_ddrphy_apb_wr(0x90052,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + dwc_ddrphy_apb_wr(0x90053,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + dwc_ddrphy_apb_wr(0x90054,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + dwc_ddrphy_apb_wr(0x90055,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + dwc_ddrphy_apb_wr(0x90056,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + dwc_ddrphy_apb_wr(0x90057,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + dwc_ddrphy_apb_wr(0x90058,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + dwc_ddrphy_apb_wr(0x90059,0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + dwc_ddrphy_apb_wr(0x9005a,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + dwc_ddrphy_apb_wr(0x9005b,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + dwc_ddrphy_apb_wr(0x9005c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + dwc_ddrphy_apb_wr(0x9005d,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + dwc_ddrphy_apb_wr(0x9005e,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + dwc_ddrphy_apb_wr(0x9005f,0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + dwc_ddrphy_apb_wr(0x90060,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + dwc_ddrphy_apb_wr(0x90061,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + dwc_ddrphy_apb_wr(0x90062,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + dwc_ddrphy_apb_wr(0x90063,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + dwc_ddrphy_apb_wr(0x90064,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + dwc_ddrphy_apb_wr(0x90065,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + dwc_ddrphy_apb_wr(0x90066,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + dwc_ddrphy_apb_wr(0x90067,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + dwc_ddrphy_apb_wr(0x90068,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + dwc_ddrphy_apb_wr(0x90069,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + dwc_ddrphy_apb_wr(0x9006a,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + dwc_ddrphy_apb_wr(0x9006b,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + dwc_ddrphy_apb_wr(0x9006c,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + dwc_ddrphy_apb_wr(0x9006d,0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + dwc_ddrphy_apb_wr(0x9006e,0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + dwc_ddrphy_apb_wr(0x9006f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + dwc_ddrphy_apb_wr(0x90070,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + dwc_ddrphy_apb_wr(0x90071,0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + dwc_ddrphy_apb_wr(0x90072,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + dwc_ddrphy_apb_wr(0x90073,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + dwc_ddrphy_apb_wr(0x90074,0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + dwc_ddrphy_apb_wr(0x90075,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + dwc_ddrphy_apb_wr(0x90076,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + dwc_ddrphy_apb_wr(0x90077,0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + dwc_ddrphy_apb_wr(0x90078,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + dwc_ddrphy_apb_wr(0x90079,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + dwc_ddrphy_apb_wr(0x9007a,0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + dwc_ddrphy_apb_wr(0x9007b,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + dwc_ddrphy_apb_wr(0x9007c,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + dwc_ddrphy_apb_wr(0x9007d,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + dwc_ddrphy_apb_wr(0x9007e,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + dwc_ddrphy_apb_wr(0x9007f,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + dwc_ddrphy_apb_wr(0x90080,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + dwc_ddrphy_apb_wr(0x90081,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + dwc_ddrphy_apb_wr(0x90082,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + dwc_ddrphy_apb_wr(0x90083,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + dwc_ddrphy_apb_wr(0x90084,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + dwc_ddrphy_apb_wr(0x90085,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + dwc_ddrphy_apb_wr(0x90086,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + dwc_ddrphy_apb_wr(0x90087,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + dwc_ddrphy_apb_wr(0x90088,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + dwc_ddrphy_apb_wr(0x90089,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + dwc_ddrphy_apb_wr(0x9008a,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + dwc_ddrphy_apb_wr(0x9008b,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + dwc_ddrphy_apb_wr(0x9008c,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + dwc_ddrphy_apb_wr(0x9008d,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + dwc_ddrphy_apb_wr(0x9008e,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + dwc_ddrphy_apb_wr(0x9008f,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + dwc_ddrphy_apb_wr(0x90090,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + dwc_ddrphy_apb_wr(0x90091,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + dwc_ddrphy_apb_wr(0x90092,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + dwc_ddrphy_apb_wr(0x90093,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + dwc_ddrphy_apb_wr(0x90094,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + dwc_ddrphy_apb_wr(0x90095,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + dwc_ddrphy_apb_wr(0x90096,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + dwc_ddrphy_apb_wr(0x90097,0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + dwc_ddrphy_apb_wr(0x90098,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + dwc_ddrphy_apb_wr(0x90099,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + dwc_ddrphy_apb_wr(0x9009a,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + dwc_ddrphy_apb_wr(0x9009b,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + dwc_ddrphy_apb_wr(0x9009c,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + dwc_ddrphy_apb_wr(0x9009d,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + dwc_ddrphy_apb_wr(0x9009e,0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + dwc_ddrphy_apb_wr(0x9009f,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + dwc_ddrphy_apb_wr(0x900a0,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + dwc_ddrphy_apb_wr(0x900a1,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + dwc_ddrphy_apb_wr(0x900a2,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + dwc_ddrphy_apb_wr(0x900a3,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + dwc_ddrphy_apb_wr(0x900a4,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + dwc_ddrphy_apb_wr(0x900a5,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + dwc_ddrphy_apb_wr(0x900a6,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + dwc_ddrphy_apb_wr(0x900a7,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + dwc_ddrphy_apb_wr(0x900a8,0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + dwc_ddrphy_apb_wr(0x900a9,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + dwc_ddrphy_apb_wr(0x900aa,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + dwc_ddrphy_apb_wr(0x900ab,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + dwc_ddrphy_apb_wr(0x900ac,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + dwc_ddrphy_apb_wr(0x900ad,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + dwc_ddrphy_apb_wr(0x900ae,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + dwc_ddrphy_apb_wr(0x900af,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + dwc_ddrphy_apb_wr(0x900b0,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + dwc_ddrphy_apb_wr(0x900b1,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + dwc_ddrphy_apb_wr(0x900b2,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + dwc_ddrphy_apb_wr(0x900b3,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + dwc_ddrphy_apb_wr(0x900b4,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + dwc_ddrphy_apb_wr(0x900b5,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + dwc_ddrphy_apb_wr(0x900b6,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + dwc_ddrphy_apb_wr(0x900b7,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + dwc_ddrphy_apb_wr(0x900b8,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + dwc_ddrphy_apb_wr(0x900b9,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + dwc_ddrphy_apb_wr(0x900ba,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + dwc_ddrphy_apb_wr(0x900bb,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + dwc_ddrphy_apb_wr(0x900bc,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + dwc_ddrphy_apb_wr(0x900bd,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + dwc_ddrphy_apb_wr(0x900be,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + dwc_ddrphy_apb_wr(0x900bf,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + dwc_ddrphy_apb_wr(0x900c0,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + dwc_ddrphy_apb_wr(0x900c1,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + dwc_ddrphy_apb_wr(0x900c2,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + dwc_ddrphy_apb_wr(0x900c3,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + dwc_ddrphy_apb_wr(0x900c4,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + dwc_ddrphy_apb_wr(0x900c5,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + dwc_ddrphy_apb_wr(0x900c6,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + dwc_ddrphy_apb_wr(0x900c7,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + dwc_ddrphy_apb_wr(0x900c8,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + dwc_ddrphy_apb_wr(0x900c9,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + dwc_ddrphy_apb_wr(0x900ca,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + dwc_ddrphy_apb_wr(0x900cb,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + dwc_ddrphy_apb_wr(0x900cc,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + dwc_ddrphy_apb_wr(0x900cd,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + dwc_ddrphy_apb_wr(0x90006,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90007,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90008,0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90009,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9000a,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9000b,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0xd00e7,0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + dwc_ddrphy_apb_wr(0x90017,0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + dwc_ddrphy_apb_wr(0x90026,0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + dwc_ddrphy_apb_wr(0x9000c,0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + dwc_ddrphy_apb_wr(0x9000d,0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + dwc_ddrphy_apb_wr(0x9000e,0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + dwc_ddrphy_apb_wr(0x9000f,0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + dwc_ddrphy_apb_wr(0x90010,0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + dwc_ddrphy_apb_wr(0x90011,0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + dwc_ddrphy_apb_wr(0x90012,0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + dwc_ddrphy_apb_wr(0x90013,0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + dwc_ddrphy_apb_wr(0xc0080,0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +} diff --git a/board/freescale/imx8mq_arm2/ddr/helper.c b/board/freescale/imx8mq_arm2/ddr/helper.c new file mode 100644 index 0000000000..636ad8e0fe --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/helper.c @@ -0,0 +1,104 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr_memory_map.h> +#include <asm/sections.h> + +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768 +#define DMEM_LEN 16384 +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_code(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN; ){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + printf("check ddr_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if(error){ + printf("check ddr_imem code fail=%d\n",error); + }else{ + printf("check ddr_imem code pass\n"); + } + + printf("check ddr_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if(error){ + printf("check ddr_dmem code fail=%d",error); + }else{ + printf("check ddr_dmem code pass\n"); + } +} diff --git a/board/freescale/imx8mq_arm2/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mq_arm2/ddr/wait_ddrphy_training_complete.c new file mode 100644 index 0000000000..0b42e58bd1 --- /dev/null +++ b/board/freescale/imx8mq_arm2/ddr/wait_ddrphy_training_complete.c @@ -0,0 +1,96 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_recieve(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + ack_pmu_message_recieve(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_recieve(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + ddr_printf("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + ddr_printf(" PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)){ + arg = get_stream_message(); + ddr_printf(" arg[%d] = 0x%08x\n", i, arg); + i++; + } + + ddr_printf("\n"); +} + +void wait_ddrphy_training_complete(void) +{ + unsigned int mail; + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + printf("Training PASS\n"); + break; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + break; + } + } +} diff --git a/board/freescale/imx8mq_arm2/imx8m_arm2.c b/board/freescale/imx8mq_arm2/imx8m_arm2.c new file mode 100644 index 0000000000..ea936eafc7 --- /dev/null +++ b/board/freescale/imx8mq_arm2/imx8m_arm2.c @@ -0,0 +1,318 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <asm/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/dma.h> +#include <asm/arch/clock.h> +#include <spl.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" +#include <usb.h> +#include <dwc3-uboot.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) + +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_QSPI +static iomux_v3_cfg_t const qspi_pads[] = { + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); + + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + mxs_dma_init(); +} +#endif + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif + +int dram_init(void) +{ + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; + else + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; +} + + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +#ifndef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); +} +#endif + +static int setup_fec(void) +{ +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 + /* + * GPR1 bit 13: + * 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also; + * 0:enet1 rmii clock comes from external phy or osc + */ + + setbits_le32(IOMUXC_GPR1, BIT(13)); /* Use internal clock from CCM */ + return set_clk_enet(ENET_50MHz); +#else + setup_iomux_fec(); + + return set_clk_enet(ENET_125MHz); +#endif +} + + +int board_phy_config(struct phy_device *phydev) +{ +#ifndef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 + + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_SUPER, + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} + +int board_usb_init(int index, enum usb_init_type init) +{ + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + dwc3_uboot_exit(index); + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 + setenv("board_name", "DDR3L-ARM2"); +#else + setenv("board_name", "DDR4-ARM2"); +#endif + setenv("board_rev", "iMX8MQ"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +phys_size_t get_effective_memsize(void) +{ + if (PHYS_SDRAM_SIZE > 0xc0000000) + return 0xc0000000; + + return PHYS_SDRAM_SIZE; +} diff --git a/board/freescale/imx8mq_arm2/spl.c b/board/freescale/imx8mq_arm2/spl.c new file mode 100644 index 0000000000..c8c543a433 --- /dev/null +++ b/board/freescale/imx8mq_arm2/spl.c @@ -0,0 +1,242 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/arch/ddr_memory_map.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" +#include <asm/arch/clock.h> +#include <asm/imx-common/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <nand.h> +#include "ddr/ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* ddr init */ + ddr_init(); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 + ret = !gpio_get_value(USDHC2_CD_GPIO); +#else + ret = gpio_get_value(USDHC2_CD_GPIO); +#endif + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return -ENODEV; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return -ENODEV; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, ®); + if ((reg & 0x3f) != 0x1c) { + reg &= ~0x3f; + reg |= 0x1c; + pmic_reg_write(p, PFUZE100_SW1ABVOL, reg); + } + + pmic_reg_read(p, PFUZE100_SW1CVOL, ®); + if ((reg & 0x3f) != 0x1c) { + reg &= ~0x3f; + reg |= 0x1c; + pmic_reg_write(p, PFUZE100_SW1CVOL, reg); + } + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} +#endif + +void spl_board_init(void) +{ + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8mq_ddr3l_arm2_defconfig b/configs/imx8mq_ddr3l_arm2_defconfig new file mode 100644 index 0000000000..1bec0a2281 --- /dev/null +++ b/configs/imx8mq_ddr3l_arm2_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_DDR3L_ARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mq-ddr3l-arm2.dtb" +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_CACHE=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-ddr3l-arm2" +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +# CONFIG_BLK is not set +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mq_ddr4_arm2_defconfig b/configs/imx8mq_ddr4_arm2_defconfig new file mode 100644 index 0000000000..e492dacf74 --- /dev/null +++ b/configs/imx8mq_ddr4_arm2_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_DDR4_ARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mq-ddr4-arm2.dtb" +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_CACHE=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-ddr4-arm2" +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +# CONFIG_BLK is not set +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mq_ddr4_arm2_nand_defconfig b/configs/imx8mq_ddr4_arm2_nand_defconfig new file mode 100644 index 0000000000..51697d91e8 --- /dev/null +++ b/configs/imx8mq_ddr4_arm2_nand_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_DDR4_ARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mq-ddr3l-arm2-nand.dtb" +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_CACHE=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-ddr4-arm2" +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +# CONFIG_BLK is not set +CONFIG_CMD_REGULATOR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=y +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_NAND_BOOT=y diff --git a/include/configs/imx8mq_arm2.h b/include/configs/imx8mq_arm2.h new file mode 100644 index 0000000000..1504fbbc8b --- /dev/null +++ b/include/configs/imx8mq_arm2.h @@ -0,0 +1,366 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8M_ARM2_H +#define __IMX8M_ARM2_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x7E1000 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00182000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x8000000 /* Put the FIT out of first 128MB boot area */ +#endif +#define CONFIG_SPL_DMA_SUPPORT + +#endif /* CONFIG_SPL_BUILD*/ + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_BOARD_LATE_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB + +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_PHY_REALTEK +#define CONFIG_FEC_MXC_PHYADDR 3 +#else +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_PHY_ATHEROS +#define CONFIG_PHY_GIGE +#endif + +#endif + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(fit),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +/* Initial environment variables */ +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "bootargs=console=${console} ubi.mtd=5 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x5000000 0x1400000;"\ + "nand read ${fdt_addr} 0x7000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr}" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else booti ${loadaddr} - ${fdt_addr}; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" +#endif + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_TEXT_BASE 0x40200000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR3L for two rank */ +#else +#define PHYS_SDRAM_SIZE 0x100000000 /* 4GB DDR4 */ +#endif +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_ARM2 +#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */ +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 1 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define FSL_QSPI_FLASH_SIZE (SZ_2M) +#define FSL_QSPI_FLASH_NUM 2 +#endif + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#ifdef CONFIG_TARGET_IMX8MQ_DDR4_ARM2 +#define CONFIG_NAND_MXS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_IMX8M +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_XHCI_HCD +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 + +#define CONFIG_USB_DWC3 +#define CONFIG_USB_DWC3_GADGET +#define CONFIG_USBD_HS + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "FSL" + +#endif + +#define CONFIG_OF_SYSTEM_SETUP + +#endif |