diff options
| author | Peng Fan <peng.fan@nxp.com> | 2017-09-20 15:07:53 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2017-09-20 15:45:56 +0800 |
| commit | e7cdf55baf73d67c72fdc61a3e92d5b2e09b702a (patch) | |
| tree | f13ad44a5044c7013966de3928b3070d7cddb6de | |
| parent | 34be5a21002132b3908bf1aada7e15aa00353ce9 (diff) | |
MLK-16496-1 imx8qm/qxp: set usdhc clock to 400M
Set usdhc clock to 400M. When enabling HS400 ES, DDR EN is enabled,
if we still have input clock as 200M, the real output clock will be 100M.
So set clock to 400M to get real 200M output when enabling HS400/ES.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv8/imx8/clock.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/imx8/clock.c b/arch/arm/cpu/armv8/imx8/clock.c index 01f53b2057..bd34f45e64 100644 --- a/arch/arm/cpu/armv8/imx8/clock.c +++ b/arch/arm/cpu/armv8/imx8/clock.c @@ -254,7 +254,7 @@ void init_clk_usdhc(u32 index) sc_err_t err; sc_ipc_t ipc; - sc_pm_clock_rate_t actual = 200000000; + sc_pm_clock_rate_t actual = 400000000; ipc = gd->arch.ipc_channel_handle; @@ -267,8 +267,8 @@ void init_clk_usdhc(u32 index) return; } - if (actual != 200000000) - debug("Actual rate for SDHC_%d is %d\n", index, actual); + if (actual != 400000000) + printf("Actual rate for SDHC_%d is %d\n", index, actual); err = sc_pm_clock_enable(ipc, usdhcs[index], SC_PM_CLK_PER, true, false); if (err != SC_ERR_NONE) { |