diff options
| author | Ye Li <ye.li@nxp.com> | 2017-08-29 02:36:52 -0500 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-08-29 21:39:16 -0500 |
| commit | c80d9c1d8b9a7ab0a17ec6c8bdfe174ad2be434a (patch) | |
| tree | c495b8035efcea95d863a0588b1cf6ceb30ce080 | |
| parent | b857d65dddd5d65dac75483271c9ef745439e073 (diff) | |
MLK-16249 mx6dlsabresd: Fix the VDD ARM voltage for 396MHz CPU freq
According to the MX6DL datasheet (IMX6SDLCEC Rev. 5, 06/2015)
"LDO Output Set Point (VDD_ARM_CAP) = 1.125 V minimum for operation
up to 396 MHz."
So change the VDD ARM to 1.15V (with 25mv margin).
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
| -rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 9f60943b6d..c9521c1948 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -1201,7 +1201,7 @@ void ldo_mode_set(int ldo_bypass) * VDDARM:0.975V@400M; VDDSOC:1.175V@400M * MX6DL: * VDDARM:1.175V@800M; VDDSOC:1.175V@800M - * VDDARM:1.075V@400M; VDDSOC:1.175V@400M + * VDDARM:1.15V@400M; VDDSOC:1.175V@400M */ is_400M = set_anatop_bypass(2); if (is_mx6dqp()) { @@ -1216,7 +1216,7 @@ void ldo_mode_set(int ldo_bypass) if (is_400M) { if (is_mx6dl()) - vddarm = 0x1f; + vddarm = 0x22; else vddarm = 0x1b; } else { @@ -1290,7 +1290,7 @@ void ldo_mode_set(int ldo_bypass) * VDDARM:0.975V@400M; VDDSOC:1.175V@400M * MX6DL: * VDDARM:1.175V@800M; VDDSOC:1.175V@800M - * VDDARM:1.075V@400M; VDDSOC:1.175V@400M + * VDDARM:1.15V@400M; VDDSOC:1.175V@400M */ is_400M = set_anatop_bypass(2); if (is_mx6dqp()) { @@ -1302,7 +1302,7 @@ void ldo_mode_set(int ldo_bypass) if (is_400M) { if (is_mx6dl()) - vddarm = 0x1f; + vddarm = 0x22; else vddarm = 0x1b; } else { |