MLK-16292 DTS: imx8qm/qxp: Update usdhc pad settings to fix DSE issue

Sychronize the usdhc pad settings from kernel DTS file to
fix DSE setting problem. For dual voltage pads, only bits[0]
is defined for DSE.
0: high drive strength
1: low drive strength

Kernel commit: 7084cf02e6cc2c9fb7f474f6cc1ba8f8d00793c7

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

3 files changed, 116 insertions, 115 deletions

diff --git a/arch/arm/dts/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm/dts/fsl-imx8qm-lpddr4-arm2.dts
index 03dd2c58b0..4730b27f76 100644
--- a/arch/arm/dts/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm/dts/fsl-imx8qm-lpddr4-arm2.dts
@@ -151,41 +151,42 @@
 				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
 				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
 				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
 				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
 			>;
 		};
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000045
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000025
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000025
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000025
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000025
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000025
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000025
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000025
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000025
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000025
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000045
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000047
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000027
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000027
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000027
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000027
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000027
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000027
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000027
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000027
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000027
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000047
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
 			>;
 		};
 
@@ -211,31 +212,31 @@
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000045
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000025
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000025
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000025
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000025
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000025
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
 			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000047
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000027
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000027
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000027
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000027
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000027
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
 			>;
 		};
 
 		pinctrl_usdhc3: usdhc3grp {
 			fsl,pins = <
-				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000021
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000041
 				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000021
 				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000021
 				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000021
diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts
index d044ca762e..c807a545a0 100644
--- a/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts
@@ -144,41 +144,41 @@
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000045
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000025
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000025
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000025
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000025
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000025
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000025
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000025
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000025
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000025
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000045
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000047
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000027
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000027
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000027
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000027
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000027
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000027
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000027
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000027
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000027
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000047
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
 			>;
 		};
 
 		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 			fsl,pins = <
-				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x06000048
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x06000021
 				SC_P_USDHC1_WP_LSIO_GPIO4_IO21		0x06000021
 				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x06000021
 			>;
@@ -198,25 +198,25 @@
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000045
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000025
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000025
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000025
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000025
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000025
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000021
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000020
 			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000047
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000027
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000027
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000027
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000027
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000027
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000021
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000020
 			>;
 		};
 
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
index 4282522dad..064ecb84ce 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek.dts
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -127,39 +127,39 @@
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000045
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000025
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000025
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000025
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000025
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000025
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000025
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000025
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000025
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000025
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000045
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000047
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000027
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000027
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000027
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000027
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000027
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000027
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000027
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000027
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000027
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000047
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
 			>;
 		};
 
 		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 			fsl,pins = <
-				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x06000048
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x06000021
 				SC_P_USDHC1_WP_LSIO_GPIO4_IO21		0x06000021
 				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x06000021
 			>;
@@ -179,25 +179,25 @@
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000045
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000025
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000025
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000025
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000025
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000025
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000021
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000020
 			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000047
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000027
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000027
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000027
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000027
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000027
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000021
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000020
 			>;
 		};