diff options
author | Li Jun <jun.li@nxp.com> | 2017-08-26 02:10:50 +0800 |
---|---|---|
committer | Li Jun <jun.li@nxp.com> | 2017-08-29 17:17:18 +0800 |
commit | a8247ecb7ff1c955d68fe4c7650fd8c062fbb14c (patch) | |
tree | 30f38d6c522e0eddcbcb86009ef3e704f13dbbf6 | |
parent | 83f152efe31d7ab6c3e713acb389eddbabfb0234 (diff) |
MLK-16273-2 imx8mq: evk: add usb init for USB0 device mode
Add USB0(type-c) config and PHY init to enable device mode.
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
-rw-r--r-- | board/freescale/imx8mq_evk/imx8m_evk.c | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/board/freescale/imx8mq_evk/imx8m_evk.c b/board/freescale/imx8mq_evk/imx8m_evk.c index 842eda783c..14542dc76e 100644 --- a/board/freescale/imx8mq_evk/imx8m_evk.c +++ b/board/freescale/imx8mq_evk/imx8m_evk.c @@ -24,6 +24,8 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" +#include <usb.h> +#include <dwc3-uboot.h> DECLARE_GLOBAL_DATA_PTR; @@ -134,6 +136,71 @@ int board_phy_config(struct phy_device *phydev) } #endif +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_SUPER, + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} + +int board_usb_init(int index, enum usb_init_type init) +{ + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + dwc3_uboot_exit(index); + return 0; +} +#endif + int board_init(void) { board_qspi_init(); |