diff options
| author | Ye Li <ye.li@nxp.com> | 2017-08-30 21:58:03 -0500 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-08-30 22:31:48 -0500 |
| commit | 1ffcff6a1e34929c977bac63a894273ceba40864 (patch) | |
| tree | 7dbd8153faf4b88341c471f36153e07733f709ea | |
| parent | 603b764ad5c7b0bd7f0db62608573974592be832 (diff) | |
MLK-16333 imx8qm/qxp: Change memory region 0x0-0x1c000000 to strongly order
This memory region is for LSIO subsystem, including OCRAM, AP ROM,
flexspi0 mapped memory and flexspi1 buffer. If we set it to cachable,
the AHB read in flexspi driver will have coherence problem.
This patch set this memory region to strongly order to avoid any issue
in driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv8/imx8/cpu.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/imx8/cpu.c b/arch/arm/cpu/armv8/imx8/cpu.c index 2b26c0863e..64af4b0caa 100644 --- a/arch/arm/cpu/armv8/imx8/cpu.c +++ b/arch/arm/cpu/armv8/imx8/cpu.c @@ -992,8 +992,7 @@ void dram_init_banksize(void) static u64 get_block_attrs(sc_faddr_t addr_start) { if ((addr_start >= PHYS_SDRAM_1 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) - || (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) - || (addr_start >= 0x0 && addr_start <= ((sc_faddr_t)0x20000000))) + || (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); return (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN); |