diff options
| author | Ye Li <ye.li@nxp.com> | 2018-07-04 18:49:59 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-07-05 18:47:45 -0700 |
| commit | fc72bf2b5ce59994765da6c5e66745d037e05237 (patch) | |
| tree | c24a5b2496ac04584c13c19f861fc70c430cc8b1 | |
| parent | d2d2e56b29c136793bd4b398ce16b3e5442c7f72 (diff) | |
MLK-18623-2 imx8mm_val: use clock API to set DRAM APB clock
Change to use clock API "clock_set_target_val" to set DRAM APB clock
root for DDR4 init.
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c index 3d6373dde4..a5c39d6227 100644 --- a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c +++ b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c @@ -220,8 +220,7 @@ void ddr4_pub_train(void) reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* deassert [4]src_system_rst_b! */ /* change the clock source of dram_apb_clk_root */ - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16)); - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x3 << 16)); /* to source 4 --800MHz/4 */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* to source 4 --800MHz/4 */ /* DDR_PLL_CONFIG_600MHz(); */ dram_pll_init(DRAM_PLL_OUT_600M); |