MLK-18926-3 ARM64: dts: fsl-imx8mq: correct usdhc pad SRE setting

According to RM, usdhc 100MHz pad setting need to set SRE(slew rate
field) to 0x01(Medium Frequency Slew Rate 100MHz), usdhc 200MHz pad
setting need to set SRE to 0x11(Max Frequency Slew Rate 200MHz).

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

3 files changed, 102 insertions, 102 deletions

diff --git a/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts b/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts
index 0234ee2f76..1dfcfe429d 100644
--- a/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts
+++ b/arch/arm/dts/fsl-imx8mq-ddr3l-arm2.dts
@@ -187,34 +187,34 @@
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x85
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x8d
 				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x87
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x9f
 				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
 			>;
 		};
@@ -240,24 +240,24 @@
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
 				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
 			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
 				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
 			>;
 		};
diff --git a/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts b/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts
index 0b6136de64..ef1feef41e 100644
--- a/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts
+++ b/arch/arm/dts/fsl-imx8mq-ddr4-arm2.dts
@@ -170,34 +170,34 @@
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x85
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x8d
 				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x87
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x9f
 				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
 			>;
 		};
@@ -223,24 +223,24 @@
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
 				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
 			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
 				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
 			>;
 		};
diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
index 4213a37fa1..6e67596320 100644
--- a/arch/arm/dts/fsl-imx8mq-evk.dts
+++ b/arch/arm/dts/fsl-imx8mq-evk.dts
@@ -195,34 +195,34 @@
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x85
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x8d
 				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x87
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x9f
 				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
 			>;
 		};
@@ -248,24 +248,24 @@
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
 				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
 			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
 				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
 			>;
 		};