diff options
| author | Ye Li <ye.li@nxp.com> | 2018-07-11 03:17:14 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-07-11 18:54:13 -0700 |
| commit | 85be73bb5bab319c096f0893729835b3ceddafde (patch) | |
| tree | 26be46138faae8b0350b8111192125785f9bb4b7 | |
| parent | ca96e0bd1aea1996904b0a71fb1d74c3f5176929 (diff) | |
MLK-18823 mx6ul/mx6ull: Add workaround for LCDIF display when optee enabled
In optee enabled defconfig, the trust zone is enabled in DCD. On iMX6UL/ULL, there
is IC limitation that LCDIF master access can only be non-secure, because PL301
hard code the m_3/4/5 to non-secure masters. It causes LCDIF fails to fetch data
from memory.
This patch adds a workaround to change trust zone Region 0 attribute to allow both secure
and non-secure read/write. So it permits the LCDIF master access to memory.
Since optee will configure Region 0 by itself, this should not introduce problem to optee.
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 45e41dd45c..cbb78bf887 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -3,6 +3,7 @@ * Sascha Hauer, Pengutronix * * (C) Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -589,6 +590,19 @@ int arch_cpu_init(void) 0x3, MX6UL_SNVS_LP_BASE_ADDR); } + if (is_mx6ull() || is_mx6ul()) { + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + if (iomux->gpr[9] & 0x1) { + /* When trust zone is enabled, + * set Region 0 attribute to allow secure and non-secure read/write permission + * Because PL301 hard code to non-secure for some masters on m_3/4/5 ports. + * Like LCDIF, PXP, CSI can't work with secure memory. + */ + + writel(0xf0000000, IP2APB_TZASC1_BASE_ADDR + 0x108); + } + } + /* Set perclk to source from OSC 24MHz */ #if defined(CONFIG_MX6SL) set_preclk_from_osc(); |