diff options
| author | Tom.zheng <haidong.zheng@nxp.com> | 2018-04-25 13:51:39 +0800 |
|---|---|---|
| committer | Bai Ping <ping.bai@nxp.com> | 2018-08-31 15:01:44 +0800 |
| commit | 74697e36df34dae033337b8b4591a7c2b95360fb (patch) | |
| tree | 11ac9b36c1a3741e679971517d0936e08e0f23e7 | |
| parent | a856985636d3a112d0b4741231bc3d3e20f2f1dc (diff) | |
MLK-19380 imx8mq_evk: update the ddr controller QoS setting
enhance memory controller performance and QoS setting
Signed-off-by: Tom.zheng <haidong.zheng@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
(cherry picked from commit ae7b37d3ed72bad542c8e77db4bbc0325180d6d2)
| -rw-r--r-- | board/freescale/imx8mq_evk/ddr/ddr_init.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/board/freescale/imx8mq_evk/ddr/ddr_init.c b/board/freescale/imx8mq_evk/ddr/ddr_init.c index b6d922f39c..e6796835dd 100644 --- a/board/freescale/imx8mq_evk/ddr/ddr_init.c +++ b/board/freescale/imx8mq_evk/ddr/ddr_init.c @@ -127,8 +127,10 @@ void lpddr4_800MHz_cfg_umctl2(void) dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505); dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c); dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b); - dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009); - dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574); + /* 150T starve and 0x90 max tran len */ + dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x90000096); + /* 300T starve and 0x10 max tran len */ + dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x1000012c); dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016); dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000); dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000); @@ -138,10 +140,12 @@ void lpddr4_800MHz_cfg_umctl2(void) dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3); dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff); dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001); - dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00); - dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790); - dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001); - dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f); + /* disable Read Qos*/ + dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x00000e00); + dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x0062ffff); + /* disable Write Qos*/ + dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00000e00); + dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000ffff); dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202); dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5); dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040); |