diff options
author | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2023-02-03 15:45:06 +0100 |
---|---|---|
committer | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2023-02-07 17:15:23 +0100 |
commit | 48d60e0a701e350ff1351f842882e5751b395e93 (patch) | |
tree | def3380020373e2632d4ce987afdcd51c6381a79 | |
parent | be65df37e9a9bb9460db60afe3e5e9872ed2d280 (diff) |
board: verdin-imx8mp: fix LPDDR4 refresh timing
Change tRFCmin (tRFCab) from 280 ns to 380 ns to be compliant with
current and futures memories.
Fixes: 2bc2f817cea7 ("board: toradex: add verdin imx8m plus support")
Upstream-Status: Pending
Waiting for internal test and validation before sending to upstream.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
-rw-r--r-- | board/toradex/verdin-imx8mp/lpddr4_timing.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c index 314b74e7df..58278d2150 100644 --- a/board/toradex/verdin-imx8mp/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c @@ -21,7 +21,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400000, 0xa3080020 }, { 0x3d400020, 0x1303 }, { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, + { 0x3d400064, 0x7a017c }, { 0x3d400070, 0x61027f10 }, { 0x3d400074, 0x7b0 }, { 0x3d4000d0, 0xc00307a3 }, @@ -39,7 +39,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40011c, 0x501 }, { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, + { 0x3d400138, 0x184 }, { 0x3d400144, 0xc80064 }, { 0x3d400180, 0x3e8001e }, { 0x3d400184, 0x3207a12 }, @@ -77,7 +77,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402020, 0x1001 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, + { 0x3d402064, 0xc0026 }, { 0x3d4020dc, 0x840000 }, { 0x3d4020e0, 0x330000 }, { 0x3d4020e8, 0x660048 }, @@ -92,7 +92,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40211c, 0x301 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, + { 0x3d402138, 0x27 }, { 0x3d402144, 0x14000a }, { 0x3d402180, 0x640004 }, { 0x3d402190, 0x3818200 }, @@ -102,7 +102,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, + { 0x3d403064, 0x3000a }, { 0x3d4030dc, 0x840000 }, { 0x3d4030e0, 0x330000 }, { 0x3d4030e8, 0x660048 }, @@ -117,7 +117,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40311c, 0x301 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, + { 0x3d403138, 0xa }, { 0x3d403144, 0x50003 }, { 0x3d403180, 0x190004 }, { 0x3d403190, 0x3818200 }, @@ -1841,7 +1841,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d400000, 0xa1080020 }, { 0x3d400020, 0x1303 }, { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, + { 0x3d400064, 0x7a017c }, { 0x3d400070, 0x61027f10 }, { 0x3d400074, 0x7b0 }, { 0x3d4000d0, 0xc00307a3 }, @@ -1859,7 +1859,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d40011c, 0x501 }, { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, + { 0x3d400138, 0x184 }, { 0x3d400144, 0xc80064 }, { 0x3d400180, 0x3e8001e }, { 0x3d400184, 0x3207a12 }, @@ -1897,7 +1897,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d402020, 0x1001 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, + { 0x3d402064, 0xc0026 }, { 0x3d4020dc, 0x840000 }, { 0x3d4020e0, 0x330000 }, { 0x3d4020e8, 0x660048 }, @@ -1912,7 +1912,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d40211c, 0x301 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, + { 0x3d402138, 0x27 }, { 0x3d402144, 0x14000a }, { 0x3d402180, 0x640004 }, { 0x3d402190, 0x3818200 }, @@ -1922,7 +1922,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, + { 0x3d403064, 0x3000a }, { 0x3d4030dc, 0x840000 }, { 0x3d4030e0, 0x330000 }, { 0x3d4030e8, 0x660048 }, @@ -1937,7 +1937,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d40311c, 0x301 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, + { 0x3d403138, 0xa }, { 0x3d403144, 0x50003 }, { 0x3d403180, 0x190004 }, { 0x3d403190, 0x3818200 }, |