pmic: initial code for pmic otp programming

- move current code in its own source file
- add OTP programming code, results to be tested
- add OTP settings file, generated from excel
  check sed commands to convert from text output to c-code

6 files changed, 527 insertions, 62 deletions

diff --git a/board/toradex/apalis_imx6/Makefile b/board/toradex/apalis_imx6/Makefile
index 8b84c1f177..0fe2c608e7 100644
--- a/board/toradex/apalis_imx6/Makefile
+++ b/board/toradex/apalis_imx6/Makefile
@@ -9,7 +9,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
-COBJS  := apalis_imx6.o
+COBJS  := apalis_imx6.o pf0100.o
 
 SRCS   := $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 7e6c6a42d6..f40e78dd2f 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
- * Copyright (C) 2013, Toradex AG
+ * Copyright (C) 2014, Toradex AG
  * copied from nitrogen6x
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -30,6 +30,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <i2c.h>
+#include "pf0100.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -758,66 +759,6 @@ static void setup_display(void)
 }
 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 
-/* 7-bit I2C bus slave address */
-#define PFUZE100_I2C_ADDR 		(0x08)
-#define PFUZE100_DEVICEID		(0x0)
-#define PFUZE100_REVID			(0x3)
-#define PFUZE100_SW1AMODE		(0x23)
-#define PFUZE100_SW1ACON		36
-#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
-#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
-#define PFUZE100_SW1CCON		49
-#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
-#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
-#define PFUZE100_SW1AVOL		32
-#define PFUZE100_SW1AVOL_VSEL_M		(0x3f<<0)
-#define PFUZE100_SW1CVOL		46
-#define PFUZE100_SW1CVOL_VSEL_M		(0x3f<<0)
-#define PFUZE100_VGEN1CTL		(0x6c)
-#define PFUZE100_VGEN1_VAL		(0x30 + 0x08) /* Always ON, 1.2V */
-#define PFUZE100_SWBSTCTL		(0x66)
-#define PFUZE100_SWBST_VAL		(0x40 + 0x08 + 0x00) /* Always ON, Auto Switching Mode, 5.0V */
-
-void pmic_init(void)
-{
-	uchar bus = 1;
-	uchar devid, revid, val;
-
-	puts("PMIC: ");
-	if(!(0 == i2c_set_bus_num(bus) && (0 == i2c_probe(PFUZE100_I2C_ADDR))))
-	{
-		puts("i2c bus failed\n");
-		return;
-	}
-	/* get device ident */
-	if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0)
-	{
-		puts("i2c pmic devid read failed\n");
-		return;
-	}
-	if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0)
-	{
-		puts("i2c pmic revid read failed\n");
-		return;
-	}
-	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
-
-	/* set VGEN1 to 1.2V */
-	val = PFUZE100_VGEN1_VAL;
-	if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1, &val, 1))
-	{
-		puts("i2c write failed\n");
-		return;
-	}
-	/* set SWBST to 5.0V */
-	val = PFUZE100_SWBST_VAL;
-	if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1, &val, 1))
-	{
-		puts("i2c write failed\n");
-		return;
-	}
-}
-
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
new file mode 100644
index 0000000000..23c17d7f24
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2014, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#include <common.h>
+#include <i2c.h>
+
+#include "pf0100_otp.inc"
+#include "pf0100.h"
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR 		(0x08)
+
+void pmic_init(void)
+{
+	uchar bus = 1;
+	uchar devid, revid, val;
+
+	puts("PMIC: ");
+	if(!(0 == i2c_set_bus_num(bus) && (0 == i2c_probe(PFUZE100_I2C_ADDR))))
+	{
+		puts("i2c bus failed\n");
+		return;
+	}
+	/* get device ident */
+	if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0)
+	{
+		puts("i2c pmic devid read failed\n");
+		return;
+	}
+	if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0)
+	{
+		puts("i2c pmic revid read failed\n");
+		return;
+	}
+	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+
+	/* set VGEN1 to 1.2V */
+	val = PFUZE100_VGEN1_VAL;
+	if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1, &val, 1))
+	{
+		puts("i2c write failed\n");
+		return;
+	}
+
+	/* set SWBST to 5.0V */
+	val = PFUZE100_SWBST_VAL;
+	if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1, &val, 1))
+	{
+		puts("i2c write failed\n");
+		return;
+	}
+}
+
+void pf0100_prog(void)
+{
+	unsigned char bus = 1;
+	unsigned char val;
+	unsigned i;
+
+	if(!(0 == i2c_set_bus_num(bus) && (0 == i2c_probe(PFUZE100_I2C_ADDR))))
+	{
+		puts("i2c bus failed\n");
+		return;
+	}
+
+	for (i=0; i<ARRAY_SIZE(pmic_otp_prog); i++) {
+		switch(pmic_otp_prog[i].cmd) {
+		case pmic_i2c:
+			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
+			if( i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
+					1, &val, 1))
+			{
+				printf("i2c write failed, reg 0x%2x, value0x%2x\n",
+						pmic_otp_prog[i].reg, val);
+				return;
+			}
+			break;
+		case pmic_delay:
+			udelay(pmic_otp_prog[i].value * 1000);
+			break;
+		case pmic_vpgm:
+			/* TODO */
+			break;
+		case pmic_pwr:
+			/* TODO */
+			break;
+		}
+	}
+}
+
+
+static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	puts("Programming PMIC OTP...");
+	pf0100_prog();
+	puts("done. Power cycle the board\n");
+	return 0;
+}
+
+U_BOOT_CMD(
+        pf0100_otp_prog, 1, 0, do_pf0100_prog,
+        "Program the OTP fuses on the PMIC PF0100",
+        ""
+);
diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h
new file mode 100644
index 0000000000..dabec3e121
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2014, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#ifndef PF0100_H_
+#define PF0100_H_
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR 		(0x08)
+/* Register Addresses */
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_SW1AMODE		(0x23)
+#define PFUZE100_SW1ACON		36
+#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1AVOL		32
+#define PFUZE100_SW1AVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_SW1CVOL		46
+#define PFUZE100_SW1CVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_VGEN1CTL		(0x6c)
+#define PFUZE100_VGEN1_VAL		(0x30 + 0x08) /* Always ON, 1.2V */
+#define PFUZE100_SWBSTCTL		(0x66)
+#define PFUZE100_SWBST_VAL		(0x40 + 0x08 + 0x00) /* Always ON, Auto Switching Mode, 5.0V */
+
+/* enables some rails on a not programmed PMIC */
+/* VGEN1 to 1.2V, set SWBST to 5.0V */
+void pmic_init(void);
+
+/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
+void pf0100_prog(void);
+
+#endif /* PF0100_H_ */
diff --git a/board/toradex/apalis_imx6/pf0100_otp.inc b/board/toradex/apalis_imx6/pf0100_otp.inc
new file mode 100644
index 0000000000..ea2727144a
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100_otp.inc
@@ -0,0 +1,185 @@
+/*

+ * Copyright (C) 2014, Toradex AG

+ *

+ * SPDX-License-Identifier:	GPL-2.0+

+ */

+

+// Register Output for PF0100 programmer

+// Customer: Toradex AG

+// Program: Apalis iMX6

+// Sample marking: 

+// Date: 20.11.2013

+// Time: 09:17:36

+// Generated from Spreadsheet Revision: P1.8

+

+/* sed commands to get from programmer script to struct */

+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc

+   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc

+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */

+

+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };

+struct pmic_otp_prog_t{

+	unsigned char cmd;

+	unsigned char reg;

+	unsigned short value;

+};

+

+struct pmic_otp_prog_t pmic_otp_prog[] = {

+{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1

+{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94

+{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95

+{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96

+{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102

+{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103

+{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104

+{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106

+{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108

+{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110

+{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111

+{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112

+{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114

+{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115

+{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116

+{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118

+{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120

+{pmic_i2c, 0xBD, 0x0A}, // Auto gen from Row123

+{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126

+{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130

+{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134

+{pmic_i2c, 0xC9, 0x09}, // Auto gen from Row135

+{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138

+{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139

+{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142

+{pmic_i2c, 0xD1, 0x06}, // Auto gen from Row143

+{pmic_i2c, 0xD5, 0x08}, // Auto gen from Row147

+{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150

+{pmic_i2c, 0xD9, 0x07}, // Auto gen from Row151

+{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154

+{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155

+{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158

+// Write OTP

+{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1

+{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1

+{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1

+{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register

+{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register

+{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2

+{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register

+{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST

+//VPGM:DOWN:n

+//VPGM:UP:n

+{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up

+//-----------------------------------------------------------------------------------

+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)

+//-----------------------------------------------------------------------------------

+// BANK 1

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN

+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 2

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN

+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 3

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN

+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 4

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN

+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 5

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN

+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 6

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN

+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 7

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN

+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 8

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN

+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 9

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN

+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 10

+//-----------------------------------------------------------------------------------

+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN

+{pmic_delay, 0, 10}, // Allow time for bank programming to complete

+{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN

+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+{pmic_vpgm, 0, 0}, // Turn off 8V SWBST

+{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off

+{pmic_i2c, 0xD0, 0x00}, // Clear

+{pmic_i2c, 0xD1, 0x00}, // Clear

+{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data

+{pmic_delay, 0, 500},

+{pmic_pwr, 0, 1},

+};
\ No newline at end of file
diff --git a/board/toradex/apalis_imx6/pf0100_otp.txt b/board/toradex/apalis_imx6/pf0100_otp.txt
new file mode 100644
index 0000000000..dea3e79e69
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100_otp.txt
@@ -0,0 +1,185 @@
+/*

+ * Copyright (C) 2014, Toradex AG

+ *

+ * SPDX-License-Identifier:	GPL-2.0+

+ */

+

+// Register Output for PF0100 programmer

+// Customer: Toradex AG

+// Program: Apalis iMX6

+// Sample marking: 

+// Date: 20.11.2013

+// Time: 09:17:36

+// Generated from Spreadsheet Revision: P1.8

+

+/* sed commands to get from programmer script to struct */

+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc

+   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc

+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */

+

+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };

+struct pmic_otp_prog_t{

+	unsigned char cmd;

+	unsigned char reg;

+	unsigned short value;

+};

+

+struct pmic_otp_prog_t pmic_otp_prog[] = {

+WRITE_I2C:7F:01 // Access FSL EXT Page 1

+WRITE_I2C:A0:2B // Auto gen from Row94

+WRITE_I2C:A1:01 // Auto gen from Row95

+WRITE_I2C:A2:05 // Auto gen from Row96

+WRITE_I2C:A8:2B // Auto gen from Row102

+WRITE_I2C:A9:02 // Auto gen from Row103

+WRITE_I2C:AA:01 // Auto gen from Row104

+WRITE_I2C:AC:18 // Auto gen from Row106

+WRITE_I2C:AE:01 // Auto gen from Row108

+WRITE_I2C:B0:2C // Auto gen from Row110

+WRITE_I2C:B1:04 // Auto gen from Row111

+WRITE_I2C:B2:01 // Auto gen from Row112

+WRITE_I2C:B4:2C // Auto gen from Row114

+WRITE_I2C:B5:04 // Auto gen from Row115

+WRITE_I2C:B6:01 // Auto gen from Row116

+WRITE_I2C:B8:18 // Auto gen from Row118

+WRITE_I2C:BA:01 // Auto gen from Row120

+WRITE_I2C:BD:0A // Auto gen from Row123

+WRITE_I2C:C0:06 // Auto gen from Row126

+WRITE_I2C:C4:04 // Auto gen from Row130

+WRITE_I2C:C8:0E // Auto gen from Row134

+WRITE_I2C:C9:09 // Auto gen from Row135

+WRITE_I2C:CC:0E // Auto gen from Row138

+WRITE_I2C:CD:05 // Auto gen from Row139

+WRITE_I2C:D0:0C // Auto gen from Row142

+WRITE_I2C:D1:06 // Auto gen from Row143

+WRITE_I2C:D5:08 // Auto gen from Row147

+WRITE_I2C:D8:07 // Auto gen from Row150

+WRITE_I2C:D9:07 // Auto gen from Row151

+WRITE_I2C:DC:0A // Auto gen from Row154

+WRITE_I2C:DD:03 // Auto gen from Row155

+WRITE_I2C:E0:05 // Auto gen from Row158

+// Write OTP

+WRITE_I2C:E4:02 // FUSE POR1=1

+WRITE_I2C:E5:02 // FUSE POR2=1

+WRITE_I2C:E6:02 // FUSE POR3=1

+WRITE_I2C:F0:1F // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register

+WRITE_I2C:F1:1F // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register

+WRITE_I2C:7F:02 // Access PF0100 EXT Page2

+WRITE_I2C:D0:1F // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register

+WRITE_I2C:D1:1F // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+VPGM:ON // Turn ON 8V SWBST

+//VPGM:DOWN:n

+//VPGM:UP:n

+DELAY:500 // Adds 500msec delay to allow VPGM time to ramp up

+//-----------------------------------------------------------------------------------

+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)

+//-----------------------------------------------------------------------------------

+// BANK 1

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F1:03 // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F1:0B // Set Bank 1 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F1:03 // Reset Bank 1 ANTIFUSE_EN

+WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 2

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F2:03 // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F2:0B // Set Bank 2 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F2:03 // Reset Bank 2 ANTIFUSE_EN

+WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 3

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F3:03 // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F3:0B // Set Bank 3 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F3:03 // Reset Bank 3 ANTIFUSE_EN

+WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 4

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F4:03 // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F4:0B // Set Bank 4 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F4:03 // Reset Bank 4 ANTIFUSE_EN

+WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 5

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F5:03 // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F5:0B // Set Bank 5 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F5:03 // Reset Bank 5 ANTIFUSE_EN

+WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 6

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F6:03 // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F6:0B // Set Bank 6 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F6:03 // Reset Bank 6 ANTIFUSE_EN

+WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 7

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F7:03 // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F7:0B // Set Bank 7 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F7:03 // Reset Bank 7 ANTIFUSE_EN

+WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 8

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F8:03 // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F8:0B // Set Bank 8 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F8:03 // Reset Bank 8 ANTIFUSE_EN

+WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 9

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F9:03 // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F9:0B // Set Bank 9 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F9:03 // Reset Bank 9 ANTIFUSE_EN

+WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 10

+//-----------------------------------------------------------------------------------

+WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:FA:03 // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:FA:0B // Set Bank 10 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:FA:03 // Reset Bank 10 ANTIFUSE_EN

+WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+VPGM:OFF // Turn off 8V SWBST

+DELAY:500 // Adds delay to allow VPGM to bleed off

+WRITE_I2C:D0:00 // Clear

+WRITE_I2C:D1:00 // Clear

+PWRON:LOW // PWRON LOW to reload new OTP data

+DELAY:500

+PWRON: HIGH

+};
\ No newline at end of file