diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-05-09 03:01:32 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-05-09 03:01:32 +0200 |
| commit | fbcc83d7214d1e2989201b692c07f9b3241af4cf (patch) | |
| tree | b24d502577a0a5b7fa510347d04befbe1396a7b7 | |
| parent | 72dd7f8c0934988e3cf2553b5f97de68e28156e8 (diff) | |
apalis/colibri_t30: increase CPU frequency at boot
Due to a unoptimised PLL X table we were only running at 400MHz during
boot.
Incorporated the PLL X table from NVIDIA's latest public U-Boot sources:
http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/u-boot.git;a=blob;f=arch/arm/cpu/arm720t/tegra-common/cpu.c;h=119342e9577f6b42f93d118b81c0e931c9c9423a;hb=chromeos/v2013.01.01-tegra114#l67
And actually set up the T30 PLLs regardless of slow flag as this is
anyway exclusively used on T20.
Issue report courtesy of Mariusz Bulkowski from Draminski.
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/ap20.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c index 62fdc2f299..07a3e2c9e5 100644 --- a/arch/arm/cpu/armv7/tegra-common/ap20.c +++ b/arch/arm/cpu/armv7/tegra-common/ap20.c @@ -65,18 +65,18 @@ static struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_COUNT] { 600, 13, 0, 12}, }, - /* T30: 1.5 GHz with slower (216MHz) PLLP */ - {{ 0xd8, 13, 1, 8}, - { 0xb4, 22, 1, 4}, - { 0x1b0, 12, 1, 8}, - { 0xd8, 26, 1, 8}, + /* T30: 1.4 GHz with slower (216MHz) PLLP */ + {{ 862, 8, 1, 8}, + { 583, 8, 1, 4}, + { 700, 6, 1, 8}, + { 700, 13, 1, 8}, }, - /* T30: 1.5 GHz with 408MHz PLLP */ - {{ 0x198, 13, 0, 8}, - { 0x154, 22, 0, 4}, - { 0x198, 12, 0, 8}, - { 0x198, 26, 0, 8}, + /* T30: 1.4 GHz with 408MHz PLLP */ + {{ 862, 8, 0, 8}, + { 583, 8, 0, 4}, + { 700, 6, 0, 8}, + { 700, 13, 0, 8}, }, /* TEGRA_SOC2_SLOW: 312 MHz */ @@ -223,8 +223,8 @@ void ap20_init_pllx(int slow) sel = &tegra_pll_x_table[chip_type][osc]; pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); - /* once we are out of slow mode, set up the T30 PLLs also */ - if (!slow && chip_type == TEGRA_SOC_T30_408MHZ) + /* set up the T30 PLLs also */ + if (chip_type == TEGRA_SOC_T30_408MHZ) adjust_pllp_out_freqs(); } |