diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2012-11-27 13:37:10 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2012-11-28 13:00:10 +0100 |
| commit | fb0920943e34158a4bed5aeaefa6014b343836e5 (patch) | |
| tree | 7c0a1627d13ae1ff83e2049066ff423de261ed77 | |
| parent | ce9bf6f809d728004194cca71622e4dadd86fea1 (diff) | |
CPU reset bitfields: - fix bitpositions in CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/clock.h | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 83abc43158..84d215aa4b 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -133,10 +133,17 @@ void reset_set_enable(enum periph_id periph_id, int enable); /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ enum crc_reset_id { /* Things we can hold in reset for each CPU */ - crc_rst_cpu = 1, - crc_rst_de = 1 << 2, /* What is de? */ - crc_rst_watchdog = 1 << 3, - crc_rst_debug = 1 << 4, + /* Bitpositions for CPU 0 */ + /* TRM T20 V08, 5.4.106 , for CPU 1 shift left by 1 */ + /* TRM T30 V02, 6.5.103 , for CPU 1..3 shift left by 1..3 */ + crc_rst_cpu = 1, /* nCPURESET */ + crc_rst_de = 1 << 4, /* What is de? */ /* nDERESET = renamed to nNEONRESET DDI0388E*/ + crc_rst_watchdog = 1 << 8, /* nWDRESET */ + crc_rst_debug = 1 << 12, /* nDBGRESET */ + /* flags not specific to CPUs but to the CPU complex */ + crc_rst_periph = 1 << 28, /* nPERIPHRESET to the CPU's interrupt/timer */ + crc_rst_scu = 1 << 29, /*nSCURESET to the SCU */ + crc_rst_presetdbg = 1 << 30, /* nPRESETDBG to the coresight */ }; /** |