Patch by Florian Schlote, 08 Sep 2004:

Add support for SenTec-COBRA5272-board (Coldfire).

15 files changed, 1351 insertions, 19 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 4dd8038d96..cdb1913b59 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Patch by Florian Schlote, 08 Sep 2004:
+  Add support for SenTec-COBRA5272-board (Coldfire).
+
 * Patch by Gleb Natapov, 07 Sep 2004:
   mpc824x: set PCI latency timer to a sane value
   (is 0 after reset).
diff --git a/Makefile b/Makefile
index a8b5063992..d5d2713926 100644
--- a/Makefile
+++ b/Makefile
@@ -924,6 +924,9 @@ SL8245_config: unconfig
 utx8245_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x utx8245
 
+cobra5272_config :		unconfig
+	@./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
+
 #########################################################################
 ## MPC8260 Systems
 #########################################################################
diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile
new file mode 100644
index 0000000000..e5d8446313
--- /dev/null
+++ b/board/cobra5272/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/cobra5272/bdm/cobra5272_uboot.gdb b/board/cobra5272/bdm/cobra5272_uboot.gdb
new file mode 100644
index 0000000000..61e778ea5f
--- /dev/null
+++ b/board/cobra5272/bdm/cobra5272_uboot.gdb
@@ -0,0 +1,169 @@
+#
+# GDB Init script for the Coldfire 5272 processor.
+#
+# The main purpose of this script is to configure the 
+# DRAM controller so code can be loaded.
+#
+# This file was changed to suite the senTec COBRA5272 board.
+# 
+
+define addresses
+
+set $mbar  = 0x10000001
+set $scr   = $mbar - 1 + 0x004
+set $spr   = $mbar - 1 + 0x006
+set $pmr   = $mbar - 1 + 0x008
+set $apmr  = $mbar - 1 + 0x00e
+set $dir   = $mbar - 1 + 0x010
+set $icr1  = $mbar - 1 + 0x020
+set $icr2  = $mbar - 1 + 0x024
+set $icr3  = $mbar - 1 + 0x028
+set $icr4  = $mbar - 1 + 0x02c
+set $isr   = $mbar - 1 + 0x030
+set $pitr  = $mbar - 1 + 0x034
+set $piwr  = $mbar - 1 + 0x038
+set $pivr  = $mbar - 1 + 0x03f
+set $csbr0 = $mbar - 1 + 0x040
+set $csor0 = $mbar - 1 + 0x044
+set $csbr1 = $mbar - 1 + 0x048
+set $csor1 = $mbar - 1 + 0x04c
+set $csbr2 = $mbar - 1 + 0x050
+set $csor2 = $mbar - 1 + 0x054
+set $csbr3 = $mbar - 1 + 0x058
+set $csor3 = $mbar - 1 + 0x05c
+set $csbr4 = $mbar - 1 + 0x060
+set $csor4 = $mbar - 1 + 0x064
+set $csbr5 = $mbar - 1 + 0x068
+set $csor5 = $mbar - 1 + 0x06c
+set $csbr6 = $mbar - 1 + 0x070
+set $csor6 = $mbar - 1 + 0x074
+set $csbr7 = $mbar - 1 + 0x078
+set $csor7 = $mbar - 1 + 0x07c
+set $pacnt = $mbar - 1 + 0x080
+set $paddr = $mbar - 1 + 0x084
+set $padat = $mbar - 1 + 0x086
+set $pbcnt = $mbar - 1 + 0x088
+set $pbddr = $mbar - 1 + 0x08c
+set $pbdat = $mbar - 1 + 0x08e
+set $pcddr = $mbar - 1 + 0x094
+set $pcdat = $mbar - 1 + 0x096
+set $pdcnt = $mbar - 1 + 0x098
+set $sdcr  = $mbar - 1 + 0x180
+set $sdtr  = $mbar - 1 + 0x184
+set $wrrr  = $mbar - 1 + 0x280
+set $wirr  = $mbar - 1 + 0x283
+set $wcr   = $mbar - 1 + 0x288
+set $wer   = $mbar - 1 + 0x28c
+
+end
+
+
+#
+# Setup system configuration
+#
+define setup-sys
+set *((unsigned short *) $scr) = 0x0003
+set *((unsigned short *) $spr) = 0xffff
+set *((unsigned char *) $pivr) = 0x4f
+end
+
+
+#
+# Setup Chip Selects (as per Motorola M5272C3 board)
+#
+define setup-cs
+
+# CS0 -- FLASH
+set *((unsigned long *) $csbr0) = 0xffe00201
+set *((unsigned long *) $csor0) = 0xffe00014
+
+# CS1 -- external bus test
+set *((unsigned long *) $csbr1) = 0x0
+set *((unsigned long *) $csor1) = 0x0
+
+# CS2 -- Optional FSRAM
+set *((unsigned long *) $csbr2) = 0x30000001
+set *((unsigned long *) $csor2) = 0xfff80000
+
+# CS3 -- not used
+set *((unsigned long *) $csbr3) = 0x0
+set *((unsigned long *) $csor3) = 0x0
+
+# CS4 --  not used
+set *((unsigned long *) $csbr4) = 0x0
+set *((unsigned long *) $csor4) = 0x0
+
+# CS5 -- PLI socket0
+set *((unsigned long *) $csbr5) = 0x0
+set *((unsigned long *) $csor5) = 0x0
+
+# CS6 -- PLI socket1
+set *((unsigned long *) $csbr6) = 0x0
+set *((unsigned long *) $csor6) = 0x0
+
+# CS7 -- SDRAM
+set *((unsigned long *) $csbr7) = 0x00000701
+set *((unsigned long *) $csor7) = 0xff00007c
+
+end
+
+
+#
+# Setup the DRAM controller.
+#
+
+define setup-dram
+set *((unsigned long *) $sdtr) = 0x0000f539
+set *((unsigned long *) $sdcr) = 0x00004211
+
+# Dummy write to start SDRAM
+set *((unsigned long *) 0) = 0
+end
+
+
+#
+# Setup for GPIO pins
+#
+define setup-ppio
+
+# PORT A -- the LED's
+set *((unsigned long *) $pacnt) = 0x00000000
+# lower 8 bits for output:
+set *((unsigned short *) $paddr) = 0xff
+# LED's off:
+set *((unsigned short *) $padat) = 0xff
+
+# PORT B
+set *((unsigned long *) $pbcnt) = 0x55554155
+set *((unsigned short *) $pbddr) = 0x0000
+set *((unsigned short *) $pbdat) = 0x17ea
+
+# PORT C
+#set *((unsigned short *) $pcddr) = 0x0000
+#set *((unsigned short *) $pcdat) = 0x1898
+
+# PORT D
+set *((unsigned long *) $pdcnt) = 0x00000000
+
+end
+
+
+#
+#	Added for uClinux-coldfire target...
+#
+target bdm /dev/bdm
+
+addresses
+setup-sys
+setup-cs
+setup-dram
+setup-ppio
+set print pretty
+set print asm-demangle
+display/i $pc
+
+
+#
+load u-boot
+set $pc=0x20000
+c
diff --git a/board/cobra5272/bdm/gdbinit.reset b/board/cobra5272/bdm/gdbinit.reset
new file mode 100644
index 0000000000..5f1e48217c
--- /dev/null
+++ b/board/cobra5272/bdm/gdbinit.reset
@@ -0,0 +1,2 @@
+target bdm /dev/bdmcf0
+q
diff --git a/board/cobra5272/bdm/load-cobra_uboot b/board/cobra5272/bdm/load-cobra_uboot
new file mode 100644
index 0000000000..933c7e7235
--- /dev/null
+++ b/board/cobra5272/bdm/load-cobra_uboot
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot
+
diff --git a/board/cobra5272/bdm/reset b/board/cobra5272/bdm/reset
new file mode 100644
index 0000000000..8bef00bf1c
--- /dev/null
+++ b/board/cobra5272/bdm/reset
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset
+
diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c
new file mode 100644
index 0000000000..26adb4abb1
--- /dev/null
+++ b/board/cobra5272/cobra5272.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5272.h>
+#include <asm/immap_5272.h>
+
+
+int checkboard (void)
+{
+	puts ("Board: ");
+	puts ("senTec COBRA5272 Board\n");
+	return 0;
+};
+
+long int initdram (int board_type)
+{
+	volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR);
+
+	sdp->sdram_sdtr = 0xf539;
+	sdp->sdram_sdcr = 0x4211;
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *) 0) = 0;
+
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/board/cobra5272/config.mk b/board/cobra5272/config.mk
new file mode 100644
index 0000000000..ccb2cf735d
--- /dev/null
+++ b/board/cobra5272/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xffe00000
diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
new file mode 100644
index 0000000000..6f5874a671
--- /dev/null
+++ b/board/cobra5272/flash.c
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_PL160CB & FLASH_TYPEMASK):
+		printf ("AM29PL160CB (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+}
+
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_PL160CB & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j == 0) {
+				/* 1st is 16 KiB */
+				flash_info[i].start[j] = flashbase;
+			}
+			if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x4000 + 0x2000 * (j - 1);
+			}
+			if (j == 3) {
+				/* 4th is 224 KiB */
+				flash_info[i].start[j] = flashbase + 0x8000;
+			}
+			if ((j >= 4) && (j <= 10)) {
+				/* rest is 256 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x40000 + 0x40000 * (j -
+									 4);
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + 0x3ffff, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		set_timer (0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds
new file mode 100644
index 0000000000..ed20c5967e
--- /dev/null
+++ b/board/cobra5272/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+    cpu/mcf52x2/start.o		(.text)
+    cpu/mcf52x2/cpu_init.o	(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 7c762bab92..d50cede3b5 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -80,11 +80,11 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 		return FPGA_FAIL;
 	}
 
-	length = (*dataptr << 8) + *(dataptr+1); 
+	length = (*dataptr << 8) + *(dataptr+1);
 	dataptr+=2;
 	for(i=0;i<length;i++)
 		buffer[i]=*dataptr++;
-	
+
 	buffer[length-5]='\0'; /* remove filename extension */
 	PRINTF(__FUNCTION__ ": design name = \"%s\".\n",buffer);
 
@@ -93,18 +93,18 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 		printf(__FUNCTION__ ": Part number identifier not recognized in bitstream.\n");
 		return FPGA_FAIL;
 	}
-	
+
 	length = (*dataptr << 8) + *(dataptr+1); dataptr+=2;
-	for(i=0;i<length;i++) 
+	for(i=0;i<length;i++)
 		buffer[i]=*dataptr++;
 	PRINTF(__FUNCTION__ ": part number = \"%s\".\n",buffer);
-	
+
 	/* get date (identifier, length, string) */
 	if (*dataptr++ != 0x63) {
 		printf(__FUNCTION__ ": Date identifier not recognized in bitstream.\n");
 		return FPGA_FAIL;
 	}
-	
+
 	length = (*dataptr << 8) + *(dataptr+1); dataptr+=2;
 	for(i=0;i<length;i++)
 		buffer[i]=*dataptr++;
@@ -115,12 +115,12 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 		printf(__FUNCTION__ ": Time identifier not recognized in bitstream.\n");
 		return FPGA_FAIL;
 	}
-	
+
 	length = (*dataptr << 8) + *(dataptr+1); dataptr+=2;
 	for(i=0;i<length;i++)
 		buffer[i]=*dataptr++;
 	PRINTF(__FUNCTION__ ": time = \"%s\".\n",buffer);
-	
+
 	/* get fpga data length (identifier, length) */
 	if (*dataptr++ != 0x65) {
 		printf(__FUNCTION__ ": Data length identifier not recognized in bitstream.\n");
@@ -129,20 +129,20 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 	swapsize = ((long)*dataptr<<24) + ((long)*(dataptr+1)<<16) + ((long)*(dataptr+2)<<8) + (long)*(dataptr+3);
 	dataptr+=4;
 	PRINTF(__FUNCTION__ ": bytes in bitstream = %d.\n",swapsize);
-	
+
 	/* check consistency of length obtained */
 	if (swapsize >= size) {
 		printf(__FUNCTION__ ": Could not find right length of data in bitstream.\n");
 		return FPGA_FAIL;
 	}
-	
+
 	/* allocate memory */
 	swapdata = (char *)malloc(swapsize);
 	if (swapdata == NULL) {
 		printf(__FUNCTION__ ": Could not allocate %d bytes memory !\n",swapsize);
 		return FPGA_FAIL;
 	}
-	
+
 	/* read data into memory and swap bits */
 	ptr = swapdata;
 	for (i = 0; i < swapsize; i++) {
diff --git a/doc/README.COBRA5272 b/doc/README.COBRA5272
new file mode 100644
index 0000000000..2d3f7067c3
--- /dev/null
+++ b/doc/README.COBRA5272
@@ -0,0 +1,156 @@
+File:		README.COBRA5272
+Author:		Florian Schlote for Sentec elektronik (linux@sentec-elektronik.de)
+Contents:	This is the README of u-boot (Universal bootloader) for our
+		COBRA5272 board.
+Version:	v01.00
+Date:		Tue Mar 30 00:28:33 CEST 2004
+License:	This document is published under the GNU GPL
+______________________________________________________________________
+
+CHANGES
+040330   v01.00 Creation
+
+______________________________________________________________________
+
+
+CONFIGURING
+-----------
+
+1. Modify include/configs/cobra5272.h acc. to your prefs
+
+2. If necessary, modify board/cobra5272/config.mk (see below)
+
+3.
+
+> make cobra5272_config
+
+> make
+
+
+Please refer to u-boot README (general info, u-boot-x-x-x/README),
+to u-boot-x-x-x/doc/README.COBRA5272 and
+to the comments in u-boot-x-x-x/include/configs/cobra5272.h
+
+Configuring u-boot is done by commenting/uncommenting preprocessor defines.
+
+Default configuration is
+
+	FLASH version (for further info see subsection below)
+	link address 0xffe00000
+
+	16 MB RAM
+
+	network enabled
+	no default IP address for target, host set, no MACaddress set
+
+	bootdelay for autoboot 5 sec.
+	autoboot disabled
+
+
+#-----------------------------------
+# u-boot FLASH version & RAM version
+#-----------------------------------
+
+The u-boot bootloader for Coldfire processors can be configured
+
+	1. as a standalone bootloader residing in flash & relocating itself to RAM on
+	startup automatically => "FLASH version"
+
+	2. as a RAM version which will not load from flash automatically as it needs a
+	prestage bootloader ("chainloading") & is running only from the RAM address it
+	is linked to => "RAM version"
+
+	This version may be very helpful when installing u-boot for the first time
+	since it can be used to make available s. th. like a "bootstrap
+	mechanism".
+
+
+How to build the different images:
+
+------------------------------
+Flash version
+------------------------------
+
+Compile u-boot
+
+in dir ./u-boot-x-x-x/
+
+please first check:
+
+	in ./include/configs/cobra5272.h
+
+		CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows:
+
+		#if 0
+			#define CONFIG_MONITOR_IS_IN_RAM
+			/* define if monitor is started from a pre-loader */
+		#endif
+
+	=> u-boot as single bootloader starting from flash
+
+
+	in board/cobra5272/config.mk TEXT_BASE should be
+
+		TEXT_BASE = 0xffe00000
+
+	=> linking address for u-boot as single bootloader stored in flash
+
+then:
+
+	host> make cobra5272_config
+		rm -f include/config.h include/config.mk
+		Configuring for cobra5272 board...
+	host> make
+		[...]
+
+	host> cp u-boot.bin /tftpboot/u-boot_flash.bin
+
+
+------------------------------
+RAM version
+------------------------------
+
+in dir ./u-boot-x-x-x/
+
+	host> make distclean
+
+please modify the settings:
+
+	in ./include/configs/cobra5272.h
+
+		CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows:
+
+		#if 1
+			#define CONFIG_MONITOR_IS_IN_RAM
+			/*define if monitor is started from a pre-loader */
+		#endif
+
+	=> u-boot as RAM version, chainloaded by another bootloader or using bdm cable
+
+
+	in board/cobra5272/config.mk TEXT_BASE should be
+
+		TEXT_BASE = 0x00020000
+
+	=> target linking address for RAM
+
+
+then:
+
+	host> make cobra5272_config
+		rm -f include/config.h include/config.mk
+		Configuring for cobra5272 board...
+	host> make
+		[...]
+
+	host> cp u-boot.bin /tftpboot/u-boot_ram.bin
+
+
+----
+HINT
+----
+
+If the m68k-elf-toolchain & the m68k-bdm-gdb is installed you can run the RAM
+version by typing (in dir ./u-boot-x-x-x/)
+"board/cobra5272/bdm/load-cobra_uboot" ,
+in ./u-boot-x-x-x/ the RAM version u-boot (elf format) has to be available.
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
new file mode 100644
index 0000000000..9033fa88ed
--- /dev/null
+++ b/include/configs/cobra5272.h
@@ -0,0 +1,355 @@
+/*
+ * Configuation settings for the Sentec Cobra Board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ---
+ * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
+ * Date: 2004-03-29
+ * Author: Florian Schlote
+ *
+ * For a description of configuration options please refer also to the
+ * general u-boot-1.x.x/README file
+ * ---
+ */
+
+/* ---
+ * board/config.h - configuration options, board specific
+ * ---
+ */
+
+#ifndef _CONFIG_COBRA5272_H
+#define _CONFIG_COBRA5272_H
+
+/* ---
+ * Define processor
+ * possible values for Sentec board: only Coldfire M5272 processor supported
+ * (please do not change)
+ * ---
+ */
+
+#define CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5272			/* define processor type */
+
+/* ---
+ * Defines processor clock - important for correct timings concerning serial
+ * interface etc.
+ * CFG_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
+ * ---
+ */
+
+#define CFG_HZ			1000
+#define CFG_CLK			66000000
+#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
+
+/* ---
+ * Enable use of Ethernet
+ * ---
+ */
+
+#define FEC_ENET
+
+/* ---
+ * Define baudrate for UART1 (console output, tftp, ...)
+ * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
+ * CFG_BAUDRATE_TABLE defines values that can be selected in u-boot command
+ * interface
+ * ---
+ */
+
+#define CONFIG_BAUDRATE		19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+/* ---
+ * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
+ * timeout acc. to your needs
+ * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
+ * for 10 sec
+ * ---
+ */
+
+#if 0
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
+#endif
+
+/* ---
+ * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
+ * bootloader residing in flash ('chainloading'); if you want to use
+ * chainloading or want to compile a u-boot binary that can be loaded into
+ * RAM via BDM set
+ * 	"#if 0" to "#if 1"
+ * You will need a first stage bootloader then, e. g. colilo or a working BDM
+ * cable (Background Debug Mode)
+ *
+ * Setting #if 0: u-boot will start from flash and relocate itself to RAM
+ *
+ * Please do not forget to modify the setting of TEXT_BASE
+ * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
+ *
+ * ---
+ */
+
+#if 0
+#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
+#endif
+
+/* ---
+ * Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ * ---
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_IS_EMBEDDED	1
+#else
+#define CFG_ENV_ADDR		0xffe04000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+/* ---
+ * Define which commmands should be available at u-boot command prompt
+ * ---
+ */
+
+#define CONFIG_COMMANDS	 ( CONFIG_CMD_DFL | CFG_CMD_PING & ~(CFG_CMD_LOADS | \
+CFG_CMD_LOADB) | CFG_CMD_MII)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ *-----------------------------------------------------------------------------
+ * Define user parameters that have to be customized most likely
+ *-----------------------------------------------------------------------------
+ */
+
+/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
+
+#define CONFIG_BOOTDELAY	5		/* used for autoboot, delay in
+seconds u-boot will wait before starting defined (auto-)boot command, setting
+to -1 disables delay, setting to 0 will too prevent access to u-boot command
+interface: u-boot then has to reflashed */
+
+
+/* The following settings will be contained in the environment block ; if you
+want to use a neutral environment all those settings can be manually set in
+u-boot: 'set' command */
+
+#if 0
+
+#define CONFIG_BOOTCOMMAND	"bootm 0xffe80000"	/*Autoboto command, please
+enter a valid image address in flash */
+
+#define CONFIG_BOOTARGS		" "			/* default bootargs that are
+considered during boot */
+
+/* User network settings */
+
+#define CONFIG_ETHADDR 00:00:00:00:00:09	/* default ethernet MAC addr. */
+#define CONFIG_IPADDR 192.168.100.2		/* default board IP address */
+#define CONFIG_SERVERIP 192.168.100.1	/* default tftp server IP address */
+
+#endif
+
+#define CFG_PROMPT		"COBRA > "	/* Layout of u-boot prompt*/
+
+#define CFG_LOAD_ADDR		0x20000		/*Defines default RAM address
+from which user programs will be started */
+
+/*---*/
+
+#define CFG_LONGHELP				/* undef to save memory		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*
+ *-----------------------------------------------------------------------------
+ * End of user parameters to be customized
+ *-----------------------------------------------------------------------------
+ */
+
+/* ---
+ * Defines memory range for test
+ * ---
+ */
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+/* ---
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * ---
+ */
+
+/* ---
+ * Base register address
+ * ---
+ */
+
+#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+
+/* ---
+ * System Conf. Reg. & System Protection Reg.
+ * ---
+ */
+
+#define CFG_SCR			0x0003;
+#define CFG_SPR			0xffff;
+
+/* ---
+ * Ethernet settings
+ * ---
+ */
+
+#define CFG_DISCOVER_PHY
+#define CFG_ENET_BD_BASE	0x780000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
+#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+
+/*
+ *-------------------------------------------------------------------------
+ * RAM SIZE (is defined above)
+ *-----------------------------------------------------------------------
+ */
+
+/* #define CFG_SDRAM_SIZE		16 */
+
+/*
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_FLASH_BASE		0xffe00000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CFG_MONITOR_BASE	0x20000
+#else
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
+#define CFG_FLASH_ERASE_TOUT	1000	/* flash timeout */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ *
+ * Please refer also to Motorola Coldfire user manual - Chapter XXX
+ * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
+ */
+#define CFG_BR0_PRELIM		0xFFE00201
+#define CFG_OR0_PRELIM		0xFFE00014
+
+#define CFG_BR1_PRELIM		0
+#define CFG_OR1_PRELIM		0
+
+#define CFG_BR2_PRELIM		0
+#define CFG_OR2_PRELIM		0
+
+#define CFG_BR3_PRELIM		0
+#define CFG_OR3_PRELIM		0
+
+#define CFG_BR4_PRELIM		0
+#define CFG_OR4_PRELIM		0
+
+#define CFG_BR5_PRELIM		0
+#define CFG_OR5_PRELIM		0
+
+#define CFG_BR6_PRELIM		0
+#define CFG_OR6_PRELIM		0
+
+#define CFG_BR7_PRELIM		0x00000701
+#define CFG_OR7_PRELIM		0xFF00007C
+
+/*-----------------------------------------------------------------------
+ * LED config
+ */
+#define	LED_STAT_0	0xffff /*all LEDs off*/
+#define	LED_STAT_1	0xfffe
+#define	LED_STAT_2	0xfffd
+#define	LED_STAT_3	0xfffb
+#define	LED_STAT_4	0xfff7
+#define	LED_STAT_5	0xffef
+#define	LED_STAT_6	0xffdf
+#define	LED_STAT_7	0xff00 /*all LEDs on*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration (GPIO)
+ */
+#define CFG_PACNT		0x00000000		/* PortA control reg.: All pins are external
+GPIO*/
+#define CFG_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
+(1^=output, 0^=input) */
+#define CFG_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
+#define CFG_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
+configuration */
+#define CFG_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
+#define CFG_PBDAT		0x0000			/* PortB value reg. */
+#define CFG_PDCNT		0x00000000		/* PortD control reg. */
+
+#endif	/* _CONFIG_COBRA5272_H */
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index f14442df26..fb335db804 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -26,7 +26,7 @@
 
 /*
  * board/config.h - configuration options, board specific
- * 
+ *
  * "EP8260 H, V.1.1"
  * 	- 64M 60x Bus SDRAM
  * 	- 32M Local Bus SDRAM
@@ -37,7 +37,7 @@
  * 	- 300MHz/133MHz/66MHz
  * 	- 64M 60x Bus SDRAM
  * 	- 32M Local Bus SDRAM
- * 	- 32M Flash 
+ * 	- 32M Flash
  * 	- 128k NVRAM with RTC
  */
 
@@ -104,7 +104,7 @@
 #define CFG_FLASH0_SIZE 32
 #else
 #define CFG_FLASH0_BASE 0xFF000000
-#define CFG_FLASH0_SIZE 16 
+#define CFG_FLASH0_SIZE 16
 #endif
 
 /* What should the base address of the secondary FLASH be and how big
@@ -127,7 +127,7 @@
  * local bus (8260 local bus is NOT cacheable!)
 */
 /* #define CFG_LSDRAM */
-#undef CFG_LSDRAM 
+#undef CFG_LSDRAM
 
 #ifdef CFG_LSDRAM
 /* What should be the base address of SDRAM DIMM (local bus) and how big is
@@ -260,7 +260,7 @@
 #ifdef CFG_EP8260_H2
 #define CONFIG_BAUDRATE         9600
 #else
-#define CONFIG_BAUDRATE         115200 
+#define CONFIG_BAUDRATE         115200
 #endif
 
 /* Ethernet MAC address */
@@ -553,9 +553,9 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #ifdef CFG_EP8260_H2
-/* TBD: Find out why setting the BMT to 0xff causes the FCC to 
- * generate TX buffer underrun errors for large packets under 
- * Linux 
+/* TBD: Find out why setting the BMT to 0xff causes the FCC to
+ * generate TX buffer underrun errors for large packets under
+ * Linux
  */
 #define CFG_SYPCR_BMT	0x00000600
 #else