diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2015-04-20 13:22:58 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2015-05-01 22:26:15 +0200 |
| commit | dcf30dacf57c15b4ce7c49e8e08ea0d20a44cba3 (patch) | |
| tree | d40e30e726546c9071068fc4c20e7fc24be3cd1e | |
| parent | d536cdbdf8e8765a2d223b2c38c0fa2e8ff36f12 (diff) | |
serial_mxc.c: add option to use in DTE mode
The serial_mxc UART can use DTE and DCE mode (i.e End device vs. modem).
This adds DTE mode capability to the driver.
In order to switch from the default DCE to DTE mode define CONFIG_MXC_UART_DTE.
| -rw-r--r-- | drivers/serial/serial_mxc.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index d6cf1d874a..b233566c09 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -74,6 +74,7 @@ #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_DCEDTE (1<<6) /* DCE=0 */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ @@ -142,7 +143,7 @@ static void mxc_serial_setbrg(void) if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; - __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UFCR) = (__REG(UART_PHYS + UFCR) & ~UFCR_RFDIV) | (4 << 7); /* divide input clock by 2 */ __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); @@ -198,6 +199,9 @@ static int mxc_serial_init(void) __REG(UART_PHYS + UTS) = 0x0; + /* keep the DCE DTE setting */ + __REG(UART_PHYS + UFCR) = __REG(UART_PHYS + UFCR) & UFCR_DCEDTE; + serial_setbrg(); __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; |