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authorThierry Reding <treding@nvidia.com>2014-08-26 17:34:24 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2014-10-11 01:26:27 +0200
commit5000d358bee6d9015e09cc581d7707896821c20b (patch)
tree5f277cd2dd1fdc7b44742de196165f695335c5b7
parent1a8f7ecda5a3b7100950f16b7be2288fe6b5c86f (diff)
ARM: tegra: Enable non-cached memory
Some boards, most notably those with a PCIe ethernet NIC, require this to avoid cache coherency problems. Since the option adds very little code and overhead enable it across all Tegra generations. Other drivers may also start supporting this functionality at some point, so enabling it now will automatically reap the benefits later on. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Conflicts: include/configs/tegra-common.h
-rw-r--r--include/configs/tegra-common.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 834b3d5686..fcd390772f 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -44,7 +44,11 @@
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
-#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#define CONFIG_SYS_MALLOC_F_LEN (4 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
/*
* NS16550 Configuration