diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2014-10-24 16:43:09 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2014-10-28 09:41:23 +0100 |
| commit | 7d71154703be65ebb48676427780f69b72160acb (patch) | |
| tree | 514b78bdb0e74be94bfa294b3af7500059e6ef3b | |
| parent | d91796f4d92e3d015eb2ddbca88d01f97a8ea76a (diff) | |
arm: vf610: improve DDR initialization
With the new JEDEC standardized initialization parameter, the
initialization takes longer than 200us. Use the status bit to
determine whether the memory initialization was completed.
Also use recommended JEDEC defaults for t_INIT.
| -rw-r--r-- | arch/arm/imx-common/ddr-vf610.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/imx-common/ddr-vf610.c b/arch/arm/imx-common/ddr-vf610.c index 1ab5af058b..ffcc3d2dd8 100644 --- a/arch/arm/imx-common/ddr-vf610.c +++ b/arch/arm/imx-common/ddr-vf610.c @@ -105,7 +105,7 @@ void ddr_ctrl_init(int tref, int trfc, int col_diff, int row_diff) struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); - writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); + writel(DDRMC_CR02_DRAM_TINIT(5), &ddrmr->cr[2]); writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]); writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); @@ -237,6 +237,6 @@ void ddr_ctrl_init(int tref, int trfc, int col_diff, int row_diff) writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); - udelay(200); + while (!(readl(&ddrmr->cr[80]) && 0x100)) + udelay(10); } - |