diff options
| author | Sanchayan Maity <maitysanchayan@gmail.com> | 2014-11-20 20:15:07 +0530 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2014-11-25 16:34:00 +0100 |
| commit | 392ca8e478dbb11740c8c2f5331987c296f36c62 (patch) | |
| tree | 21e6a3552cb90653bf8b6c7c257fde93c628bed7 | |
| parent | 9bc01735c6529507071aa7d9876be25ad0edcab0 (diff) | |
colibri_vf: Enable USB peripherals
Enable clock and PLL's for USB
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | board/toradex/colibri_vf/colibri_vf.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 4149e0b7d3..fa027d4f75 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -158,7 +158,8 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, - CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); + CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK | + CCM_CCGR1_USBC0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | @@ -171,15 +172,21 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, - CCM_CCGR7_SDHC1_CTRL_MASK); + CCM_CCGR7_SDHC1_CTRL_MASK | CCM_CCGR7_USBC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, CCM_CCGR10_NFC_CTRL_MASK); + clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS | + ANADIG_PLL7_CTRL_POWERDOWN, ANADIG_PLL7_CTRL_ENABLE | + ANADIG_PLL7_CTRL_DIV_SELECT); clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | ANADIG_PLL5_CTRL_DIV_SELECT); + clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS | + ANADIG_PLL3_CTRL_POWERDOWN, ANADIG_PLL3_CTRL_ENABLE | + ANADIG_PLL3_CTRL_DIV_SELECT); if (is_colibri_vf61()) { clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | @@ -204,6 +211,8 @@ static void clock_init(void) } clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | + CCM_CCSR_PLL3_PFD4_EN | CCM_CCSR_PLL3_PFD3_EN | + CCM_CCSR_PLL3_PFD2_EN | CCM_CCSR_PLL3_PFD1_EN | CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | |