diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2014-04-10 18:49:09 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan@agner.ch> | 2014-04-23 18:23:27 +0200 |
| commit | 4718da3d0d5be9317e175b9fe98b1d4b1bd88883 (patch) | |
| tree | 19257fcd99cbecba03246e555768c3b34b415368 | |
| parent | 920fd05e72a521ce7f9f260b5fce1ad9f07a34f4 (diff) | |
arm: vf610: add NFC clock support
Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/crm_regs.h | 16 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/imx-regs.h | 1 |
2 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index e17c7d1f70..509559c1cd 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -150,17 +150,32 @@ struct anadig_reg { #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) +#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12 +#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) +#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12) + #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) #define CCM_CSCDR1_RMII_CLK_EN (1 << 24) +#define CCM_CSCDR2_NFC_EN (1 << 9) +#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) +#define CCM_CSCDR2_NFC_CLK_INV (1 << 14) +#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4 +#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4) +#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4) + #define CCM_CSCDR2_ESDHC1_EN (1 << 29) #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) +#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13 +#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) +#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13) + #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) @@ -186,6 +201,7 @@ struct anadig_reg { #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) +#define CCM_CCGR10_NFC_CTRL_MASK 0x3 #define ANADIG_PLL5_CTRL_BYPASS (1 << 16) #define ANADIG_PLL5_CTRL_ENABLE (1 << 13) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 0c28e1b840..8803521074 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -86,6 +86,7 @@ #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) #define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) +#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000) /* MUX mode and PAD ctrl are in one register */ #define CONFIG_IOMUX_SHARE_CONF_REG |