colibri-imx6: initial support for dual-light

14 files changed, 2097 insertions, 0 deletions

diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
new file mode 100644
index 0000000000..e0d3d10d5a
--- /dev/null
+++ b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x2c305323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+/* DDR3 DATA BUS SIZE: 64BIT */
+/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */
+/* DDR3 DATA BUS SIZE: 32BIT */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
new file mode 100644
index 0000000000..0e9c13814d
--- /dev/null
+++ b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x2c305323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+/* DDR3 DATA BUS SIZE: 64BIT */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000
+/* DDR3 DATA BUS SIZE: 32BIT */
+/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/Makefile b/board/toradex/colibri_imx6/Makefile
new file mode 100644
index 0000000000..a5d1f779c0
--- /dev/null
+++ b/board/toradex/colibri_imx6/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+# (C) Copyright 2014 Toradex AG
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := colibri_imx6.o
+obj-y  += pf0100.o
+obj-y  += do_fuse.o
diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg
new file mode 100644
index 0000000000..8bddb91d77
--- /dev/null
+++ b/board/toradex/colibri_imx6/clocks.cfg
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/colibri_imx6/colibri-imx6.cfg b/board/toradex/colibri_imx6/colibri-imx6.cfg
new file mode 100644
index 0000000000..b67d82ce71
--- /dev/null
+++ b/board/toradex/colibri_imx6/colibri-imx6.cfg
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014 Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+
+#if DDR_MB == 256
+#include "800mhz_2x64mx16.cfg"
+#else
+#include "800mhz_4x64mx16.cfg"
+#endif
+
+#include "clocks.cfg"
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
new file mode 100644
index 0000000000..923b8c8356
--- /dev/null
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -0,0 +1,788 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ * Copyright (C) 2014, Toradex AG
+ * copied from nitrogen6x
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <i2c.h>
+#include "pf0100.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_BOARD_LATE_INIT) && (defined(CONFIG_TRDX_CFG_BLOCK) || \
+		defined(CONFIG_SERIAL_TAG))
+/* buffer suitable for DMA */
+#define CONFIG_BLOCK_BUFFER_SIZE 4096
+static unsigned char config_block[roundup(CONFIG_BLOCK_BUFFER_SIZE, ARCH_DMA_MINALIGN)]
+                                  __aligned(ARCH_DMA_MINALIGN);
+#endif
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+int dram_init(void)
+{
+	/* FIXME make the RAM size dynamic */
+	gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
+
+	return 0;
+}
+
+/* Colibri UARTA */
+iomux_v3_cfg_t const uart1_pads[] = {
+#ifndef CONFIG_MXC_UART_DTE
+	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+#else
+	MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+#endif
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* Colibri I2C */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
+		.gp = IMX_GPIO_NR(1, 6)
+	}
+};
+
+/* Colibri local, PMIC, SGTL5000, STMPE811*/
+struct i2c_pads_info i2c_pad_info_loc = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+		.gp = IMX_GPIO_NR(3, 16)
+	}
+};
+
+/* Apalis MMC */
+iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+#	define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
+};
+
+/* eMMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RXD0__ENET_RX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RXD1__ENET_RX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RX_ER__ENET_RX_ER		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_TX_EN__ENET_TX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_TXD0__ENET_TX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_TXD1__ENET_TX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_CRS_DV__ENET_RX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_GPIO_16__ENET_REF_CLK		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+iomux_v3_cfg_t const usb_pads[] = {
+	/* TODO This pin has a dedicated USB power functionality, can we use it? */
+	/* USB_PE */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
+#if 0
+/* FIXME USB CLIENT */
+	/* USB_C_DET */
+	MX6_PAD_ENET_RX_ER__USB_OTG_ID	| MUX_PAD_CTRL(WEAK_PULLUP),
+#endif
+};
+
+/* if UARTs are used in DTE mode, so switch the mode on all UARTs before
+ * any pinmuxing connects a (DCE) output to a transceiver output.
+ */
+#define UFCR		0x90	/* FIFO Control Register */
+#define UFCR_DCEDTE	(1<<6)	/* DCE=0 */
+#define SET_DCEDTE(p)	(writel( (readl((u32 *) (p)) | UFCR_DCEDTE), (u32 *) (p)))
+
+#ifdef CONFIG_MXC_UART_DTE
+static void setup_dtemode_uart(void)
+{
+	SET_DCEDTE(UART1_BASE + UFCR);
+	SET_DCEDTE(UART2_BASE + UFCR);
+	SET_DCEDTE(UART3_BASE + UFCR);
+}
+#endif 
+
+static void setup_iomux_uart(void)
+{
+#ifdef CONFIG_MXC_UART_DTE
+	setup_dtemode_uart();
+#endif
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+
+	/* Set MXM USBH power enable */
+	gpio_direction_output(GPIO_USBH_EN, 0);
+	mdelay(100);
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	/* No special PE for USBC, always on when ID pin signals host mode */
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+/* use the following sequence: eMMC, MMC */
+struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = true; /* default: assume inserted */
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		gpio_direction_input(GPIO_MMC_CD);
+		ret = !gpio_get_value(GPIO_MMC_CD);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	s32 status = 0;
+	u32 index = 0;
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	usdhc_cfg[0].max_bus_width = 8;
+	usdhc_cfg[1].max_bus_width = 4;
+
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) then supported by the board (%d)\n",
+				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return status;
+		}
+
+		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+	}
+
+	return status;
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct iomuxc_base_regs *const iomuxc_regs =
+			(struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+	int ret;
+
+	//provide the phy clock from the i.mx6
+	ret = enable_fec_anatop_clock(ENET_50MHz);
+	if (ret)
+		return ret;
+	/* set gpr1[ENET_CLK_SEL] */
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return 0;
+	/* scan phy 1..7 */
+	phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
+	if (!phydev) {
+		free(bus);
+		puts("no phy found\n");
+		return 0;
+	}
+	printf("using phy at %d\n", phydev->addr);
+	ret  = fec_probe(bis, -1, base, bus, phydev);
+	if (ret) {
+		printf("FEC MXC: %s:failed\n", __func__);
+		free(phydev);
+		free(bus);
+	}
+#endif
+	return 0;
+}
+
+static iomux_v3_cfg_t const pwr_intb_pads[] = {
+	/* the bootrom sets the iomux to vselect, potentially connecting
+	 * two outputs. Set this back to GPIO */
+	MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight On */
+	MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
+/* TODO PWM not GPIO */
+	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+		MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+		MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+		MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+		MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+		MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+		MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+		MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+		MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+		MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+		MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+		MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+		MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+		MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+		MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+		MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+		MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+		MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+		MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+		MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+		MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+		MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+		MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+};
+
+struct display_info_t {
+	int	bus;
+	int	addr;
+	int	pixfmt;
+	int	(*detect)(struct display_info_t const *dev);
+	void	(*enable)(struct display_info_t const *dev);
+	struct	fb_videomode mode;
+};
+
+
+static int detect_hdmi(struct display_info_t const *dev)
+{
+	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	imx_iomux_v3_setup_multiple_pads(
+		rgb_pads,
+		ARRAY_SIZE(rgb_pads));
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+}
+
+static struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= NULL,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "vga-rgb",
+		.refresh        = 60,
+		.xres           = 640,
+		.yres           = 480,
+		.pixclock       = 39682,
+		.left_margin    = 48,
+		.right_margin   = 16,
+		.upper_margin   = 33,
+		.lower_margin   = 10,
+		.hsync_len      = 96,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= NULL,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "wvga-rgb",
+		.refresh        = 57,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 37037,
+		.left_margin    = 40,
+		.right_margin   = 60,
+		.upper_margin   = 10,
+		.lower_margin   = 10,
+		.hsync_len      = 20,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+
+int board_video_skip(void)
+{
+	int i;
+	int ret;
+	char const *panel = getenv("panel");
+	if (!panel) {
+		for (i = 0; i < ARRAY_SIZE(displays); i++) {
+			struct display_info_t const *dev = displays+i;
+			if (dev->detect) {
+				if (dev->detect(dev)) {
+					panel = dev->mode.name;
+					printf("auto-detected panel %s\n", panel);
+					break;
+				}
+			}
+			else {
+				/* assume connected */
+				panel = dev->mode.name;
+				printf("auto-detected panel %s\n", panel);
+				break;
+			}
+		}
+		if (!panel) {
+			panel = displays[0].mode.name;
+			printf("No panel detected: default to %s\n", panel);
+			i = 0;
+		}
+	} else {
+		for (i = 0; i < ARRAY_SIZE(displays); i++) {
+			if (!strcmp(panel, displays[i].mode.name))
+				break;
+		}
+	}
+	if (i < ARRAY_SIZE(displays)) {
+		ret = ipuv3_fb_init(&displays[i].mode, 0,
+				    displays[i].pixfmt);
+		if (!ret) {
+			displays[i].enable(displays+i);
+			printf("Display: %s (%ux%u)\n",
+			       displays[i].mode.name,
+			       displays[i].mode.xres,
+			       displays[i].mode.yres);
+		} else {
+			printf("LCD %s cannot be configured: %d\n",
+			       displays[i].mode.name, ret);
+		}
+	} else {
+		printf("unsupported panel %s\n", panel);
+		ret = -EINVAL;
+	}
+	return (0 != ret);
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+/* FIXME disable whatever LVDS stuff is initialized here */
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+			|IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* backlights unconditionally on for now */
+	imx_iomux_v3_setup_multiple_pads(backlight_pads,
+					 ARRAY_SIZE(backlight_pads));
+	/* use 0 for EDT 7", use 1 for LG fullHD panel */
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+#endif /* defined(CONFIG_VIDEO_IPUV3) */
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
+					ARRAY_SIZE(pwr_intb_pads));
+	setup_iomux_uart();
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
+
+	(void) pmic_init();
+
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_TRDX_CFG_BLOCK
+	char env_str[256];
+
+	int i;
+	unsigned size = 0;
+
+	char *addr_str, *end;
+	unsigned char bi_enetaddr[6]	= {0, 0, 0, 0, 0, 0};	/* Ethernet
+								   address */
+	unsigned char *mac_addr;
+	unsigned char mac_addr00[6]	= {0, 0, 0, 0, 0, 0};
+
+	struct mmc *mmc;
+
+	unsigned char toradex_oui[3]	= { 0x00, 0x14, 0x2d };
+	int valid			= 0;
+
+	int ret;
+	/* Read production parameter config block from eMMC */
+	mmc = find_mmc_device(0);
+	/* Just reading one 512 byte block */
+	ret = mmc->block_dev.block_read(0, (CONFIG_TRDX_CFG_BLOCK_OFFSET / 512), 1,
+					(unsigned char *)config_block);
+	if (ret == 1) {
+		ret = 0;
+		size = 512;
+	}
+
+	/* Check validity */
+	if ((ret == 0) && (size > 0)) {
+		mac_addr = config_block + 8;
+		if (!(memcmp(mac_addr, toradex_oui, 3)))
+			valid = 1;
+	}
+
+	if (!valid) {
+		printf("Missing Colibri config block\n");
+		memset((void *)config_block, 0, size);
+	} else {
+		/* Get MAC address from environment */
+		addr_str = getenv("ethaddr");
+		if (addr_str != NULL) {
+			for (i = 0; i < 6; i++) {
+				bi_enetaddr[i] = addr_str ? simple_strtoul(
+						addr_str, &end, 16) : 0;
+				if (addr_str)
+					addr_str = (*end) ? end + 1 : end;
+			}
+		}
+
+		/* Set Ethernet MAC address from config block if not already set
+		 */
+		if (memcmp(mac_addr00, bi_enetaddr, 6) == 0) {
+			sprintf(env_str, "%02x:%02x:%02x:%02x:%02x:%02x",
+				mac_addr[0], mac_addr[1], mac_addr[2],
+				mac_addr[3], mac_addr[4], mac_addr[5]);
+			setenv("ethaddr", env_str);
+#ifndef CONFIG_ENV_IS_NOWHERE
+			saveenv();
+#endif
+		}
+	}
+#endif /* CONFIG_TRDX_CFG_BLOCK */
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+/* i.MX6 uses the 'standard' board revision for things, i.e.
+   video decoding no longer works.
+   so don't interfere with the Apalis iMX6 HW Revision */
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+#ifdef CONFIG_BOARD_LATE_INIT
+	int i;
+	unsigned short major = 0, minor = 0, release = 0;
+	size_t size = 4096;
+
+	if (config_block == NULL)
+		return 0;
+
+	/* Parse revision information in config block */
+	for (i = 0; i < (size - 8); i++) {
+		if (config_block[i] == 0x02 && config_block[i+1] == 0x40 &&
+				config_block[i+2] == 0x08) {
+			break;
+		}
+	}
+
+	major = (config_block[i+3] << 8) | config_block[i+4];
+	minor = (config_block[i+5] << 8) | config_block[i+6];
+	release = (config_block[i+7] << 8) | config_block[i+8];
+
+	/* Check validity */
+	if (major)
+		return ((major & 0xff) << 8) | ((minor & 0xf) << 4) |
+		       ((release & 0xf) + 0xa);
+	else
+		return 0;
+#else
+	return 0;
+#endif /* CONFIG_BOARD_LATE_INIT */
+}
+#endif /* CONFIG_REVISION_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+#ifdef CONFIG_BOARD_LATE_INIT
+	int array[8];
+	int i;
+	unsigned int serial		= 0;
+	unsigned int serial_offset	= 11;
+
+	if (config_block == NULL) {
+		serialnr->low = 0;
+		serialnr->high = 0;
+		return;
+	}
+
+	/* Get MAC address from config block */
+	memcpy(&serial, config_block + serial_offset, 3);
+	serial = ntohl(serial);
+	serial >>= 8;
+
+	/* Check validity */
+	if (serial) {
+		/* Convert to Linux serial number format (hexadecimal coded
+		   decimal) */
+		i = 7;
+		while (serial) {
+			array[i--] = serial % 10;
+			serial /= 10;
+		}
+		while (i >= 0)
+			array[i--] = 0;
+		serial = array[0];
+		for (i = 1; i < 8; i++) {
+			serial *= 16;
+			serial += array[i];
+		}
+	}
+
+	serialnr->low = serial;
+#else
+	serialnr->low = 0;
+#endif /* CONFIG_BOARD_LATE_INIT */
+	serialnr->high = 0;
+}
+#endif /* CONFIG_SERIAL_TAG */
+
+int checkboard(void)
+{
+	puts("Board: Toradex Colibri iMX6\n");
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"mmc1",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg
new file mode 100644
index 0000000000..78e68f37c5
--- /dev/null
+++ b/board/toradex/colibri_imx6/ddr-setup.cfg
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 32 bits	x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+/* TODO: check what the RALAT field does */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+/*
+ * MDSCR	con_req
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c
new file mode 100644
index 0000000000..de4cc393d2
--- /dev/null
+++ b/board/toradex/colibri_imx6/do_fuse.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2014, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for i.MX OTP fusing during module production
+*/
+
+#include <common.h>
+#include <fuse.h>
+
+static unsigned mfgr_fuse(void);
+unsigned mfgr_fuse(void)
+{
+	unsigned val, val6;
+
+	fuse_sense(0, 5, &val);
+	printf("Fuse 0, 5: %8x\n", val);
+	fuse_sense(0, 6, &val6);
+	printf("Fuse 0, 6: %8x\n", val6);
+	fuse_sense(4, 3, &val);
+	printf("Fuse 4, 3: %8x\n", val);
+	fuse_sense(4, 2, &val);
+	printf("Fuse 4, 2: %8x\n", val);
+	if(val6 & 0x10)
+	{
+		puts("BT_FUSE_SEL already fused, will do nothing\n");
+		return 1;
+	}
+	puts("BT_FUSE_SEL FIXME rethink the correct value first, will do nothing\n");
+	return 1;
+	/* boot cfg */
+	fuse_prog(0, 5, 0x00005062);
+	/* BT_FUSE_SEL */
+	fuse_prog(0, 6, 0x00000010);
+	return 0;
+}
+
+int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	puts("Fusing...\n");
+	if(!mfgr_fuse())
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return 0;
+}
+
+U_BOOT_CMD(
+	mfgr_fuse, 1, 0, do_mfgr_fuse,
+	"OTP fusing during module production\n",
+	""
+);
diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c
new file mode 100644
index 0000000000..beab598cfd
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2014, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+
+#include "pf0100_otp.inc"
+#include "pf0100.h"
+
+/* define for PMIC register dump */
+/*#define DEBUG */
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR 		(0x08)
+
+static iomux_v3_cfg_t const pmic_prog_pads[] = {
+	MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
+};
+
+unsigned pmic_init(void)
+{
+	unsigned programmed = 0;
+	uchar bus = 1;
+	uchar devid, revid, val;
+
+	puts("PMIC: ");
+	if(!(0 == i2c_set_bus_num(bus) && (0 == i2c_probe(PFUZE100_I2C_ADDR))))
+	{
+		puts("i2c bus failed\n");
+		return 0;
+	}
+	/* get device ident */
+	if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0)
+	{
+		puts("i2c pmic devid read failed\n");
+		return 0;
+	}
+	if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0)
+	{
+		puts("i2c pmic revid read failed\n");
+		return 0;
+	}
+	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+
+#ifdef DEBUG
+	{
+		unsigned i,j;
+
+		for(i=0; i<16; i++)
+			printf("\t%x",i);
+		for(j=0; j<0x80; )
+		{
+			printf("\n%2x",j);
+			for(i=0; i<16; i++)
+			{
+				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 1");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE1;
+		if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1))
+		{
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for(j=0x80; j<0x100; )
+		{
+			printf("\n%2x",j);
+			for(i=0; i<16; i++)
+			{
+				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 2");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE2;
+		if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1))
+		{
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for(j=0x80; j<0x100; )
+		{
+			printf("\n%2x",j);
+			for(i=0; i<16; i++)
+			{
+				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\n");
+	}
+#endif
+	/* get device programmed state */
+	val = PFUZE100_PAGE_REGISTER_PAGE1;
+	if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1))
+	{
+		puts("i2c write failed\n");
+		return 0;
+	}
+	if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0)
+	{
+		puts("i2c fuse_por read failed\n");
+		return 0;
+	}
+	if(val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0)
+	{
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if(val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0)
+	{
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if(val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	switch (programmed) {
+	case 0:
+		printf("PMIC: not programmed\n");
+		break;
+	case 3:
+		printf("PMIC: programmed\n");
+		break;
+	default:
+		printf("PMIC: undefined programming state\n");
+		break;
+	}
+
+	return programmed;
+}
+
+int pf0100_prog(void)
+{
+	unsigned char bus = 1;
+	unsigned char val;
+	unsigned i;
+
+	if(pmic_init() == 3) {
+		puts("PMIC already programmed, exiting\n");
+		return 1;
+	}
+	/* set up gpio to manipulate vprog, initially off */
+	imx_iomux_v3_setup_multiple_pads(pmic_prog_pads, ARRAY_SIZE(pmic_prog_pads));
+	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
+
+	if(!(0 == i2c_set_bus_num(bus) && (0 == i2c_probe(PFUZE100_I2C_ADDR))))
+	{
+		puts("i2c bus failed\n");
+		return 1;
+	}
+
+	for (i=0; i<ARRAY_SIZE(pmic_otp_prog); i++) {
+		switch(pmic_otp_prog[i].cmd) {
+		case pmic_i2c:
+			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
+			if( i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
+					1, &val, 1))
+			{
+				printf("i2c write failed, reg 0x%2x, value0x%2x\n",
+						pmic_otp_prog[i].reg, val);
+				return 1;
+			}
+			break;
+		case pmic_delay:
+			udelay(pmic_otp_prog[i].value * 1000);
+			break;
+		case pmic_vpgm:
+			gpio_direction_output(IMX_GPIO_NR(2, 4) , pmic_otp_prog[i].value);
+			break;
+		case pmic_pwr:
+			/* TODO */
+			break;
+		}
+	}
+	return 0;
+}
+
+
+int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	puts("Programming PMIC OTP...");
+	if(!pf0100_prog())
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return 0;
+}
+
+U_BOOT_CMD(
+	pf0100_otp_prog, 1, 0, do_pf0100_prog,
+	"Program the OTP fuses on the PMIC PF0100",
+	""
+);
diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h
new file mode 100644
index 0000000000..b43744c47e
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2014, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#ifndef PF0100_H_
+#define PF0100_H_
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR 		(0x08)
+/* Register Addresses */
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_SW1AMODE		(0x23)
+#define PFUZE100_SW1ACON		36
+#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1AVOL		32
+#define PFUZE100_SW1AVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_SW1CVOL		46
+#define PFUZE100_SW1CVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_VGEN1CTL		(0x6c)
+#define PFUZE100_VGEN1_VAL		(0x30 + 0x08) /* Always ON, 1.2V */
+#define PFUZE100_SWBSTCTL		(0x66)
+#define PFUZE100_SWBST_VAL		(0x40 + 0x08 + 0x00) /* Always ON, Auto Switching Mode, 5.0V */
+
+/* chooses the extended page (registers 0x80..0xff) */
+#define PFUZE100_PAGE_REGISTER		0x7f
+#define PFUZE100_PAGE_REGISTER_PAGE_M	(0x1f << 0)
+#define PFUZE100_PAGE_REGISTER_PAGE1	(0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
+#define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
+
+/* extended page 1 */
+#define PFUZE100_FUSE_POR1		0xe4
+#define PFUZE100_FUSE_POR2		0xe5
+#define PFUZE100_FUSE_POR3		0xe6
+#define PFUZE100_FUSE_POR_M		(0x1 << 1)
+
+
+/* output some informational messages, return the number FUSE_POR=1 */
+/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
+unsigned pmic_init(void);
+
+/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
+int pf0100_prog(void);
+
+#endif /* PF0100_H_ */
diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc
new file mode 100644
index 0000000000..e321d4ebe6
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100_otp.inc
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2014, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+// Register Output for PF0100 programmer
+// Customer: Toradex AG
+// Program: Colibri iMX6
+// Sample marking: 
+// Date: 06.08.2014
+// Time: 14:01:01
+// Generated from Spreadsheet Revision: P1.8
+
+/* sed commands to get from programmer script to struct */
+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc
+   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
+
+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
+struct pmic_otp_prog_t{
+	unsigned char cmd;
+	unsigned char reg;
+	unsigned short value;
+};
+
+struct pmic_otp_prog_t pmic_otp_prog[] = {
+{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
+{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
+{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
+{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
+{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
+{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
+{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
+{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
+{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
+{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
+{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
+{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
+{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
+{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
+{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
+{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
+{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
+{pmic_i2c, 0xBD, 0x08}, // Auto gen from Row123
+{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
+{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
+{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
+{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
+{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
+{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
+{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
+{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
+{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
+{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
+{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
+{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158
+
+#if 0 /* TBB mode */
+{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
+{pmic_delay, 0, 10},
+#else
+// Write OTP
+{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
+{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
+{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
+{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
+{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
+{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
+{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
+{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
+//VPGM:DOWN:n
+//VPGM:UP:n
+{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
+//-----------------------------------------------------------------------------------
+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
+//-----------------------------------------------------------------------------------
+// BANK 1
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 2
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 3
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 4
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 5
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 6
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 7
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 8
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 9
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 10
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
+{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
+{pmic_i2c, 0xD0, 0x00}, // Clear
+{pmic_i2c, 0xD1, 0x00}, // Clear
+{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
+{pmic_delay, 0, 500},
+{pmic_pwr, 0, 1},
+#endif
+};
\ No newline at end of file
diff --git a/board/toradex/colibri_imx6/pf0100_otp_Colibri_iMX6.txt b/board/toradex/colibri_imx6/pf0100_otp_Colibri_iMX6.txt
new file mode 100644
index 0000000000..e6813123f0
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100_otp_Colibri_iMX6.txt
@@ -0,0 +1,189 @@
+/*

+ * Copyright (C) 2014, Toradex AG

+ *

+ * SPDX-License-Identifier:	GPL-2.0+

+ */

+

+// Register Output for PF0100 programmer

+// Customer: Toradex AG

+// Program: Colibri iMX6

+// Sample marking: 

+// Date: 06.08.2014

+// Time: 14:01:01

+// Generated from Spreadsheet Revision: P1.8

+

+/* sed commands to get from programmer script to struct */

+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc

+   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc

+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */

+

+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };

+struct pmic_otp_prog_t{

+	unsigned char cmd;

+	unsigned char reg;

+	unsigned short value;

+};

+

+struct pmic_otp_prog_t pmic_otp_prog[] = {

+WRITE_I2C:7F:01 // Access FSL EXT Page 1

+WRITE_I2C:A0:2B // Auto gen from Row94

+WRITE_I2C:A1:01 // Auto gen from Row95

+WRITE_I2C:A2:05 // Auto gen from Row96

+WRITE_I2C:A8:2B // Auto gen from Row102

+WRITE_I2C:A9:02 // Auto gen from Row103

+WRITE_I2C:AA:01 // Auto gen from Row104

+WRITE_I2C:AC:18 // Auto gen from Row106

+WRITE_I2C:AE:01 // Auto gen from Row108

+WRITE_I2C:B0:2C // Auto gen from Row110

+WRITE_I2C:B1:04 // Auto gen from Row111

+WRITE_I2C:B2:01 // Auto gen from Row112

+WRITE_I2C:B4:2C // Auto gen from Row114

+WRITE_I2C:B5:04 // Auto gen from Row115

+WRITE_I2C:B6:01 // Auto gen from Row116

+WRITE_I2C:B8:18 // Auto gen from Row118

+WRITE_I2C:BA:01 // Auto gen from Row120

+WRITE_I2C:BD:08 // Auto gen from Row123

+WRITE_I2C:C0:06 // Auto gen from Row126

+WRITE_I2C:C4:04 // Auto gen from Row130

+WRITE_I2C:C8:0E // Auto gen from Row134

+WRITE_I2C:CC:0E // Auto gen from Row138

+WRITE_I2C:CD:05 // Auto gen from Row139

+WRITE_I2C:D0:0C // Auto gen from Row142

+WRITE_I2C:D5:07 // Auto gen from Row147

+WRITE_I2C:D8:07 // Auto gen from Row150

+WRITE_I2C:D9:06 // Auto gen from Row151

+WRITE_I2C:DC:0A // Auto gen from Row154

+WRITE_I2C:DD:03 // Auto gen from Row155

+WRITE_I2C:E0:05 // Auto gen from Row158
+

+#if 1 /* TBB mode */

+WRITE_I2C:E4:80 // TBB_POR = 1

+DELAY:10

+#else

+// Write OTP

+WRITE_I2C:E4:02 // FUSE POR1=1

+WRITE_I2C:E5:02 // FUSE POR2=1

+WRITE_I2C:E6:02 // FUSE POR3=1

+WRITE_I2C:F0:1F // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register

+WRITE_I2C:F1:1F // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register

+WRITE_I2C:7F:02 // Access PF0100 EXT Page2

+WRITE_I2C:D0:1F // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register

+WRITE_I2C:D1:1F // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+VPGM:ON // Turn ON 8V SWBST

+//VPGM:DOWN:n

+//VPGM:UP:n

+DELAY:500 // Adds 500msec delay to allow VPGM time to ramp up

+//-----------------------------------------------------------------------------------

+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)

+//-----------------------------------------------------------------------------------

+// BANK 1

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F1:03 // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F1:0B // Set Bank 1 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F1:03 // Reset Bank 1 ANTIFUSE_EN

+WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 2

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F2:03 // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F2:0B // Set Bank 2 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F2:03 // Reset Bank 2 ANTIFUSE_EN

+WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 3

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F3:03 // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F3:0B // Set Bank 3 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F3:03 // Reset Bank 3 ANTIFUSE_EN

+WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 4

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F4:03 // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F4:0B // Set Bank 4 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F4:03 // Reset Bank 4 ANTIFUSE_EN

+WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 5

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F5:03 // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F5:0B // Set Bank 5 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F5:03 // Reset Bank 5 ANTIFUSE_EN

+WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 6

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F6:03 // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F6:0B // Set Bank 6 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F6:03 // Reset Bank 6 ANTIFUSE_EN

+WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 7

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F7:03 // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F7:0B // Set Bank 7 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F7:03 // Reset Bank 7 ANTIFUSE_EN

+WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 8

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F8:03 // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F8:0B // Set Bank 8 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F8:03 // Reset Bank 8 ANTIFUSE_EN

+WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 9

+//-----------------------------------------------------------------------------------

+WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F9:03 // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:F9:0B // Set Bank 9 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:F9:03 // Reset Bank 9 ANTIFUSE_EN

+WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+// BANK 10

+//-----------------------------------------------------------------------------------

+WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:FA:03 // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+WRITE_I2C:FA:0B // Set Bank 10 ANTIFUSE_EN

+DELAY:10 // Allow time for bank programming to complete

+WRITE_I2C:FA:03 // Reset Bank 10 ANTIFUSE_EN

+WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

+//-----------------------------------------------------------------------------------

+VPGM:OFF // Turn off 8V SWBST

+DELAY:500 // Adds delay to allow VPGM to bleed off

+WRITE_I2C:D0:00 // Clear

+WRITE_I2C:D1:00 // Clear

+PWRON:LOW // PWRON LOW to reload new OTP data

+DELAY:500

+PWRON: HIGH

+#endif

+};
\ No newline at end of file
diff --git a/boards.cfg b/boards.cfg
index 37eefd9f3a..1af4664920 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -329,6 +329,8 @@ Active  arm         armv7          mx6         gateworks       gw_ventana
 Active  arm         armv7          mx6         gateworks       gw_ventana          gwventanaq1gspi                      gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH                                        Tim Harvey <tharvey@gateworks.com>
 Active  arm         armv7          mx6         solidrun        hummingboard        hummingboard_solo                    hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512                                                      Jon Nettleton <jon.nettleton@gmail.com>
 Active  arm         armv7          mx6         toradex         apalis_imx6         apalis_imx6q1g                       apalis-imx6:IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024                                                Max Krummenacher <max.krummenacher@toradex.com>
+Active  arm         armv7          mx6         toradex         colibri_imx6        colibri_imx6dl512m                   colibri-imx6:IMX_CONFIG=board/toradex/colibri_imx6/colibri-imx6.cfg,MX6DL,DDR_MB=512                                              Max Krummenacher <max.krummenacher@toradex.com>
+Active  arm         armv7          mx6         toradex         colibri_imx6        colibri_imx6s256m                    colibri-imx6:IMX_CONFIG=board/toradex/colibri_imx6/colibri-imx6.cfg,MX6DL,DDR_MB=256                                              Max Krummenacher <max.krummenacher@toradex.com>
 Active  arm         armv7          omap3       -               overo               omap3_overo                          -                                                                                                                                 Steve Sakoman <sakoman@gmail.com>
 Active  arm         armv7          omap3       -               pandora             omap3_pandora                        -                                                                                                                                 Grazvydas Ignotas <notasas@gmail.com>
 Active  arm         armv7          omap3       8dtech          eco5pk              eco5pk                               -                                                                                                                                 Raphael Assenat <raph@8d.com>
diff --git a/include/configs/colibri-imx6.h b/include/configs/colibri-imx6.h
new file mode 100644
index 0000000000..0826b2d341
--- /dev/null
+++ b/include/configs/colibri-imx6.h
@@ -0,0 +1,305 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014, Toradex AG
+ *
+ * Configuration settings for the Toradex Apalis iMX6
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_MX6
+#define CONFIG_COLIBRI_IMX6 /* Toradex Colibri iMX6 module */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+//#define CONFIG_MACH_TYPE	4886
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_MXC_UART_DTE 		/* use the uart in DTE mode */
+
+/* Make the HW version stuff available in u-boot env */
+#define CONFIG_VERSION_VARIABLE		/* ver environment variable */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* OCOTP Configs */
+#define CONFIG_CMD_IMXOTP
+#ifdef CONFIG_CMD_IMXOTP
+#define CONFIG_IMX_OTP
+#define IMX_OTP_BASE			OCOTP_BASE_ADDR
+#define IMX_OTP_ADDR_MAX		0x7F
+#define IMX_OTP_DATA_ERROR_VAL		0xBADABADA
+#define IMX_OTPWRITE_ENABLED
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+#define CONFIG_USB_KEYBOARD
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#endif /* CONFIG_USB_KEYBOARD */
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_NETMASK		255.255.255.0
+#undef CONFIG_IPADDR
+#define CONFIG_IPADDR		192.168.10.2
+#undef CONFIG_SERVERIP
+#define CONFIG_SERVERIP		192.168.10.1
+
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_DRIVE_MMC "mmc "
+#else
+#define CONFIG_DRIVE_MMC
+#endif
+
+#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC
+
+#define EMMC_BOOTCMD \
+	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
+		"rootwait\0" \
+	"emmcboot=run setup; " \
+		"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
+		"${vidargs}; echo Booting from internal eMMC chip...; "	\
+		"run emmcdtbload; fatload mmc 0:1 ${kernel_addr_r} " \
+		"${boot_file} && bootm ${kernel_addr_r} ${dtbparam}\0" \
+	"emmcdtbload=setenv dtbparam; fatload mmc 0:1 ${fdt_addr_r} " \
+		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"fdt_addr_r=0x12000000\0" \
+	"kernel_addr_r=0x10800000\0" \
+	"ramdisk_addr_r=0x10900000\0"
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0:on root=/dev/nfs rw netdevwait\0" \
+	"nfsboot=run setup; " \
+		"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
+		"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
+		"run nfsdtbload; dhcp ${kernel_addr_r} " \
+		"&& bootm ${kernel_addr_r} ${dtbparam}\0" \
+	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
+		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define SD_BOOTCMD						\
+	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
+		"rootwait\0" \
+	"sdboot=" "run setup; " \
+		"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
+		"${vidargs}; echo Booting from SD card in 8bit slot...; " \
+		"run sddtbload; fatload mmc 1:1 ${kernel_addr_r} " \
+		"${boot_file} && bootm ${kernel_addr_r} ${dtbparam}\0" \
+	"sddtbload=setenv dtbparam; fatload mmc 1:1 ${fdt_addr_r} " \
+		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
+		"run nfsboot ; echo ; echo nfsboot failed ; " \
+		"usb start ;" \
+		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
+	"boot_file=uImage\0" \
+	"console=ttymxc0\0" \
+	"defargs=enable_wait_mode=off vmalloc=400M\0" \
+	EMMC_BOOTCMD \
+	"fdt_file=imx6dl-colibri-eval-v3.dtb\0" \
+	MEM_LAYOUT_ENV_SETTINGS \
+	NFS_BOOTCMD \
+	SD_BOOTCMD \
+	"setup=setenv setupargs fec_mac=${ethaddr} " \
+		"consoleblank=0  no_console_suspend=1 console=tty1 " \
+		"console=ttymxc0,${baudrate}n8\0 " \
+	"setupdate=setenv drive 1; fatload mmc ${drive}:1 ${kernel_addr_r} " \
+		"flash_mmc.img && source ${kernel_addr_r}\0" \
+	"vidargs=mxc_hdmi.only_cea=1 " \
+		"video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \
+		"video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
+		"fbmem=32M\0 " \
+	"vidargs_edt=video=mxcfb0:dev=lcd,EDT-WVGA,if=RGB24 " \
+		"video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
+		"fbmem=32M\0 " \
+	"vidargs_hdmi_cea_only=mxc_hdmi.only_cea=1 " \
+		"video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \
+		"video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
+		"fbmem=32M\0 " \
+	"vidargs_hdmi_lvds=mxc_hdmi.only_cea=1 " \
+		"video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \
+		"video=mxcfb1:dev=ldb,LDB-LG_LP156WF1,if=RGB666 ldb=spl1 " \
+		"video=mxcfb2:off video=mxcfb3:off " \
+		"fbmem=32M\0 " \
+	"vidargs_lvds=video=mxcfb0:dev=ldb,800x600M@60,if=RGB666 ldb=sin0 " \
+		"video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
+		"fbmem=32M\0 " \
+	"vidargs_vdac=video=mxcfb0:dev=vdac,1280x720M@60,if=RGB565 " \
+		"video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"Colibri iMX6 # "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(512 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* Toradex Configblock */
+#define CONFIG_TRDX_CFG_BLOCK
+#define CONFIG_TRDX_CFG_BLOCK_OFFSET	(640 * 1024)
+
+#define CONFIG_OF_LIBFDT
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_CMD_BMP
+
+#define CONFIG_CMD_TIME
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_CMD_FS_GENERIC
+
+#endif	/* __CONFIG_H */