diff options
author | Stefan Agner <stefan@agner.ch> | 2014-04-24 15:58:03 +0200 |
---|---|---|
committer | Stefan Agner <stefan@agner.ch> | 2014-04-24 16:32:57 +0200 |
commit | 1d75facc0daa8b2cc91363cf862b7bf10aeb321d (patch) | |
tree | 28d8cfc522f9bd61e0a5d6c17b3a80ff34295da1 | |
parent | 795d73eed0f604919fcd51bbd518f4bead25f31d (diff) |
colibri_vf: add detection for Colibri VF50
Detect Colibri VF50 modules by read L2 cache configuration of the
running CPU. Colibri VF50 modules come without L2 cache. Configure
CPU clock accordingly.
-rw-r--r-- | arch/arm/include/asm/arch-vf610/imx-regs.h | 14 | ||||
-rw-r--r-- | arch/arm/include/asm/mach-types.h | 26 | ||||
-rw-r--r-- | board/toradex/colibri_vf/colibri_vf.c | 39 | ||||
-rw-r--r-- | include/configs/colibri_vf.h | 2 |
4 files changed, 71 insertions, 10 deletions
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index b35991de90..42943f3732 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -98,6 +98,8 @@ #define MSCM_IRSPRC_CP0_EN 1 #define MSCM_IRSPRC_NUM 112 +#define MSCM_CP0CFG1 (MSCM_BASE_ADDR + 0x000000014) + /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x00002613 #define DDRMC_PHY_DQS_TIMING 0x00002615 @@ -406,6 +408,18 @@ struct mscm_ir { u16 rsvd3[848]; }; +/* MSCM */ +struct mscm { + u32 cpxtype; + u32 cpxnum; + u32 cpxmaster; + u32 cpxcount; + u32 cpxcfg0; + u32 cpxcfg1; + u32 cpxcfg2; + u32 cpxcfg3; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 440b041a16..266b37cea2 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1106,6 +1106,8 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP5_SEVM 3777 #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 +#define MACH_TYPE_COLIBRI_VF50 4749 +#define MACH_TYPE_COLIBRI_VF61 4750 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14235,6 +14237,30 @@ extern unsigned int __machine_arch_type; # define machine_is_kzm9g() (0) #endif +#ifdef CONFIG_MACH_COLIBRI_VF50 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLIBRI_VF50 +# endif +# define machine_is_colibri_vf50() (machine_arch_type == MACH_TYPE_COLIBRI_VF50) +#else +# define machine_is_colibri_vf50() (0) +#endif + +#ifdef CONFIG_MACH_COLIBRI_VF61 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLIBRI_VF61 +# endif +# define machine_is_colibri_vf61() (machine_arch_type == MACH_TYPE_COLIBRI_VF61) +#else +# define machine_is_colibri_vf61() (0) +#endif + /* * These have not yet been registered */ diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 0aaf299c75..7f5fad6ae8 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -340,10 +340,22 @@ int board_mmc_init(bd_t *bis) } #endif +static inline int is_colibri_vf61(void) +{ + struct mscm *mscm = (struct mscm*)MSCM_BASE_ADDR; + + /* + * Detect board type by Level 2 Cache: VF50 don't have any + * Level 2 Cache. + */ + return !!mscm->cpxcfg1; +} + static void clock_init(void) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; + u32 pfd_clk_sel; clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART0_CTRL_MASK); @@ -379,13 +391,16 @@ static void clock_init(void) CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); /* See "Typical PLL Configuration" */ - clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, - CCM_CCSR_PLL1_PFD_CLK_SEL(1) | CCM_CCSR_PLL2_PFD4_EN | - CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | - CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | - CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | - CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | - CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); + pfd_clk_sel = is_colibri_vf61() ? CCM_CCSR_PLL1_PFD_CLK_SEL(1) : + CCM_CCSR_PLL1_PFD_CLK_SEL(3); + clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | + CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | + CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | + CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | + CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | + CCM_CCSR_DDRC_CLK_SEL(1) | CCM_CCSR_FAST_CLK_SEL(1) | + CCM_CCSR_SYS_CLK_SEL(4)); + clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_ARM_CLK_DIV(0)); @@ -558,12 +573,20 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + if (is_colibri_vf61()) + gd->bd->bi_arch_number = MACH_TYPE_COLIBRI_VF61; + else + gd->bd->bi_arch_number = MACH_TYPE_COLIBRI_VF50; + return 0; } int checkboard(void) { - puts("Board: Colibri VF61\n"); + if (is_colibri_vf61()) + puts("Board: Colibri VF61\n"); + else + puts("Board: Colibri VF50\n"); return 0; } diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 09e841e2e3..1763067ce0 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -21,8 +21,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_MACH_TYPE 4749 - #define CONFIG_SKIP_LOWLEVEL_INIT /* Enable passing of ATAGs */ |