am33xx: Add am33xx_spl_board_init function, call, scale core frequency

We need to allow for a further call-out in spl_board_init.  For now,
call this am33xx_spl_board_init.  This function will depending on board
see if we know how to scale the core frequency up to 720MHz.

Signed-off-by: Tom Rini <trini@ti.com>

4 files changed, 77 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 2b584e0a53..2a639a1429 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -55,6 +55,9 @@ void spl_board_init(void)
 #ifdef CONFIG_SPL_NAND_SUPPORT
 	gpmc_init();
 #endif
+#ifdef CONFIG_AM33XX
+	am33xx_spl_board_init();
+#endif
 }
 
 int board_mmc_init(bd_t *bis)
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 417f84c55f..b7b81549be 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -21,7 +21,8 @@
 
 #define OSC	(V_OSCK/1000000)
 
-/* MAIN PLL Fdll = 550 MHZ, */
+/* MAIN PLL Fdll = 550MHz or 720MHz */
+#define MPUPLL_M_720	720
 #define MPUPLL_M_550	550
 #define MPUPLL_N	(OSC-1)
 #define MPUPLL_M2	1
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 510d07ee10..b60cd4bdd6 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -36,4 +36,5 @@ void mpu_pll_config(int mpupll_M);
 void sdelay(unsigned long);
 void gpmc_init(void);
 void omap_nand_switch_ecc(int);
+void am33xx_spl_board_init(void);
 #endif
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 6e30ac0265..d5c2d20424 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -348,6 +348,77 @@ static struct emif_regs ddr3_emif_reg_data = {
 	.zq_config = MT41J128MJT125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
 };
+
+void am33xx_spl_board_init(void)
+{
+	if (!strncmp("A335BONE", header.name, 8)) {
+		/* BeagleBone PMIC Code */
+		uchar pmic_status_reg;
+
+		if (i2c_probe(TPS65217_CHIP_PM))
+			return;
+
+		if (tps65217_reg_read(STATUS, &pmic_status_reg))
+			return;
+
+		/* Increase USB current limit to 1300mA */
+		if (tps65217_reg_write(PROT_LEVEL_NONE, POWER_PATH,
+				       USB_INPUT_CUR_LIMIT_1300MA,
+				       USB_INPUT_CUR_LIMIT_MASK))
+			printf("tps65217_reg_write failure\n");
+
+		/* Only perform PMIC configurations if board rev > A1 */
+		if (!strncmp(header.version, "00A1", 4))
+			return;
+
+		/* Set DCDC2 (MPU) voltage to 1.275V */
+		if (tps65217_voltage_update(DEFDCDC2,
+					     DCDC_VOLT_SEL_1275MV)) {
+			printf("tps65217_voltage_update failure\n");
+			return;
+		}
+
+		/* Set LDO3, LDO4 output voltage to 3.3V */
+		if (tps65217_reg_write(PROT_LEVEL_2, DEFLS1,
+				       LDO_VOLTAGE_OUT_3_3, LDO_MASK))
+			printf("tps65217_reg_write failure\n");
+
+		if (tps65217_reg_write(PROT_LEVEL_2, DEFLS2,
+				       LDO_VOLTAGE_OUT_3_3, LDO_MASK))
+			printf("tps65217_reg_write failure\n");
+
+		if (!(pmic_status_reg & PWR_SRC_AC_BITMASK)) {
+			printf("No AC power, disabling frequency switch\n");
+			return;
+		}
+
+		/* Set MPU Frequency to 720MHz */
+		mpu_pll_config(MPUPLL_M_720);
+	} else {
+		uchar buf[4];
+		/*
+		 * EVM PMIC code.  All boards currently want an MPU voltage
+		 * of 1.2625V and CORE voltage of 1.1375V to operate at
+		 * 720MHz.
+		 */
+		if (i2c_probe(PMIC_CTRL_I2C_ADDR))
+			return;
+
+		/* VDD1/2 voltage selection register access by control i/f */
+		if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
+			return;
+
+		buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
+
+		if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
+			return;
+
+		if (!voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) &&
+				!voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3))
+			/* Frequency switching for OPP 120 */
+			mpu_pll_config(MPUPLL_M_720);
+	}
+}
 #endif
 
 /*