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authorBo Shen <voice.shen@atmel.com>2013-04-15 16:16:09 +0800
committerBo Shen <voice.shen@atmel.com>2013-04-18 11:07:43 +0800
commit3e44b9bf68147d2857a8c29ba16c51a909c443fa (patch)
tree038c25e9cd913bffc39ca5cf96317455834c7777
parentadf2f66dbe8840a7bdc09db0e5af67ba36268b14 (diff)
ARM: at91/clock: at91sam9n12 has PLLA divisor by 2
The at91sam9n12 has PLLA divisor by 2, add it Signed-off-by: Bo Shen <voice.shen@atmel.com>
-rw-r--r--arch/arm/cpu/arm926ejs/at91/clock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
index 99e6956354..12eae4b38a 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -155,7 +155,7 @@ int at91_clock_init(unsigned long main_clock)
*/
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
- || defined(CONFIG_AT91SAM9X5)
+ || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
/* plla divisor by 2 */
gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif