diff options
| author | Tom Rini <trini@ti.com> | 2013-06-13 15:16:15 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-06-13 15:16:15 -0400 |
| commit | 41341221d12341a2ecfb280142d6478071738fc2 (patch) | |
| tree | 850a87b274b572b65a579474a0aad5e590ca6d61 | |
| parent | b7ab8b8ff092ab8214eeb86e8a79573154f448b9 (diff) | |
| parent | 847e6693ccb529bf8346db62876f38f0c4e04ade (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR
Conflicts:
arch/arm/include/asm/arch-omap5/omap.h
Signed-off-by: Tom Rini <trini@ti.com>
125 files changed, 4926 insertions, 3740 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 14075afae4..7820375e9c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -897,6 +897,10 @@ Steve Sakoman <sakoman@gmail.com> omap3_overo ARM ARMV7 (OMAP3xx SoC) +Leo Sartre <lsartre@adeneo-embedded.com> + + cgtqmx6qeval i.MX6Q + Jens Scharsig <esw@bus-elektronik.de> eb_cpux9k2 ARM920T (AT91RM9200 SoC) @@ -969,6 +973,10 @@ Hugo Villeneuve <hugo.villeneuve@lyrtech.com> SFFSDR ARM926EJS +Lokesh Vutla <lokeshvutla@ti.com> + + dra7xx_evm ARM ARMV7 (DRA7xx Soc) + Matt Waddel <matt.waddel@linaro.org> vexpress_ca9x4 ARM ARMV7 (Quad Core) @@ -1025,10 +1033,6 @@ Matthias Weisser <weisserm@arcor.de> jadecpu ARM926EJS (MB86R01 SoC) zmx25 ARM926EJS (imx25 SoC) -Richard Woodruff <r-woodruff2@ti.com> - - omap2420h4 ARM1136EJS - Josh Wu <josh.wu@atmel.com> at91sam9n12ek ARM926EJS (AT91SAM9N12 SoC) @@ -1066,6 +1070,14 @@ Eric Nelson <eric.nelson@boundarydevices.com> nitrogen6s i.MX6S 512MB nitrogen6s1g i.MX6S 1GB +Alison Wang <b18965@freescale.com> + + vf610twr VF610 + +Sergey Yanovich <ynvich@gmail.com> + + lp8x4x xscale/pxa + ------------------------------------------------------------------------- Unknown / orphaned boards: @@ -341,7 +341,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index edf249d902..a7e0c28c90 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -142,24 +142,6 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 -#ifdef CONFIG_OMAP2420H4 - /* Copy vectors to mask ROM indirect addr */ - adr r0, _start /* r0 <- current position of code */ - add r0, r0, #4 /* skip reset vector */ - mov r2, #64 /* r2 <- size to copy */ - add r2, r0, r2 /* r2 <- source end address */ - mov r1, #SRAM_OFFSET0 /* build vect addr */ - mov r3, #SRAM_OFFSET1 - add r1, r1, r3 - mov r3, #SRAM_OFFSET2 - add r1, r1, r3 -next: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next /* loop until equal */ - bl cpy_clk_code /* put dpll adjust code behind vectors */ -#endif /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index dec7bfbfaa..bba4671f78 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_SOC_DM646X) += dm646x.o +COBJS-$(CONFIG_SOC_DA830) += da830_pinmux.o COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c new file mode 100644 index 0000000000..d0c964a349 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c @@ -0,0 +1,151 @@ +/* + * Pinmux configurations for the DA830 SoCs + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/arch/davinci_misc.h> +#include <asm/arch/hardware.h> +#include <asm/arch/pinmux_defs.h> + +/* SPI0 pin muxer settings */ +const struct pinmux_config spi0_pins_base[] = { + { pinmux(7), 1, 3 }, /* SPI0_SOMI */ + { pinmux(7), 1, 4 }, /* SPI0_SIMO */ + { pinmux(7), 1, 6 } /* SPI0_CLK */ +}; + +const struct pinmux_config spi0_pins_scs0[] = { + { pinmux(7), 1, 7 } /* SPI0_SCS[0] */ +}; + +const struct pinmux_config spi0_pins_ena[] = { + { pinmux(7), 1, 5 } /* SPI0_ENA */ +}; + +/* NAND pin muxer settings */ +const struct pinmux_config emifa_pins_cs0[] = { + { pinmux(18), 1, 2 } /* EMA_CS[0] */ +}; + +const struct pinmux_config emifa_pins_cs2[] = { + { pinmux(18), 1, 3 } /* EMA_CS[2] */ +}; + +const struct pinmux_config emifa_pins_cs3[] = { + { pinmux(18), 1, 4 } /* EMA_CS[3] */ +}; + +#ifdef CONFIG_USE_NAND +const struct pinmux_config emifa_pins[] = { + { pinmux(13), 1, 6 }, /* EMA_D[0] */ + { pinmux(13), 1, 7 }, /* EMA_D[1] */ + { pinmux(14), 1, 0 }, /* EMA_D[2] */ + { pinmux(14), 1, 1 }, /* EMA_D[3] */ + { pinmux(14), 1, 2 }, /* EMA_D[4] */ + { pinmux(14), 1, 3 }, /* EMA_D[5] */ + { pinmux(14), 1, 4 }, /* EMA_D[6] */ + { pinmux(14), 1, 5 }, /* EMA_D[7] */ + { pinmux(14), 1, 6 }, /* EMA_D[8] */ + { pinmux(14), 1, 7 }, /* EMA_D[9] */ + { pinmux(15), 1, 0 }, /* EMA_D[10] */ + { pinmux(15), 1, 1 }, /* EMA_D[11] */ + { pinmux(15), 1, 2 }, /* EMA_D[12] */ + { pinmux(15), 1, 3 }, /* EMA_D[13] */ + { pinmux(15), 1, 4 }, /* EMA_D[14] */ + { pinmux(15), 1, 5 }, /* EMA_D[15] */ + { pinmux(15), 1, 6 }, /* EMA_A[0] */ + { pinmux(15), 1, 7 }, /* EMA_A[1] */ + { pinmux(16), 1, 0 }, /* EMA_A[2] */ + { pinmux(16), 1, 1 }, /* EMA_A[3] */ + { pinmux(16), 1, 2 }, /* EMA_A[4] */ + { pinmux(16), 1, 3 }, /* EMA_A[5] */ + { pinmux(16), 1, 4 }, /* EMA_A[6] */ + { pinmux(16), 1, 5 }, /* EMA_A[7] */ + { pinmux(16), 1, 6 }, /* EMA_A[8] */ + { pinmux(16), 1, 7 }, /* EMA_A[9] */ + { pinmux(17), 1, 0 }, /* EMA_A[10] */ + { pinmux(17), 1, 1 }, /* EMA_A[11] */ + { pinmux(17), 1, 2 }, /* EMA_A[12] */ + { pinmux(17), 1, 3 }, /* EMA_BA[1] */ + { pinmux(17), 1, 4 }, /* EMA_BA[0] */ + { pinmux(17), 1, 5 }, /* EMA_CLK */ + { pinmux(17), 1, 6 }, /* EMA_SDCKE */ + { pinmux(17), 1, 7 }, /* EMA_CAS */ + { pinmux(18), 1, 0 }, /* EMA_CAS */ + { pinmux(18), 1, 1 }, /* EMA_WE */ + { pinmux(18), 1, 5 }, /* EMA_OE */ + { pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */ + { pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */ + { pinmux(10), 1, 0 } /* Tristate */ +}; +#endif + +/* EMAC PHY interface pins */ +const struct pinmux_config emac_pins_rmii[] = { + { pinmux(10), 2, 1 }, /* RMII_TXD[0] */ + { pinmux(10), 2, 2 }, /* RMII_TXD[1] */ + { pinmux(10), 2, 3 }, /* RMII_TXEN */ + { pinmux(10), 2, 4 }, /* RMII_CRS_DV */ + { pinmux(10), 2, 5 }, /* RMII_RXD[0] */ + { pinmux(10), 2, 6 }, /* RMII_RXD[1] */ + { pinmux(10), 2, 7 } /* RMII_RXER */ +}; + +const struct pinmux_config emac_pins_mdio[] = { + { pinmux(11), 2, 0 }, /* MDIO_CLK */ + { pinmux(11), 2, 1 } /* MDIO_D */ +}; + +const struct pinmux_config emac_pins_rmii_clk_source[] = { + { pinmux(9), 0, 5 } /* ref.clk from external source */ +}; + +/* UART2 pin muxer settings */ +const struct pinmux_config uart2_pins_txrx[] = { + { pinmux(8), 2, 7 }, /* UART2_RXD */ + { pinmux(9), 2, 0 } /* UART2_TXD */ +}; + +/* I2C0 pin muxer settings */ +const struct pinmux_config i2c0_pins[] = { + { pinmux(8), 2, 3 }, /* I2C0_SDA */ + { pinmux(8), 2, 4 } /* I2C0_SCL */ +}; + +/* USB0_DRVVBUS pin muxer settings */ +const struct pinmux_config usb_pins[] = { + { pinmux(9), 1, 1 } /* USB0_DRVVBUS */ +}; + +#ifdef CONFIG_DAVINCI_MMC +/* MMC0 pin muxer settings */ +const struct pinmux_config mmc0_pins_8bit[] = { + { pinmux(15), 2, 7 }, /* MMCSD0_CLK */ + { pinmux(16), 2, 0 }, /* MMCSD0_CMD */ + { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */ + { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */ + { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */ + { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */ + { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */ + { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */ + { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */ + { pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */ + /* DA830 supports 8-bit mode */ +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index a5e388b5ad..45667bd8fb 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -76,13 +76,32 @@ void enable_caches(void) #endif } +/* + * This function will craft a jumptable at 0x0 which will redirect interrupt + * vectoring to proper location of U-Boot in RAM. + * + * The structure of the jumptable will be as follows: + * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times + * <destination address> ... for each previous ldr, thus also repeated 8 times + * + * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at + * offset 0x18 from current value of PC register. Note that PC is already + * incremented by 4 when computing the offset, so the effective offset is + * actually 0x20, this the associated <destination address>. Loading the PC + * register with an address performs a jump to that address. + */ void mx28_fixup_vt(uint32_t start_addr) { - uint32_t *vt = (uint32_t *)0x20; + /* ldr pc, [pc, #0x18] */ + const uint32_t ldr_pc = 0xe59ff018; + /* Jumptable location is 0x0 */ + uint32_t *vt = (uint32_t *)0x0; int i; - for (i = 0; i < 8; i++) - vt[i] = start_addr + (4 * i); + for (i = 0; i < 8; i++) { + vt[i] = ldr_pc; + vt[i + 8] = start_addr + (4 * i); + } } #ifdef CONFIG_ARCH_MISC_INIT diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 55e82ba369..c4b9809ad0 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -34,6 +34,7 @@ COBJS += hwinit-common.o COBJS += clocks-common.o COBJS += emif-common.o COBJS += vc.o +COBJS += abb.o endif ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c new file mode 100644 index 0000000000..87d1fb82eb --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/abb.c @@ -0,0 +1,137 @@ +/* + * + * Adaptive Body Bias programming sequence for OMAP family + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/omap_common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> + +__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) +{ + return -1; +} + +static void abb_setup_timings(u32 setup) +{ + u32 sys_rate, sr2_cnt, clk_cycles; + + /* + * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a + * transition and must be programmed with the correct time at boot. + * The value programmed into the register is the number of SYS_CLK + * clock cycles that match a given wall time profiled for the ldo. + * This value depends on: + * settling time of ldo in micro-seconds (varies per OMAP family), + * of clock cycles per SYS_CLK period (varies per OMAP family), + * the SYS_CLK frequency in MHz (varies per board) + * The formula is: + * + * ldo settling time (in micro-seconds) + * SR2_WTCNT_VALUE = ------------------------------------------ + * (# system clock cycles) * (sys_clk period) + * + * Put another way: + * + * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate)) + * + * To avoid dividing by zero multiply both "# clock cycles" and + * "settling time" by 10 such that the final result is the one we want. + */ + + /* calculate SR2_WTCNT_VALUE */ + sys_rate = DIV_ROUND(V_OSCK, 1000000); + clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate); + sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles); + + setbits_le32(setup, + sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1)); +} + +void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, + u32 txdone, u32 txdone_mask, u32 opp) +{ + u32 abb_type_mask, opp_sel_mask; + + /* sanity check */ + if (!setup || !control || !txdone) + return; + + /* setup ABB only in case of Fast or Slow OPP */ + switch (opp) { + case OMAP_ABB_FAST_OPP: + abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK; + opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK; + break; + case OMAP_ABB_SLOW_OPP: + abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK; + opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK; + break; + default: + return; + } + + /* + * For some OMAP silicons additional setup for LDOVBB register is + * required. This is determined by data retrieved from corresponding + * OPP EFUSE register. Data, which is retrieved from EFUSE - is + * ABB enable/disable flag and VSET value, which must be copied + * to LDOVBB register. If function call fails - return quietly, + * it means no ABB is required for such silicon. + * + * For silicons, which don't require LDOVBB setup "fuse" and + * "ldovbb" offsets are not defined. ABB will be initialized in + * the common way for them. + */ + if (fuse && ldovbb) { + if (abb_setup_ldovbb(fuse, ldovbb)) + return; + } + + /* clear ABB registers */ + writel(0, setup); + writel(0, control); + + /* configure timings, based on oscillator value */ + abb_setup_timings(setup); + + /* clear pending interrupts before setup */ + setbits_le32(txdone, txdone_mask); + + /* select ABB type */ + setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK); + + /* initiate ABB ldo change */ + setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); + + /* wait until transition complete */ + if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY)) + puts("Error: ABB txdone is not set\n"); + + /* clear ABB tranxdone */ + setbits_le32(txdone, txdone_mask); +} diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 99910cdcb0..ef23127bb6 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -30,9 +30,10 @@ * MA 02111-1307 USA */ #include <common.h> +#include <i2c.h> #include <asm/omap_common.h> #include <asm/gpio.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/utils.h> #include <asm/omap_gpio.h> @@ -49,13 +50,12 @@ const u32 sys_clk_array[8] = { 12000000, /* 12 MHz */ - 13000000, /* 13 MHz */ + 20000000, /* 20 MHz */ 16800000, /* 16.8 MHz */ 19200000, /* 19.2 MHz */ 26000000, /* 26 MHz */ 27000000, /* 27 MHz */ 38400000, /* 38.4 MHz */ - 20000000, /* 20 MHz */ }; static inline u32 __get_sys_clk_index(void) @@ -74,13 +74,6 @@ static inline u32 __get_sys_clk_index(void) /* SYS_CLKSEL - 1 to match the dpll param array indices */ ind = (readl((*prcm)->cm_sys_clksel) & CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; - /* - * SYS_CLKSEL value for 20MHz is 0. This is introduced newly - * in DRA7XX socs. SYS_CLKSEL -1 will be greater than - * NUM_SYS_CLK. So considering the last 3 bits as the index - * for the dpll param array. - */ - ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK; } return ind; } @@ -440,6 +433,12 @@ static void setup_non_essential_dplls(void) params = get_abe_dpll_params(*dplls_data); #ifdef CONFIG_SYS_OMAP_ABE_SYSCK abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; + + if (omap_revision() == DRA752_ES1_0) + /* Select the sys clk for dpll_abe */ + clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel, + CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK, + CM_ABE_PLL_SYS_CLKSEL_SYSCLK2); #else abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; /* @@ -487,6 +486,10 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) u32 offset = volt_mv; int ret = 0; + if (!volt_mv) + return; + + pmic->pmic_bus_init(); /* See if we can first get the GPIO if needed */ if (pmic->gpio_en) ret = gpio_request(pmic->gpio, "PMIC_GPIO"); @@ -509,14 +512,45 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, offset_code); - if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR, - vcore_reg, offset_code)) + if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code)) printf("Scaling voltage failed for 0x%x\n", vcore_reg); if (pmic->gpio_en) gpio_direction_output(pmic->gpio, 1); } +static u32 optimize_vcore_voltage(struct volts const *v) +{ + u32 val; + if (!v->value) + return 0; + if (!v->efuse.reg) + return v->value; + + switch (v->efuse.reg_bits) { + case 16: + val = readw(v->efuse.reg); + break; + case 32: + val = readl(v->efuse.reg); + break; + default: + printf("Error: efuse 0x%08x bits=%d unknown\n", + v->efuse.reg, v->efuse.reg_bits); + return v->value; + } + + if (!val) { + printf("Error: efuse 0x%08x bits=%d val=0, using %d\n", + v->efuse.reg, v->efuse.reg_bits, v->value); + return v->value; + } + + debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n", + __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val); + return val; +} + /* * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva * We set the maximum voltages allowed here because Smart-Reflex is not @@ -525,16 +559,34 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) */ void scale_vcores(struct vcores_data const *vcores) { - omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); + u32 val; + + val = optimize_vcore_voltage(&vcores->core); + do_scale_vcore(vcores->core.addr, val, vcores->core.pmic); + + val = optimize_vcore_voltage(&vcores->mpu); + do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic); + + /* Configure MPU ABB LDO after scale */ + abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2, + (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, + (*prcm)->prm_abbldo_mpu_setup, + (*prcm)->prm_abbldo_mpu_ctrl, + (*prcm)->prm_irqstatus_mpu_2, + OMAP_ABB_MPU_TXDONE_MASK, + OMAP_ABB_FAST_OPP); - do_scale_vcore(vcores->core.addr, vcores->core.value, - vcores->core.pmic); + val = optimize_vcore_voltage(&vcores->mm); + do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic); - do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, - vcores->mpu.pmic); + val = optimize_vcore_voltage(&vcores->gpu); + do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic); - do_scale_vcore(vcores->mm.addr, vcores->mm.value, - vcores->mm.pmic); + val = optimize_vcore_voltage(&vcores->eve); + do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic); + + val = optimize_vcore_voltage(&vcores->iva); + do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic); if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ @@ -710,6 +762,7 @@ void prcm_init(void) case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: enable_basic_clocks(); + timer_init(); scale_vcores(*omap_vcores); setup_dplls(); #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL @@ -725,3 +778,13 @@ void prcm_init(void) if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) enable_basic_uboot_clocks(); } + +void gpi2c_init(void) +{ + static int gpi2c = 1; + + if (gpi2c) { + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gpi2c = 0; + } +} diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 11e830a533..652e5a71b3 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -27,7 +27,7 @@ #include <common.h> #include <asm/emif.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> #include <asm/utils.h> @@ -209,7 +209,8 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - if (omap_revision() >= OMAP5430_ES1_0) { + if ((omap_revision() >= OMAP5430_ES1_0) || + (omap_revision() == DRA752_ES1_0)) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -263,6 +264,18 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs) __udelay(130); } +static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + config_data_eye_leveling_samples(base); + + writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); + writel(regs->sdram_config, &emif->emif_sdram_config); +} + static void ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -273,6 +286,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) * defined, contents of mode Registers must be fully initialized. * H/W takes care of this initialization */ + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); writel(regs->sdram_config_init, &emif->emif_sdram_config); writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); @@ -290,7 +304,10 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); - ddr3_leveling(base, regs); + if (omap_revision() == DRA752_ES1_0) + ddr3_sw_leveling(base, regs); + else + ddr3_leveling(base, regs); } #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS @@ -1078,7 +1095,10 @@ static void do_sdram_init(u32 base) if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { set_lpmode_selfrefresh(base); emif_reset_phy(base); - ddr3_leveling(base, regs); + if (omap_revision() == DRA752_ES1_0) + ddr3_sw_leveling(base, regs); + else + ddr3_leveling(base, regs); } /* Write to the shadow registers */ diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 0776d5c6e8..5df116edbe 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -166,8 +166,6 @@ void s_init(void) #endif prcm_init(); #ifdef CONFIG_SPL_BUILD - timer_init(); - /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); #endif diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 507f6873e9..5926a5a810 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -35,6 +35,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/cpu.h> +#include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c index e6e5f7893c..a68f1d145d 100644 --- a/arch/arm/cpu/armv7/omap-common/vc.c +++ b/arch/arm/cpu/armv7/omap-common/vc.c @@ -17,6 +17,7 @@ #include <common.h> #include <asm/omap_common.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> /* * Define Master code if there are multiple masters on the I2C_SR bus. @@ -57,7 +58,7 @@ * omap_vc_init() - Initialization for Voltage controller * @speed_khz: I2C buspeed in KHz */ -void omap_vc_init(u16 speed_khz) +static void omap_vc_init(u16 speed_khz) { u32 val; u32 sys_clk_khz, cycles_hi, cycles_low; @@ -137,3 +138,14 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) /* All good.. */ return 0; } + +void sri2c_init(void) +{ + static int sri2c = 1; + + if (sri2c) { + omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); + sri2c = 0; + } + return; +} diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 09c51f62aa..81cc859780 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -27,7 +27,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <asm/arch/clocks_omap3.h> #include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 06a2fc8c2f..b97cad4364 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -29,7 +29,7 @@ #include <asm/arch/omap.h> #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <asm/omap_gpio.h> #include <asm/io.h> @@ -219,6 +219,9 @@ struct pmic_data twl6030_4430es1 = { .step = 12660, /* 12.66 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; struct pmic_data twl6030 = { @@ -226,6 +229,9 @@ struct pmic_data twl6030 = { .step = 12660, /* 12.66 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; struct pmic_data tps62361 = { @@ -233,7 +239,10 @@ struct pmic_data tps62361 = { .step = 10000, /* 10 mV represented in uV */ .start_code = 0, .gpio = TPS62361_VSEL0_GPIO, - .gpio_en = 1 + .gpio_en = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; struct vcores_data omap4430_volts_es1 = { diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index 7225a301b1..7e71ca0a26 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -301,6 +301,8 @@ struct omap_sys_ctrl_regs const omap4_ctrl = { .control_ldosram_iva_voltage_ctrl = 0x4A002320, .control_ldosram_mpu_voltage_ctrl = 0x4A002324, .control_ldosram_core_voltage_ctrl = 0x4A002328, + .control_usbotghs_ctrl = 0x4A00233C, + .control_padconf_core_base = 0x4A100000, .control_pbiaslite = 0x4A100600, .control_lpddr2io1_0 = 0x4A100638, .control_lpddr2io1_1 = 0x4A10063C, @@ -312,4 +314,5 @@ struct omap_sys_ctrl_regs const omap4_ctrl = { .control_lpddr2io2_3 = 0x4A100654, .control_efuse_1 = 0x4A100700, .control_efuse_2 = 0x4A100704, + .control_padconf_wkup_base = 0x4A31E000, }; diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index ce00e2c3c5..6ff8dbb4eb 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -30,6 +30,7 @@ COBJS += emif.o COBJS += sdram.o COBJS += prcm-regs.o COBJS += hw_data.o +COBJS += abb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c new file mode 100644 index 0000000000..92470becc0 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/abb.c @@ -0,0 +1,67 @@ +/* + * + * Adaptive Body Bias programming sequence for OMAP5 family + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/omap_common.h> +#include <asm/io.h> + +/* + * Setup LDOVBB for OMAP5. + * On OMAP5+ some ABB settings are fused. They are handled + * in the following way: + * + * 1. corresponding EFUSE register contains ABB enable bit + * and VSET value + * 2. If ABB enable bit is set to 1, than ABB should be + * enabled, otherwise ABB should be disabled + * 3. If ABB is enabled, than VSET value should be copied + * to corresponding MUX control register + */ +s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) +{ + u32 vset; + + /* + * ABB parameters must be properly fused + * otherwise ABB should be disabled + */ + vset = readl(fuse); + if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK)) + return -1; + + /* prepare VSET value for LDOVBB mux register */ + vset &= OMAP5_ABB_FUSE_VSET_MASK; + vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1; + vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; + vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK; + + /* setup LDOVBB using fused value */ + clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset); + + return 0; +} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 604fa42b1b..56cf1f8c60 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -26,10 +26,11 @@ * MA 02111-1307 USA */ #include <common.h> +#include <palmas.h> #include <asm/arch/omap.h> #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <asm/omap_gpio.h> #include <asm/io.h> #include <asm/emif.h> @@ -99,14 +100,13 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { }; static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { - {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ - {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ + {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; static const struct dpll_params @@ -132,15 +132,14 @@ static const struct dpll_params }; static const struct dpll_params - core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = { - {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */ - {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */ - {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */ + core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { + {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ + {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ + {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ + {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ + {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */ - {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */ + {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ }; static const struct dpll_params @@ -186,14 +185,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { }; static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { - {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ + {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ + {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ - {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */ + {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ }; static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { @@ -206,6 +204,16 @@ static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { + {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + /* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { @@ -223,26 +231,36 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = { 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 }; +/* ABE M & N values with sysclk2(22.5792 MHz) as input */ +static const struct dpll_params + abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ - {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ }; -static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = { - {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ +static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { + {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ - {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ + {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; struct dplls omap5_dplls_es1 = { @@ -275,10 +293,12 @@ struct dplls omap5_dplls_es2 = { struct dplls dra7xx_dplls = { .mpu = mpu_dpll_params_1ghz, - .core = core_dpll_params_2128mhz_ddr532_dra7xx, + .core = core_dpll_params_2128mhz_dra7xx, .per = per_dpll_params_768mhz_dra7xx, + .abe = abe_dpll_params_sysclk2_361267khz, + .iva = iva_dpll_params_2330mhz_dra7xx, .usb = usb_dpll_params_1920mhz, - .ddr = ddr_dpll_params_1066mhz, + .ddr = ddr_dpll_params_2128mhz, }; struct pmic_data palmas = { @@ -289,6 +309,22 @@ struct pmic_data palmas = { * Offset code 0 switches OFF the SMPS */ .start_code = 6, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +struct pmic_data tps659038 = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, + .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, }; struct vcores_data omap5430_volts = { @@ -319,6 +355,38 @@ struct vcores_data omap5430_volts_es2 = { .mm.pmic = &palmas, }; +struct vcores_data dra752_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -383,12 +451,6 @@ void enable_basic_clocks(void) clk_modules_explicit_en_essential, 1); - /* Select 384Mhz for GPU as its the POR for ES1.0 */ - setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, - CLKSEL_GPU_HYD_GCLK_MASK); - setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, - CLKSEL_GPU_CORE_GCLK_MASK); - /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); @@ -540,6 +602,17 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = { .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, }; +const struct ctrl_ioregs ioregs_dra7xx_es1 = { + .ctrl_ddrch = 0x40404040, + .ctrl_lpddr2ch = 0x40404040, + .ctrl_ddr3ch = 0x80808080, + .ctrl_ddrio_0 = 0xbae8c631, + .ctrl_ddrio_1 = 0xb46318d8, + .ctrl_ddrio_2 = 0x84210000, + .ctrl_emif_sdram_config_ext = 0xb2c00000, + .ctrl_ddr_ctrl_ext_0 = 0xA2000000, +}; + void hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -565,7 +638,7 @@ void hw_data_init(void) case DRA752_ES1_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; - *omap_vcores = &omap5430_volts_es2; + *omap_vcores = &dra752_volts; *ctrl = &dra7xx_ctrl; break; @@ -582,14 +655,16 @@ void get_ioregs(const struct ctrl_ioregs **regs) case OMAP5430_ES1_0: case OMAP5430_ES2_0: *regs = &ioregs_omap5430; - break; + break; case OMAP5432_ES1_0: *regs = &ioregs_omap5432_es1; - break; + break; case OMAP5432_ES2_0: - case DRA752_ES1_0: *regs = &ioregs_omap5432_es2; - break; + break; + case DRA752_ES1_0: + *regs = &ioregs_dra7xx_es1; + break; default: printf("\n INVALID OMAP REVISION "); diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index e192fea0eb..daf124e99c 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -32,7 +32,7 @@ #include <asm/armv7.h> #include <asm/arch/cpu.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <asm/sizes.h> #include <asm/utils.h> #include <asm/arch/gpio.h> @@ -100,16 +100,21 @@ static void io_settings_ddr3(void) writel(ioregs->ctrl_emif_sdram_config_ext, (*ctrl)->control_emif2_sdram_config_ext); - /* Disable DLL select */ - io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) + if (is_omap54xx()) { + /* Disable DLL select */ + io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) & 0xFFEFFFFF); - writel(io_settings, - (*ctrl)->control_port_emif1_sdram_config); + writel(io_settings, + (*ctrl)->control_port_emif1_sdram_config); - io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) + io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) & 0xFFEFFFFF); - writel(io_settings, - (*ctrl)->control_port_emif2_sdram_config); + writel(io_settings, + (*ctrl)->control_port_emif2_sdram_config); + } else { + writel(ioregs->ctrl_ddr_ctrl_ext_0, + (*ctrl)->control_ddr_control_ext_0); + } } /* @@ -201,6 +206,9 @@ void srcomp_enable(void) u32 sysclk_ind = get_sys_clk_index(); u32 omap_rev = omap_revision(); + if (!is_omap54xx()) + return; + mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; div_factor = srcomp_parameters[sysclk_ind].divide_factor; diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index e9f6a32653..e839ff5fe5 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -298,6 +298,7 @@ struct prcm_regs const omap5_es1_prcm = { .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, .prm_rstctrl = 0x4ae07b00, .prm_rstst = 0x4ae07b04, + .prm_rsttime = 0x4ae07b08, .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, @@ -307,10 +308,16 @@ struct prcm_regs const omap5_es1_prcm = { .prm_sldo_mpu_ctrl = 0x4ae07bd0, .prm_sldo_mm_setup = 0x4ae07bd4, .prm_sldo_mm_ctrl = 0x4ae07bd8, + + /* SCRM stuff, used by some boards */ + .scrm_auxclk0 = 0x4ae0a310, + .scrm_auxclk1 = 0x4ae0a314, }; struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, + .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, + .control_padconf_core_base = 0x4A002800, .control_paconf_global = 0x4A002DA0, .control_paconf_mode = 0x4A002DA4, .control_smart1io_padconf_0 = 0x4A002DA8, @@ -358,6 +365,8 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_port_emif2_sdram_config = 0x4AE0C118, .control_emif1_sdram_config_ext = 0x4AE0C144, .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318, + .control_padconf_wkup_base = 0x4AE0C800, .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, .control_padconf_mode = 0x4AE0CDA8, @@ -434,6 +443,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_east_side = 0x4A002E7C, .control_srcomp_west_side = 0x4A002E80, .control_srcomp_code_latch = 0x4A002E84, + .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, @@ -709,6 +719,9 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, + /* prm irqstatus regs */ + .prm_irqstatus_mpu_2 = 0x4ae06014, + /* l4 wkup regs */ .cm_abe_pll_ref_clksel = 0x4ae0610c, .cm_sys_clksel = 0x4ae06110, @@ -740,6 +753,12 @@ struct prcm_regs const omap5_es2_prcm = { .prm_sldo_mpu_ctrl = 0x4ae07cd0, .prm_sldo_mm_setup = 0x4ae07cd4, .prm_sldo_mm_ctrl = 0x4ae07cd8, + .prm_abbldo_mpu_setup = 0x4ae07cdc, + .prm_abbldo_mpu_ctrl = 0x4ae07ce0, + + /* SCRM stuff, used by some boards */ + .scrm_auxclk0 = 0x4ae0a310, + .scrm_auxclk1 = 0x4ae0a314, }; struct prcm_regs const dra7xx_prcm = { @@ -941,6 +960,7 @@ struct prcm_regs const dra7xx_prcm = { /* l4 wkup regs */ .cm_abe_pll_ref_clksel = 0x4ae0610c, .cm_sys_clksel = 0x4ae06110, + .cm_abe_pll_sys_clksel = 0x4ae06118, .cm_wkup_clkstctrl = 0x4ae07800, .cm_wkup_l4wkup_clkctrl = 0x4ae07820, .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 6b461e4846..1b445a61eb 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -108,6 +108,7 @@ const struct emif_regs emif_regs_266_mhz_2cs = { const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { .sdram_config_init = 0x61851B32, .sdram_config = 0x61851B32, + .sdram_config2 = 0x0, .ref_ctrl = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, @@ -131,6 +132,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { .sdram_config_init = 0x61851B32, .sdram_config = 0x61851B32, + .sdram_config2 = 0x0, .ref_ctrl = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, @@ -151,6 +153,54 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { .emif_rd_wr_exec_thresh = 0x40000305 }; +const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { + .sdram_config_init = 0x61851ab2, + .sdram_config = 0x61851ab2, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0E20400A, + .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_3 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_4 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0020400A, + .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_3 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_4 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_5 = 0x009D009D, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, @@ -159,11 +209,39 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .is_ma_present = 0x1 }; -const struct dmm_lisa_map_regs lisa_map_512M_x_1 = { +/* + * DRA752 EVM board has 1.5 GB of memory + * EMIF1 --> 2Gb * 2 = 512MB + * EMIF2 --> 2Gb * 4 = 1GB + * so mapping 1GB interleaved and 512MB non-interleaved + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x80640300, + .dmm_lisa_map_2 = 0xC0500220, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +/* + * DRA752 EVM EMIF1 ONLY CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x0, - .dmm_lisa_map_3 = 0x80500100, + .dmm_lisa_map_2 = 0x80500100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +/* + * DRA752 EVM EMIF2 ONLY CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80600200, + .dmm_lisa_map_3 = 0xFF020100, .is_ma_present = 0x1 }; @@ -180,9 +258,20 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_532_mhz_2cs_es2; break; case OMAP5432_ES2_0: + *regs = &emif_regs_ddr3_532_mhz_1cs_es2; + break; case DRA752_ES1_0: + switch (emif_nr) { + case 1: + *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; + break; + case 2: + *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1; + break; + } + break; default: - *regs = &emif_regs_ddr3_532_mhz_1cs_es2; + *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } } @@ -201,7 +290,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs break; case DRA752_ES1_0: default: - *dmm_lisa_regs = &lisa_map_512M_x_1; + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; } } @@ -252,7 +341,8 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000077 + 0x00000077, + 0x0 }; const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { @@ -274,7 +364,8 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000057 + 0x00000057, + 0x0 }; const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { @@ -296,7 +387,56 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000057 + 0x00000057, + 0x0 +}; + +const u32 +dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x009E009E, + 0x002E002E, + 0x002E002E, + 0x002E002E, + 0x002E002E, + 0x002E002E, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x0, + 0x600020, + 0x40010080, + 0x8102040 +}; + +const u32 +dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x009D009D, + 0x002D002D, + 0x002D002D, + 0x002D002D, + 0x002D002D, + 0x002D002D, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x0, + 0x600020, + 0x40010080, + 0x8102040 }; const struct lpddr2_mr_regs mr_regs = { @@ -307,7 +447,7 @@ const struct lpddr2_mr_regs mr_regs = { .mr16 = MR16_REF_FULL_ARRAY }; -static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) +static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs) { switch (omap_revision()) { case OMAP5430_ES1_0: @@ -318,7 +458,14 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) *regs = ddr3_ext_phy_ctrl_const_base_es1; break; case OMAP5432_ES2_0: + *regs = ddr3_ext_phy_ctrl_const_base_es2; + break; case DRA752_ES1_0: + if (emif_nr == 1) + *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; + else + *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2; + break; default: *regs = ddr3_ext_phy_ctrl_const_base_es2; @@ -334,9 +481,12 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) { u32 *ext_phy_ctrl_base = 0; u32 *emif_ext_phy_ctrl_base = 0; + u32 emif_nr; const u32 *ext_phy_ctrl_const_regs; u32 i = 0; + emif_nr = (base == EMIF1_BASE) ? 1 : 2; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); @@ -353,7 +503,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) * external phy 6-24 registers do not change with * ddr frequency */ - emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs); + emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs); for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile new file mode 100644 index 0000000000..9232cd4276 --- /dev/null +++ b/arch/arm/cpu/armv7/vf610/Makefile @@ -0,0 +1,42 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS += generic.o +COBJS += timer.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c new file mode 100644 index 0000000000..87f2a8642d --- /dev/null +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -0,0 +1,324 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <netdev.h> +#ifdef CONFIG_FSL_ESDHC +#include <fsl_esdhc.h> +#endif + +#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&ccm->ccgr6); + if (enable) + reg |= CCM_CCGR6_OCOTP_CTRL_MASK; + else + reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK; + writel(reg, &ccm->ccgr6); +} +#endif + +static u32 get_mcu_main_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_ccsr, ccm_cacrr, armclk_div; + u32 sysclk_sel, pll_pfd_sel = 0; + u32 freq = 0; + + ccm_ccsr = readl(&ccm->ccsr); + sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK; + sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET; + + ccm_cacrr = readl(&ccm->cacrr); + armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK; + armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET; + armclk_div += 1; + + switch (sysclk_sel) { + case 0: + freq = FASE_CLK_FREQ; + break; + case 1: + freq = SLOW_CLK_FREQ; + break; + case 2: + pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK; + pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET; + if (pll_pfd_sel == 0) + freq = PLL2_MAIN_FREQ; + else if (pll_pfd_sel == 1) + freq = PLL2_PFD1_FREQ; + else if (pll_pfd_sel == 2) + freq = PLL2_PFD2_FREQ; + else if (pll_pfd_sel == 3) + freq = PLL2_PFD3_FREQ; + else if (pll_pfd_sel == 4) + freq = PLL2_PFD4_FREQ; + break; + case 3: + freq = PLL2_MAIN_FREQ; + break; + case 4: + pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; + pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET; + if (pll_pfd_sel == 0) + freq = PLL1_MAIN_FREQ; + else if (pll_pfd_sel == 1) + freq = PLL1_PFD1_FREQ; + else if (pll_pfd_sel == 2) + freq = PLL1_PFD2_FREQ; + else if (pll_pfd_sel == 3) + freq = PLL1_PFD3_FREQ; + else if (pll_pfd_sel == 4) + freq = PLL1_PFD4_FREQ; + break; + case 5: + freq = PLL3_MAIN_FREQ; + break; + default: + printf("unsupported system clock select\n"); + } + + return freq / armclk_div; +} + +static u32 get_bus_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_cacrr, busclk_div; + + ccm_cacrr = readl(&ccm->cacrr); + + busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK; + busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET; + busclk_div += 1; + + return get_mcu_main_clk() / busclk_div; +} + +static u32 get_ipg_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_cacrr, ipgclk_div; + + ccm_cacrr = readl(&ccm->cacrr); + + ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK; + ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET; + ipgclk_div += 1; + + return get_bus_clk() / ipgclk_div; +} + +static u32 get_uart_clk(void) +{ + return get_ipg_clk(); +} + +static u32 get_sdhc_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div; + u32 freq = 0; + + ccm_cscmr1 = readl(&ccm->cscmr1); + sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK; + sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET; + + ccm_cscdr2 = readl(&ccm->cscdr2); + sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK; + sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET; + sdhc_clk_div += 1; + + switch (sdhc_clk_sel) { + case 0: + freq = PLL3_MAIN_FREQ; + break; + case 1: + freq = PLL3_PFD3_FREQ; + break; + case 2: + freq = PLL1_PFD3_FREQ; + break; + case 3: + freq = get_bus_clk(); + break; + } + + return freq / sdhc_clk_div; +} + +u32 get_fec_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_cscmr2, rmii_clk_sel; + u32 freq = 0; + + ccm_cscmr2 = readl(&ccm->cscmr2); + rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK; + rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET; + + switch (rmii_clk_sel) { + case 0: + freq = ENET_EXTERNAL_CLK; + break; + case 1: + freq = AUDIO_EXTERNAL_CLK; + break; + case 2: + freq = PLL5_MAIN_FREQ; + break; + case 3: + freq = PLL5_MAIN_FREQ / 2; + break; + } + + return freq; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_mcu_main_clk(); + case MXC_BUS_CLK: + return get_bus_clk(); + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_UART_CLK: + return get_uart_clk(); + case MXC_ESDHC_CLK: + return get_sdhc_clk(); + case MXC_FEC_CLK: + return get_fec_clk(); + default: + break; + } + return -1; +} + +/* Dump some core clocks */ +int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + printf("\n"); + printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000); + printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000); + + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks, + "display clocks", + "" +); + +#ifdef CONFIG_FEC_MXC +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[4]; + struct fuse_bank4_regs *fuse = + (struct fuse_bank4_regs *)bank->fuse_regs; + + u32 value = readl(&fuse->mac_addr0); + mac[0] = (value >> 8); + mac[1] = value; + + value = readl(&fuse->mac_addr1); + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; +} +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +static char *get_reset_cause(void) +{ + u32 cause; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + cause = readl(&src_regs->srsr); + writel(cause, &src_regs->srsr); + cause &= 0xff; + + switch (cause) { + case 0x08: + return "WDOG"; + case 0x20: + return "JTAG HIGH-Z"; + case 0x80: + return "EXTERNAL RESET"; + case 0xfd: + return "POR"; + default: + return "unknown reset"; + } +} + +int print_cpuinfo(void) +{ + printf("CPU: Freescale Vybrid VF610 at %d MHz\n", + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause()); + + return 0; +} +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_FEC_MXC) + rc = fecmxc_initialize(bis); +#endif + + return rc; +} + +#ifdef CONFIG_FSL_ESDHC +int cpu_mmc_init(bd_t *bis) +{ + return fsl_esdhc_mmc_init(bis); +} +#endif + +int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} diff --git a/arch/arm/cpu/armv7/vf610/timer.c b/arch/arm/cpu/armv7/vf610/timer.c new file mode 100644 index 0000000000..f8fbed7864 --- /dev/null +++ b/arch/arm/cpu/armv7/vf610/timer.c @@ -0,0 +1,103 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <div64.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> + +static struct pit_reg *cur_pit = (struct pit_reg *)PIT_BASE_ADDR; + +DECLARE_GLOBAL_DATA_PTR; + +#define TIMER_LOAD_VAL 0xffffffff + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, mxc_get_clock(MXC_IPG_CLK)); + + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long usec) +{ + usec = usec * mxc_get_clock(MXC_IPG_CLK) + 999999; + do_div(usec, 1000000); + + return usec; +} + +int timer_init(void) +{ + __raw_writel(0, &cur_pit->mcr); + + __raw_writel(TIMER_LOAD_VAL, &cur_pit->ldval1); + __raw_writel(0, &cur_pit->tctrl1); + __raw_writel(1, &cur_pit->tctrl1); + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +unsigned long long get_ticks(void) +{ + ulong now = TIMER_LOAD_VAL - __raw_readl(&cur_pit->cval1); + + /* increment tbu if tbl has rolled over */ + if (now < gd->arch.tbl) + gd->arch.tbu++; + gd->arch.tbl = now; + + return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* delay x useconds AND preserve advance timstamp value */ +void __udelay(unsigned long usec) +{ + unsigned long long start; + ulong tmo; + + start = get_ticks(); /* get current timestamp */ + tmo = us_to_tick(usec); /* convert usecs to ticks */ + while ((get_ticks() - start) < tmo) + ; /* loop till time has passed */ +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return mxc_get_clock(MXC_IPG_CLK); +} diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index 0c186101ec..f07dc67823 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -244,7 +244,7 @@ void pxa_clock_setup(void) { writel(CONFIG_SYS_CKEN, CKEN); writel(CONFIG_SYS_CCCR, CCCR); - asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2)); + asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b)); /* enable the 32Khz oscillator for RTC and PowerManager */ writel(OSCC_OON, OSCC); diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index e099683890..9e6d51dd12 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -109,6 +109,10 @@ static void enable_scu(void) struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; u32 reg; + /* Only enable the SCU on T20/T25 */ + if (tegra_get_chip() != CHIPID_TEGRA20) + return; + /* If SCU already setup/enabled, return */ if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) return; diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 8bba8a57bf..9492326615 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libimx-common.o -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610)) COBJS-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 7fe5ce7ce5..35880c7a7c 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) __raw_writel(sel_input, base + sel_input_ofs); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG + if (!(pad_ctrl & NO_PAD_CTRL)) + __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl, + base + pad_ctrl_ofs); +#else if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); +#endif } void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h index a851f1f50f..beaf0d601a 100644 --- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -22,8 +22,14 @@ #define __ASM_ARCH_PINMUX_DEFS_H #include <asm/arch/davinci_misc.h> +#include <config.h> -/* SPI pin muxer settings */ +/* SPI0 pin muxer settings */ +extern const struct pinmux_config spi0_pins_base[3]; +extern const struct pinmux_config spi0_pins_scs0[1]; +extern const struct pinmux_config spi0_pins_ena[1]; + +/* SPI1 pin muxer settings */ extern const struct pinmux_config spi1_pins_base[3]; extern const struct pinmux_config spi1_pins_scs0[1]; @@ -35,6 +41,7 @@ extern const struct pinmux_config uart2_pins_rtscts[2]; /* EMAC pin muxer settings*/ extern const struct pinmux_config emac_pins_rmii[7]; +extern const struct pinmux_config emac_pins_rmii_clk_source[1]; extern const struct pinmux_config emac_pins_mii[15]; extern const struct pinmux_config emac_pins_mdio[2]; @@ -43,13 +50,19 @@ extern const struct pinmux_config i2c0_pins[2]; extern const struct pinmux_config i2c1_pins[2]; /* EMIFA pin muxer settings */ +extern const struct pinmux_config emifa_pins[40]; +extern const struct pinmux_config emifa_pins_cs0[1]; extern const struct pinmux_config emifa_pins_cs2[1]; extern const struct pinmux_config emifa_pins_cs3[1]; extern const struct pinmux_config emifa_pins_cs4[1]; extern const struct pinmux_config emifa_pins_nand[12]; extern const struct pinmux_config emifa_pins_nor[43]; +/* USB pin mux setting */ +extern const struct pinmux_config usb_pins[1]; + /* MMC pin muxer settings */ +extern const struct pinmux_config mmc0_pins_8bit[10]; extern const struct pinmux_config mmc0_pins[6]; #endif diff --git a/arch/arm/include/asm/arch-omap24xx/bits.h b/arch/arm/include/asm/arch-omap24xx/bits.h deleted file mode 100644 index 8522335bfc..0000000000 --- a/arch/arm/include/asm/arch-omap24xx/bits.h +++ /dev/null @@ -1,48 +0,0 @@ -/* bits.h - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/clocks.h b/arch/arm/include/asm/arch-omap24xx/clocks.h deleted file mode 100644 index 2e92569a9c..0000000000 --- a/arch/arm/include/asm/arch-omap24xx/clocks.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_CLOCKS_H_ -#define _OMAP24XX_CLOCKS_H_ - -#define COMMIT_DIVIDERS 0x1 - -#define MODE_BYPASS_FAST 0x2 -#define APLL_LOCK 0xc -#ifdef CONFIG_APTIX -#define DPLL_LOCK 0x1 /* stay in bypass mode */ -#else -#define DPLL_LOCK 0x3 /* DPLL lock */ -#endif - -/****************************************************************************; -; PRCM Scheme II -; -; Enable clocks and DPLL for: -; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 -; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] -; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] -; DSPI=100 6 CM_CLKSEL_DSP[6:5] -; DSP_S bypass CM_CLKSEL_DSP[7] -; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] -; IVAF=100 auto -; IVAI auto -; IVA_MPU auto -; IVA_S bypass CM_CLKSEL_DSP[13] -; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] -; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=100 auto -; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] -; L4=100Mhz 6 -; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define II_DPLL_OUT_X2 0x2 /* x2 core out */ -#define II_MPU_DIV 0x2 /* mpu = core/2 */ -#define II_DSP_DIV 0x343 /* dsp & iva divider */ -#define II_GFX_DIV 0x2 -#define II_BUS_DIV 0x04601026 -#define II_DPLL_300 0x01832100 - -/****************************************************************************; -; PRCM Scheme III -; -; Enable clocks and DPLL for: -; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 -; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] -; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] -; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] -; DSP_S ACTIVATED CM_CLKSEL_DSP[7] -; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] -; IVAF=88.67 auto -; IVAI auto -; IVA_MPU auto -; IVA_S ACTIVATED CM_CLKSEL_DSP[13] -; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: -; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=88.67 auto -; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] -; L4=66.5Mhz /8 -; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define III_DPLL_OUT_X2 0x2 /* x2 core out */ -#define III_MPU_DIV 0x2 /* mpu = core/2 */ -#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ -#define III_GFX_DIV 0x2 -#define III_BUS_DIV 0x08301044 -#define III_DPLL_266 0x01885500 - -/* set defaults for boot up */ -#ifdef PRCM_CONFIG_II -# define DPLL_OUT II_DPLL_OUT_X2 -# define MPU_DIV II_MPU_DIV -# define DSP_DIV II_DSP_DIV -# define GFX_DIV II_GFX_DIV -# define BUS_DIV II_BUS_DIV -# define DPLL_VAL II_DPLL_300 -#elif PRCM_CONFIG_III -# define DPLL_OUT III_DPLL_OUT_X2 -# define MPU_DIV III_MPU_DIV -# define DSP_DIV III_DSP_DIV -# define GFX_DIV III_GFX_DIV -# define BUS_DIV III_BUS_DIV -# define DPLL_VAL III_DPLL_266 -#endif - -/* lock delay time out */ -#define LDELAY 12000000 - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h deleted file mode 100644 index 6f645192a7..0000000000 --- a/arch/arm/include/asm/arch-omap24xx/i2c.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_I2C_H_ -#define _OMAP24XX_I2C_H_ - -#define I2C_BASE1 0x48070000 -#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -struct i2c { - unsigned short rev; /* 0x00 */ - unsigned short res1; - unsigned short ie; /* 0x04 */ - unsigned short res2; - unsigned short stat; /* 0x08 */ - unsigned short res3; - unsigned short iv; /* 0x0C */ - unsigned short res4; - unsigned short syss; /* 0x10 */ - unsigned short res4p1; - unsigned short buf; /* 0x14 */ - unsigned short res5; - unsigned short cnt; /* 0x18 */ - unsigned short res6; - unsigned short data; /* 0x1C */ - unsigned short res7; - unsigned short sysc; /* 0x20 */ - unsigned short res8; - unsigned short con; /* 0x24 */ - unsigned short res9; - unsigned short oa; /* 0x28 */ - unsigned short res10; - unsigned short sa; /* 0x2C */ - unsigned short res11; - unsigned short psc; /* 0x30 */ - unsigned short res12; - unsigned short scll; /* 0x34 */ - unsigned short res13; - unsigned short sclh; /* 0x38 */ - unsigned short res14; - unsigned short systest; /* 0x3c */ - unsigned short res15; -}; - -#define I2C_BUS_MAX 2 - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/mem.h b/arch/arm/include/asm/arch-omap24xx/mem.h deleted file mode 100644 index 42e8ab2bce..0000000000 --- a/arch/arm/include/asm/arch-omap24xx/mem.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_MEM_H_ -#define _OMAP24XX_MEM_H_ - -#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ -/* struct's for holding data tables for current boards, they are getting used - early in init when NO global access are there */ -struct sdrc_data_s { - u32 sdrc_sharing; - u32 sdrc_mdcfg_0_ddr; - u32 sdrc_mdcfg_0_sdr; - u32 sdrc_actim_ctrla_0; - u32 sdrc_actim_ctrlb_0; - u32 sdrc_rfr_ctrl; - u32 sdrc_mr_0_ddr; - u32 sdrc_mr_0_sdr; - u32 sdrc_dllab_ctrl; -} /*__attribute__ ((packed))*/; -typedef struct sdrc_data_s sdrc_data_t; - -typedef enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -} mem_t; - -#endif - -/* Slower full frequency range default timings for x32 operation*/ -#define H4_2420_SDRC_SHARING 0x00000100 -#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ -#define H4_2420_SDRC_MR_0_SDR 0x00000031 -#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ -#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ -#define H4_2420_SDRC_MR_0_DDR 0x00000032 - -#define H4_2422_SDRC_SHARING 0x00004b00 -#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */ -#define H4_2422_SDRC_MR_0_DDR 0x00000032 - -/* ES1 work around timings */ -#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ -#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 -#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ - -/* optimized timings good for current shipping parts */ -#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 -#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e -#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ -#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ -#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 -#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 -#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/ -#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */ - -#ifdef PRCM_CONFIG_II -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz -#elif PRCM_CONFIG_III -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz -#endif - - -/* GPMC settings */ -#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ -# ifdef CONFIG_SYS_NAND_BOOT -# define H4_24XX_GPMC_CONFIG1_0 0x0 -# define H4_24XX_GPMC_CONFIG2_0 0x00141400 -# define H4_24XX_GPMC_CONFIG3_0 0x00141400 -# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -# else /* else NOR */ -# define H4_24XX_GPMC_CONFIG1_0 0x3 -# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 -# define H4_24XX_GPMC_CONFIG3_0 0x00050502 -# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 -# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -# endif /* endif CONFIG_SYS_NAND_BOOT */ -# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) -# define H4_24XX_GPMC_CONFIG1_1 0x00011000 -# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 -# define H4_24XX_GPMC_CONFIG3_1 0x00080802 -# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F -# define H4_24XX_GPMC_CONFIG6_1 0x000003C2 -# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif /* endif PRCM_CONFIG_II */ - -#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ -# ifdef CONFIG_SYS_NAND_BOOT -# define H4_24XX_GPMC_CONFIG1_0 0x0 -# define H4_24XX_GPMC_CONFIG2_0 0x00141400 -# define H4_24XX_GPMC_CONFIG3_0 0x00141400 -# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -# else /* NOR boot */ -# define H4_24XX_GPMC_CONFIG1_0 0x3 -# define H4_24XX_GPMC_CONFIG2_0 0x00151501 -# define H4_24XX_GPMC_CONFIG3_0 0x00060602 -# define H4_24XX_GPMC_CONFIG4_0 0x10081008 -# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -# define H4_24XX_GPMC_CONFIG6_0 0x000004c4 -# endif /* endif CONFIG_SYS_NAND_BOOT */ -# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) -# define H4_24XX_GPMC_CONFIG1_1 0x00011000 -# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 -# define H4_24XX_GPMC_CONFIG3_1 0x00080803 -# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F -# define H4_24XX_GPMC_CONFIG6_1 0x000004C4 -# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif /* endif CONFIG_SYS_PRCM_III */ - -#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap24xx/mux.h b/arch/arm/include/asm/arch-omap24xx/mux.h deleted file mode 100644 index 4fdb9c635f..0000000000 --- a/arch/arm/include/asm/arch-omap24xx/mux.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP2420_MUX_H_ -#define _OMAP2420_MUX_H_ - -#ifndef __ASSEMBLY__ -typedef unsigned char uint8; -typedef unsigned int uint32; - -void muxSetupSDRC(void); -void muxSetupGPMC(void); -void muxSetupUsb0(void); -void muxSetupUsbHost(void); -void muxSetupUart3(void); -void muxSetupI2C1(void); -void muxSetupUART1(void); -void muxSetupLCD(void); -void muxSetupCamera(void); -void muxSetupMMCSD(void) ; -void muxSetupTouchScreen(void) ; -void muxSetupHDQ(void); -#endif - -#define USB_OTG_CTRL ((volatile uint32 *)0x4805E30C) - -/* Pin Muxing registers used for HDQ (Smart battery) */ -#define CONTROL_PADCONF_HDQ_SIO ((volatile unsigned char *)0x48000115) - -/* Pin Muxing registers used for GPMC */ -#define CONTROL_PADCONF_GPMC_D2_BYTE0 ((volatile unsigned char *)0x48000088) -#define CONTROL_PADCONF_GPMC_D2_BYTE1 ((volatile unsigned char *)0x48000089) -#define CONTROL_PADCONF_GPMC_D2_BYTE2 ((volatile unsigned char *)0x4800008A) -#define CONTROL_PADCONF_GPMC_D2_BYTE3 ((volatile unsigned char *)0x4800008B) - -#define CONTROL_PADCONF_GPMC_NCS0_BYTE0 ((volatile unsigned char *)0x4800008C) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE4 (0x48000090) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE5 (0x48000091) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE6 (0x48000092) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE7 (0x48000093) - -/* Pin Muxing registers used for SDRC */ -#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0) -#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1) -#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2) -#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3) - -#define CONTROL_PADCONF_SDRC_A14_BYTE0 ((volatile unsigned char *)0x48000030) -#define CONTROL_PADCONF_SDRC_A14_BYTE1 ((volatile unsigned char *)0x48000031) -#define CONTROL_PADCONF_SDRC_A14_BYTE2 ((volatile unsigned char *)0x48000032) -#define CONTROL_PADCONF_SDRC_A14_BYTE3 ((volatile unsigned char *)0x48000033) - -/* Pin Muxing registers used for Touch Screen (SPI) */ -#define CONTROL_PADCONF_SPI1_CLK ((volatile unsigned char *)0x480000FF) -#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100) -#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101) -#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102) -#define CONTROL_PADCONF_SPI1_NCS1 (0x48000103) - -#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B) - -/* Pin Muxing registers used for MMCSD */ -#define CONTROL_PADCONF_MMC_CLKI ((volatile unsigned char *)0x480000FE) -#define CONTROL_PADCONF_MMC_CLKO ((volatile unsigned char *)0x480000F3) -#define CONTROL_PADCONF_MMC_CMD ((volatile unsigned char *)0x480000F4) -#define CONTROL_PADCONF_MMC_DAT0 ((volatile unsigned char *)0x480000F5) -#define CONTROL_PADCONF_MMC_DAT1 ((volatile unsigned char *)0x480000F6) -#define CONTROL_PADCONF_MMC_DAT2 ((volatile unsigned char *)0x480000F7) -#define CONTROL_PADCONF_MMC_DAT3 ((volatile unsigned char *)0x480000F8) -#define CONTROL_PADCONF_MMC_DAT_DIR0 ((volatile unsigned char *)0x480000F9) -#define CONTROL_PADCONF_MMC_DAT_DIR1 ((volatile unsigned char *)0x480000FA) -#define CONTROL_PADCONF_MMC_DAT_DIR2 ((volatile unsigned char *)0x480000FB) -#define CONTROL_PADCONF_MMC_DAT_DIR3 ((volatile unsigned char *)0x480000FC) -#define CONTROL_PADCONF_MMC_CMD_DIR ((volatile unsigned char *)0x480000FD) - -#define CONTROL_PADCONF_SDRC_A14 ((volatile unsigned char *)0x48000030) -#define CONTROL_PADCONF_SDRC_A13 ((volatile unsigned char *)0x48000031) - -/* Pin Muxing registers used for CAMERA */ -#define CONTROL_PADCONF_SYS_NRESWARM ((volatile unsigned char *)0x4800012B) - -#define CONTROL_PADCONF_CAM_XCLK ((volatile unsigned char *)0x480000DC) -#define CONTROL_PADCONF_CAM_LCLK ((volatile unsigned char *)0x480000DB) -#define CONTROL_PADCONF_CAM_VS ((volatile unsigned char *)0x480000DA) -#define CONTROL_PADCONF_CAM_HS ((volatile unsigned char *)0x480000D9) -#define CONTROL_PADCONF_CAM_D0 ((volatile unsigned char *)0x480000D8) -#define CONTROL_PADCONF_CAM_D1 ((volatile unsigned char *)0x480000D7) -#define CONTROL_PADCONF_CAM_D2 ((volatile unsigned char *)0x480000D6) -#define CONTROL_PADCONF_CAM_D3 ((volatile unsigned char *)0x480000D5) -#define CONTROL_PADCONF_CAM_D4 ((volatile unsigned char *)0x480000D4) -#define CONTROL_PADCONF_CAM_D5 ((volatile unsigned char *)0x480000D3) -#define CONTROL_PADCONF_CAM_D6 ((volatile unsigned char *)0x480000D2) -#define CONTROL_PADCONF_CAM_D7 ((volatile unsigned char *)0x480000D1) -#define CONTROL_PADCONF_CAM_D8 ((volatile unsigned char *)0x480000D0) -#define CONTROL_PADCONF_CAM_D9 ((volatile unsigned char *)0x480000CF) - -/* Pin Muxing registers used for LCD */ -#define CONTROL_PADCONF_DSS_D0 ((volatile unsigned char *)0x480000B3) -#define CONTROL_PADCONF_DSS_D1 ((volatile unsigned char *)0x480000B4) -#define CONTROL_PADCONF_DSS_D2 ((volatile unsigned char *)0x480000B5) -#define CONTROL_PADCONF_DSS_D3 ((volatile unsigned char *)0x480000B6) -#define CONTROL_PADCONF_DSS_D4 ((volatile unsigned char *)0x480000B7) -#define CONTROL_PADCONF_DSS_D5 ((volatile unsigned char *)0x480000B8) -#define CONTROL_PADCONF_DSS_D6 ((volatile unsigned char *)0x480000B9) -#define CONTROL_PADCONF_DSS_D7 ((volatile unsigned char *)0x480000BA) -#define CONTROL_PADCONF_DSS_D8 ((volatile unsigned char *)0x480000BB) -#define CONTROL_PADCONF_DSS_D9 ((volatile unsigned char *)0x480000BC) -#define CONTROL_PADCONF_DSS_D10 ((volatile unsigned char *)0x480000BD) -#define CONTROL_PADCONF_DSS_D11 ((volatile unsigned char *)0x480000BE) -#define CONTROL_PADCONF_DSS_D12 ((volatile unsigned char *)0x480000BF) -#define CONTROL_PADCONF_DSS_D13 ((volatile unsigned char *)0x480000C0) -#define CONTROL_PADCONF_DSS_D14 ((volatile unsigned char *)0x480000C1) -#define CONTROL_PADCONF_DSS_D15 ((volatile unsigned char *)0x480000C2) -#define CONTROL_PADCONF_DSS_D16 ((volatile unsigned char *)0x480000C3) -#define CONTROL_PADCONF_DSS_D17 ((volatile unsigned char *)0x480000C4) -#define CONTROL_PADCONF_DSS_PCLK ((volatile unsigned char *)0x480000CB) -#define CONTROL_PADCONF_DSS_VSYNC ((volatile unsigned char *)0x480000CC) -#define CONTROL_PADCONF_DSS_HSYNC ((volatile unsigned char *)0x480000CD) -#define CONTROL_PADCONF_DSS_ACBIAS ((volatile unsigned char *)0x480000CE) - -/* Pin Muxing registers used for UART1 */ -#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) -#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) -#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) -#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) - -/* Pin Muxing registers used for I2C1 */ -#define CONTROL_PADCONF_I2C1_SCL ((volatile unsigned char *)0x48000111) -#define CONTROL_PADCONF_I2C1_SDA ((volatile unsigned char *)0x48000112) - -/* Pin Muxing registres used for USB0. */ -#define CONTROL_PADCONF_USB0_PUEN ((volatile uint8 *)0x4800011D) -#define CONTROL_PADCONF_USB0_VP ((volatile uint8 *)0x4800011E) -#define CONTROL_PADCONF_USB0_VM ((volatile uint8 *)0x4800011F) -#define CONTROL_PADCONF_USB0_RCV ((volatile uint8 *)0x48000120) -#define CONTROL_PADCONF_USB0_TXEN ((volatile uint8 *)0x48000121) -#define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122) -#define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123) - -/* Pin Muxing registres used for USB1. */ -#define CONTROL_PADCONF_USB1_RCV (0x480000EB) -#define CONTROL_PADCONF_USB1_TXEN (0x480000EC) - -/* Pin Muxing registers used for UART3/IRDA */ -#define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118) -#define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119) - -/* Pin Muxing registers used for GPIO */ -#define CONTROL_PADCONF_GPIO69 (0x480000ED) -#define CONTROL_PADCONF_GPIO70 (0x480000EE) -#define CONTROL_PADCONF_GPIO102 (0x48000116) -#define CONTROL_PADCONF_GPIO103 (0x48000117) -#define CONTROL_PADCONF_GPIO104 (0x48000118) -#define CONTROL_PADCONF_GPIO105 (0x48000119) - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h deleted file mode 100644 index 5724f5d4ba..0000000000 --- a/arch/arm/include/asm/arch-omap24xx/omap2420.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2420_SYS_H_ -#define _OMAP2420_SYS_H_ - -#include <asm/sizes.h> - -/* - * 2420 specific Section - */ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 -/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 - -/* CONTROL */ -#define OMAP2420_CTRL_BASE (0x48000000) -#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) - -/* device type */ -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* TAP information */ -#define OMAP2420_TAP_BASE (0x48014000) -#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) -#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) - -/* GPMC */ -#define OMAP2420_GPMC_BASE (0x6800A000) -#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) -#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) -#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) -#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) -#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) -#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) -#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) -#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) -#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) -#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) -#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) -#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) -#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) -#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) -#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) -#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) - -/* SMS */ -#define OMAP2420_SMS_BASE 0x68008000 -#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) -#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0) -# define BURSTCOMPLETE_GROUP7 BIT31 - -/* SDRC */ -#define OMAP2420_SDRC_BASE 0x68009000 -#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) -#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) -#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) -#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) -#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) -#define OMAP2420_SDRC_CS0 0x80000000 -#define OMAP2420_SDRC_CS1 0xA0000000 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2420_UART1 0x4806A000 -#define OMAP2420_UART2 0x4806C000 -#define OMAP2420_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP2420_GPT1 0x48028000 -#define OMAP2420_GPT2 0x4802A000 -#define OMAP2420_GPT3 0x48078000 -#define OMAP2420_GPT4 0x4807A000 -#define OMAP2420_GPT5 0x4807C000 -#define OMAP2420_GPT6 0x4807E000 -#define OMAP2420_GPT7 0x48080000 -#define OMAP2420_GPT8 0x48082000 -#define OMAP2420_GPT9 0x48084000 -#define OMAP2420_GPT10 0x48086000 -#define OMAP2420_GPT11 0x48088000 -#define OMAP2420_GPT12 0x4808A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x48020000 -#define WD2_BASE 0x48022000 -#define WD3_BASE 0x48024000 -#define WD4_BASE 0x48026000 -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP2420_CM_BASE 0x48008000 -#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) -#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) -#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) -#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) - -/* - * H4 specific Section - */ - -/* - * The 2420's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP2420H4) -/* GPMC */ -#ifdef CONFIG_VIRTIO_A /* Pre version B */ -# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x04000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#else -# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x04000000 /* debug board */ -# define H4_CS2_BASE 0x0C000000 /* wifi board */ -#endif - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) -#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) -#endif /* endif CONFIG_2420H4 */ - -/* Common */ -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/sys_info.h b/arch/arm/include/asm/arch-omap24xx/sys_info.h deleted file mode 100644 index 53c231a5e4..0000000000 --- a/arch/arm/include/asm/arch-omap24xx/sys_info.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_SYS_INFO_H_ -#define _OMAP24XX_SYS_INFO_H_ - -typedef struct h4_system_data { - /* base board info */ - u32 base_b_rev; /* rev from base board i2c */ - /* cpu board info */ - u32 cpu_b_rev; /* rev from cpu board i2c */ - u32 cpu_b_mux; /* mux type on daughter board */ - u32 cpu_b_ddr_type; /* mem type */ - u32 cpu_b_ddr_speed; /* ddr speed rating */ - u32 cpu_b_switches; /* boot ctrl switch settings */ - /* cpu info */ - u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ - u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ -} h4_sys_data; - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_2420 0x2420 -#define CPU_2422 0x2422 /* 2420 + 64M stacked */ -#define CPU_2423 0x2423 /* 2420 + 96M stacked */ - -#define CPU_2422_ES1 1 -#define CPU_2422_ES2 2 -#define CPU_2420_ES1 1 -#define CPU_2420_ES2 2 -#define CPU_2420_2422_ES1 1 - -#define CPU_2420_CHIPID 0x0B5D9000 -#define CPU_24XX_ID_MASK 0x0FFFF000 -#define CPU_242X_REV_MASK 0xF0000000 -#define CPU_242X_PID_MASK 0x000F0000 - -#define BOARD_H4_MENELAUS 1 -#define BOARD_H4_SDP 2 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/sys_proto.h b/arch/arm/include/asm/arch-omap24xx/sys_proto.h deleted file mode 100644 index 9d8e5b2622..0000000000 --- a/arch/arm/include/asm/arch-omap24xx/sys_proto.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_SYS_PROTO_H_ -#define _OMAP24XX_SYS_PROTO_H_ - -void prcm_init(void); -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32,u32); -void gpmc_init(void); - -void ether_init(void); -void watchdog_init(void); -void set_muxconf_regs(void); -void peripheral_enable(void); - -u32 get_cpu_type(void); -u32 get_cpu_rev(void); -u32 get_mem_type(void); -u32 get_sysboot_value(void); -u32 get_gpmc0_base(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); -u32 get_board_type(void); -void display_board_info(u32); -void update_mux(u32,u32); -u32 get_sdr_cs_size(u32 offset); - -u32 running_in_sdram(void); -u32 running_in_sram(void); -u32 running_in_flash(void); -u32 running_from_internal_boot(void); -u32 get_device_type(void); -#endif diff --git a/arch/arm/include/asm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clock.h index bed0002ec0..bed0002ec0 100644 --- a/arch/arm/include/asm/arch-omap3/clocks.h +++ b/arch/arm/include/asm/arch-omap3/clock.h diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 2b5e9aeae1..c57599a938 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -253,4 +253,11 @@ struct gpio { #define OMAP3_EMU_HAL_START_HAL_CRITICAL 4 +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 30 +#define OMAP_ABB_CLOCK_CYCLES 8 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26) + #endif diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clock.h index ed7a1c8be7..d14d8fb8af 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -34,25 +34,6 @@ */ #define LDELAY 1000000 -#define CM_CLKMODE_DPLL_CORE 0x4A004120 -#define CM_CLKMODE_DPLL_PER 0x4A008140 -#define CM_CLKMODE_DPLL_MPU 0x4A004160 -#define CM_CLKSEL_CORE 0x4A004100 - -/* DPLL register offsets */ -#define CM_CLKMODE_DPLL 0 -#define CM_IDLEST_DPLL 0x4 -#define CM_AUTOIDLE_DPLL 0x8 -#define CM_CLKSEL_DPLL 0xC -#define CM_DIV_M2_DPLL 0x10 -#define CM_DIV_M3_DPLL 0x14 -#define CM_DIV_M4_DPLL 0x18 -#define CM_DIV_M5_DPLL 0x1C -#define CM_DIV_M6_DPLL 0x20 -#define CM_DIV_M7_DPLL 0x24 - -#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ - /* CM_DLL_CTRL */ #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) @@ -94,10 +75,8 @@ #define CM_CLKSEL_DCC_EN_SHIFT 22 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) -#define OMAP4_DPLL_MAX_N 127 - /* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 /* CM_CLKSEL_CORE */ #define CLKSEL_CORE_SHIFT 0 @@ -181,9 +160,7 @@ #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) /* Clock frequencies */ -#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 -#define OMAP_32K_CLK_FREQ 32768 /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 @@ -234,14 +211,13 @@ #define ALTCLKSRC_MODE_ACTIVE 1 -/* Defines for DPLL setup */ -#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 -#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 -#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 - #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 +/* Clock Defines */ +#define V_OSCK 38400000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + struct omap4_scrm_regs { u32 revision; /* 0x0000 */ u32 pad00[63]; diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index 3a0bfbf0c6..311c6ff522 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -115,18 +115,6 @@ struct watchdog { #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 -#define SYSCLKDIV_1 (0x1 << 6) -#define SYSCLKDIV_2 (0x1 << 7) - -#define CLKSEL_GPT1 (0x1 << 0) - -#define EN_GPT1 (0x1 << 0) -#define EN_32KSYNC (0x1 << 2) - -#define ST_WDT2 (0x1 << 5) - -#define RESETDONE (0x1 << 0) - #define TCLR_ST (0x1 << 0) #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 44353a43f2..9fd00ff2aa 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -47,14 +47,6 @@ #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END -/* CONTROL */ -#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) -#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) -#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000) - -/* LPDDR2 IO regs */ -#define LPDDR2_IO_REGS_BASE 0x4A100638 - /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE 0x4A002204 @@ -79,15 +71,9 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000) - /* GPMC */ #define OMAP44XX_GPMC_BASE 0x50000000 -/* SYSTEM CONTROL MODULE */ -#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000 - /* * Hardware Register Details */ @@ -144,4 +130,12 @@ struct s32ktimer { #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4030D000 + +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 50 +#define OMAP_ABB_CLOCK_CYCLES 16 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) + #endif diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ef85594bd2..e413466148 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -22,7 +22,7 @@ #define _SYS_PROTO_H_ #include <asm/arch/omap.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <asm/io.h> #include <asm/omap_common.h> #include <asm/arch/mux_omap4.h> @@ -57,7 +57,8 @@ u32 cortex_rev(void); void save_omap_boot_params(void); void init_omap_revision(void); void do_io_settings(void); -void omap_vc_init(u16 speed_khz); +void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clock.h index 68afa76696..4d2765d878 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -35,19 +35,6 @@ */ #define LDELAY 1000000 -#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120) -#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140) -#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160) -#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100) - -/* DPLL register offsets */ -#define CM_CLKMODE_DPLL 0 -#define CM_IDLEST_DPLL 0x4 -#define CM_AUTOIDLE_DPLL 0x8 -#define CM_CLKSEL_DPLL 0xC - -#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ - /* CM_DLL_CTRL */ #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) @@ -93,10 +80,8 @@ #define CM_CLKSEL_DCC_EN_SHIFT 22 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) -#define OMAP4_DPLL_MAX_N 127 - /* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 /* CM_CLKSEL_CORE */ #define CLKSEL_CORE_SHIFT 0 @@ -113,6 +98,12 @@ #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 +/* CM_CLKSEL_ABE_PLL_SYS */ +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 + /* CM_BYPCLK_DPLL_IVA */ #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 @@ -195,9 +186,7 @@ #define RSTTIME1_MASK (0x3ff << 0) /* Clock frequencies */ -#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 -#define OMAP_32K_CLK_FREQ 32768 /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 @@ -229,9 +218,54 @@ #define VDD_MPU_ES2_LOW 880 #define VDD_MM_ES2_LOW 880 +/* TPS659038 Voltage settings in mv for OPP_NOMINAL */ +#define VDD_MPU_DRA752 1090 +#define VDD_EVE_DRA752 1060 +#define VDD_GPU_DRA752 1060 +#define VDD_CORE_DRA752 1030 +#define VDD_IVA_DRA752 1060 + +/* Efuse register offsets for DRA7xx platform */ +#define DRA752_EFUSE_BASE 0x4A002000 +#define DRA752_EFUSE_REGBITS 16 +/* STD_FUSE_OPP_VMIN_IVA_2 */ +#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) +/* STD_FUSE_OPP_VMIN_IVA_3 */ +#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) +/* STD_FUSE_OPP_VMIN_IVA_4 */ +#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) +/* STD_FUSE_OPP_VMIN_DSPEVE_2 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) +/* STD_FUSE_OPP_VMIN_DSPEVE_3 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) +/* STD_FUSE_OPP_VMIN_DSPEVE_4 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) +/* STD_FUSE_OPP_VMIN_CORE_2 */ +#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) +/* STD_FUSE_OPP_VMIN_GPU_2 */ +#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) +/* STD_FUSE_OPP_VMIN_GPU_3 */ +#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) +/* STD_FUSE_OPP_VMIN_GPU_4 */ +#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) +/* STD_FUSE_OPP_VMIN_MPU_2 */ +#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) +/* STD_FUSE_OPP_VMIN_MPU_3 */ +#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) +/* STD_FUSE_OPP_VMIN_MPU_4 */ +#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 +/* TPS659038 */ +#define TPS659038_I2C_SLAVE_ADDR 0x58 +#define TPS659038_REG_ADDR_SMPS12_MPU 0x23 +#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B +#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F +#define TPS659038_REG_ADDR_SMPS7_CORE 0x33 +#define TPS659038_REG_ADDR_SMPS8_IVA 0x37 + /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 #define TPS62361_REG_ADDR_SET0 0x0 @@ -261,4 +295,25 @@ * into microsec and passing the value. */ #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 + +#ifdef CONFIG_DRA7XX +#define V_OSCK 20000000 /* Clock output from T2 */ +#else +#define V_OSCK 19200000 /* Clock output from T2 */ +#endif + +#define V_SCLK V_OSCK + +/* AUXCLKx reg fields */ +#define AUXCLK_ENABLE_MASK (1 << 8) +#define AUXCLK_SRCSELECT_SHIFT 1 +#define AUXCLK_SRCSELECT_MASK (3 << 1) +#define AUXCLK_CLKDIV_SHIFT 16 +#define AUXCLK_CLKDIV_MASK (0xF << 16) + +#define AUXCLK_SRCSELECT_SYS_CLK 0 +#define AUXCLK_SRCSELECT_CORE_DPLL 1 +#define AUXCLK_SRCSELECT_PER_DPLL 2 +#define AUXCLK_SRCSELECT_ALTERNATE 3 + #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 044ab5581a..4753f4624e 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -119,18 +119,6 @@ struct watchdog { #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 -#define SYSCLKDIV_1 (0x1 << 6) -#define SYSCLKDIV_2 (0x1 << 7) - -#define CLKSEL_GPT1 (0x1 << 0) - -#define EN_GPT1 (0x1 << 0) -#define EN_32KSYNC (0x1 << 2) - -#define ST_WDT2 (0x1 << 5) - -#define RESETDONE (0x1 << 0) - #define TCLR_ST (0x1 << 0) #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h index 55e9de6041..5f2b0f9f5d 100644 --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -28,11 +28,14 @@ #include <asm/types.h> +#define FSC (1 << 19) +#define SSC (0 << 19) + #define IEN (1 << 18) #define IDIS (0 << 18) -#define PTU (3 << 16) -#define PTD (1 << 16) +#define PTU (1 << 17) +#define PTD (0 << 17) #define PEN (1 << 16) #define PDIS (0 << 16) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 04af227e02..5e6d82e51f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -44,16 +44,15 @@ #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END -/* CONTROL */ -#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) -#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800) -#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800) - -/* LPDDR2 IO regs. To be verified */ -#define LPDDR2_IO_REGS_BASE 0x4A100638 - -/* CONTROL_ID_CODE */ -#define CONTROL_ID_CODE (CTRL_BASE + 0x204) +/* CONTROL ID CODE */ +#define CONTROL_CORE_ID_CODE 0x4A002204 +#define CONTROL_WKUP_ID_CODE 0x4AE0C204 + +#ifdef CONFIG_DRA7XX +#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE +#else +#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE +#endif /* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F @@ -62,11 +61,6 @@ #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F -/* STD_FUSE_PROD_ID_1 */ -#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) -#define PROD_ID_1_SILICON_TYPE_SHIFT 16 -#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16) - /* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) @@ -80,15 +74,9 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000) - /* GPMC */ #define OMAP54XX_GPMC_BASE 0x50000000 -/* SYSTEM CONTROL MODULE */ -#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000 - /* * Hardware Register Details */ @@ -118,9 +106,9 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 +#define SDCARD_BIAS_PWRDNZ (1 << 27) #define SDCARD_PWRDNZ (1 << 26) #define SDCARD_BIAS_HIZ_MODE (1 << 25) -#define SDCARD_BIAS_PWRDNZ (1 << 22) #define SDCARD_PBIASLITE_VMODE (1 << 21) #ifndef __ASSEMBLY__ @@ -181,27 +169,18 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ +#ifdef CONFIG_DRA7XX +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ +#else #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ +#endif #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START + /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 -/* Silicon revisions */ -#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF -#define OMAP4430_ES1_0 0x44300100 -#define OMAP4430_ES2_0 0x44300200 -#define OMAP4430_ES2_1 0x44300210 -#define OMAP4430_ES2_2 0x44300220 -#define OMAP4430_ES2_3 0x44300230 -#define OMAP4460_ES1_0 0x44600100 -#define OMAP4460_ES1_1 0x44600110 - /* CONTROL_SRCOMP_XXX_SIDE */ #define OVERRIDE_XS_SHIFT 30 #define OVERRIDE_XS_MASK (1 << 30) @@ -216,6 +195,19 @@ struct s32ktimer { #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 50 +#define OMAP_ABB_CLOCK_CYCLES 16 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) + +/* ABB efuse masks */ +#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) +#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) +#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) +#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) + #ifndef __ASSEMBLY__ struct srcomp_params { s8 divide_factor; @@ -230,6 +222,7 @@ struct ctrl_ioregs { u32 ctrl_ddrio_1; u32 ctrl_ddrio_2; u32 ctrl_emif_sdram_config_ext; + u32 ctrl_ddr_ctrl_ext_0; }; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 4d99db9b7d..0bb59d869b 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -23,9 +23,9 @@ #include <asm/arch/omap.h> #include <asm/io.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <asm/omap_common.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; @@ -61,7 +61,8 @@ u32 cortex_rev(void); void save_omap_boot_params(void); void init_omap_revision(void); void do_io_settings(void); -void omap_vc_init(u16 speed_khz); +void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h new file mode 100644 index 0000000000..04e418cf84 --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -0,0 +1,39 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#include <common.h> + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_BUS_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_FEC_CLK, +}; + +void enable_ocotp_clk(unsigned char enable); +unsigned int mxc_get_clock(enum mxc_clock clk); + +#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h new file mode 100644 index 0000000000..e3f703dc83 --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -0,0 +1,225 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__ +#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__ + +#ifndef __ASSEMBLY__ + +/* Clock Controller Module (CCM) */ +struct ccm_reg { + u32 ccr; + u32 csr; + u32 ccsr; + u32 cacrr; + u32 cscmr1; + u32 cscdr1; + u32 cscdr2; + u32 cscdr3; + u32 cscmr2; + u32 cscdr4; + u32 ctor; + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; + u32 cgpr; + u32 ccgr0; + u32 ccgr1; + u32 ccgr2; + u32 ccgr3; + u32 ccgr4; + u32 ccgr5; + u32 ccgr6; + u32 ccgr7; + u32 ccgr8; + u32 ccgr9; + u32 ccgr10; + u32 ccgr11; + u32 cmeor0; + u32 cmeor1; + u32 cmeor2; + u32 cmeor3; + u32 cmeor4; + u32 cmeor5; + u32 cppdsr; + u32 ccowr; + u32 ccpgr0; + u32 ccpgr1; + u32 ccpgr2; + u32 ccpgr3; +}; + +/* Analog components control digital interface (ANADIG) */ +struct anadig_reg { + u32 pll3_ctrl; + u32 resv0[3]; + u32 pll7_ctrl; + u32 resv1[3]; + u32 pll2_ctrl; + u32 resv2[3]; + u32 pll2_ss; + u32 resv3[3]; + u32 pll2_num; + u32 resv4[3]; + u32 pll2_denom; + u32 resv5[3]; + u32 pll4_ctrl; + u32 resv6[3]; + u32 pll4_num; + u32 resv7[3]; + u32 pll4_denom; + u32 pll6_ctrl; + u32 resv8[3]; + u32 pll6_num; + u32 resv9[3]; + u32 pll6_denom; + u32 resv10[3]; + u32 pll5_ctrl; + u32 resv11[3]; + u32 pll3_pfd; + u32 resv12[3]; + u32 pll2_pfd; + u32 resv13[3]; + u32 reg_1p1; + u32 resv14[3]; + u32 reg_3p0; + u32 resv15[3]; + u32 reg_2p5; + u32 resv16[7]; + u32 ana_misc0; + u32 resv17[3]; + u32 ana_misc1; + u32 resv18[63]; + u32 anadig_digprog; + u32 resv19[3]; + u32 pll1_ctrl; + u32 resv20[3]; + u32 pll1_ss; + u32 resv21[3]; + u32 pll1_num; + u32 resv22[3]; + u32 pll1_denom; + u32 resv23[3]; + u32 pll1_pdf; + u32 resv24[3]; + u32 pll_lock; +}; +#endif + +#define CCM_CCR_FIRC_EN (1 << 16) +#define CCM_CCR_OSCNT_MASK 0xff +#define CCM_CCR_OSCNT(v) ((v) & 0xff) + +#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 +#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) +#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) + +#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 +#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) +#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) + +#define CCM_CCSR_PLL2_PFD4_EN (1 << 15) +#define CCM_CCSR_PLL2_PFD3_EN (1 << 14) +#define CCM_CCSR_PLL2_PFD2_EN (1 << 13) +#define CCM_CCSR_PLL2_PFD1_EN (1 << 12) +#define CCM_CCSR_PLL1_PFD4_EN (1 << 11) +#define CCM_CCSR_PLL1_PFD3_EN (1 << 10) +#define CCM_CCSR_PLL1_PFD2_EN (1 << 9) +#define CCM_CCSR_PLL1_PFD1_EN (1 << 8) + +#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) +#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) + +#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 +#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 +#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) + +#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 +#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) +#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) +#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 +#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) +#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) +#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 +#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 +#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) + +#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 +#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) +#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) + +#define CCM_CSCDR1_RMII_CLK_EN (1 << 24) + +#define CCM_CSCDR2_ESDHC1_EN (1 << 29) +#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 +#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) +#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) + +#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 +#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) +#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) + +#define CCM_REG_CTRL_MASK 0xffffffff +#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) +#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) +#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) +#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) +#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) +#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) +#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) +#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) +#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 +#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) +#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) +#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) +#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) +#define CCM_CCGR9_FEC0_CTRL_MASK 0x3 +#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) + +#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL2_CTRL_DIV_SELECT 1 +#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL1_CTRL_DIV_SELECT 1 + +#define FASE_CLK_FREQ 24000000 +#define SLOW_CLK_FREQ 32000 +#define PLL1_PFD1_FREQ 500000000 +#define PLL1_PFD2_FREQ 452000000 +#define PLL1_PFD3_FREQ 396000000 +#define PLL1_PFD4_FREQ 528000000 +#define PLL1_MAIN_FREQ 528000000 +#define PLL2_PFD1_FREQ 500000000 +#define PLL2_PFD2_FREQ 396000000 +#define PLL2_PFD3_FREQ 339000000 +#define PLL2_PFD4_FREQ 413000000 +#define PLL2_MAIN_FREQ 528000000 +#define PLL3_MAIN_FREQ 480000000 +#define PLL3_PFD3_FREQ 298000000 +#define PLL5_MAIN_FREQ 500000000 + +#define ENET_EXTERNAL_CLK 50000000 +#define AUDIO_EXTERNAL_CLK 24576000 + +#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h new file mode 100644 index 0000000000..c9df32a21d --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -0,0 +1,419 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IMX_REGS_H__ +#define __ASM_ARCH_IMX_REGS_H__ + +#define ARCH_MXC + +#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */ +#define IRAM_SIZE 0x00080000 /* 512 KB */ + +#define AIPS0_BASE_ADDR 0x40000000 +#define AIPS1_BASE_ADDR 0x40080000 + +/* AIPS 0 */ +#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) +#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800) +#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) +#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000) +#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000) +#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000) +#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000) +#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) +#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) +#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000) +#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) +#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000) +#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000) +#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) +#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000) +#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000) +#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000) +#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000) +#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000) +#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000) +#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000) +#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000) +#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000) +#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000) +#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000) +#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000) +#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000) +#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000) +#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000) +#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000) +#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000) +#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000) +#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) +#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) +#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) +#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000) +#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) +#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) +#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) +#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) +#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000) +#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000) +#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000) +#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000) +#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) +#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000) +#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) +#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) +#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) +#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) +#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) +#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) +#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) +#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) +#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000) +#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) +#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000) +#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000) +#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) +#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) +#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) +#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) + +/* AIPS 1 */ +#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) +#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000) +#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) +#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) +#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) + +/* MUX mode and PAD ctrl are in one register */ +#define CONFIG_IOMUX_SHARE_CONF_REG + +#define FEC_QUIRK_ENET_MAC + +/* MSCM interrupt rounter */ +#define MSCM_IRSPRC_CP0_EN 1 +#define MSCM_IRSPRC_NUM 112 + +/* DDRMC */ +#define DDRMC_PHY_DQ_TIMING 0x00002613 +#define DDRMC_PHY_DQS_TIMING 0x00002615 +#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_MASTER_CTRL 0x0001012a +#define DDRMC_PHY_SLAVE_CTRL 0x00012020 + +#define DDRMC_PHY50_DDR3_MODE (1 << 12) +#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) + +#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8) +#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8) +#define DDRMC_CR00_START 1 +#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff) +#define DDRMC_CR10_TRST_PWRON(v) (v) +#define DDRMC_CR11_CKE_INACTIVE(v) (v) +#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8) +#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f) +#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24) +#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16) +#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8) +#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7) +#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24) +#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16) +#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8) +#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff) +#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24) +#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16) +#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8) +#define DDRMC_CR17_TMOD(v) ((v) & 0xff) +#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8) +#define DDRMC_CR18_TCKE(v) ((v) & 0x7) +#define DDRMC_CR20_AP_EN (1 << 24) +#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16) +#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8) +#define DDRMC_CR21_CCMAP_EN 1 +#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) +#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) +#define DDRMC_CR23_TDLL(v) ((v) & 0xff) +#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) +#define DDRMC_CR25_TREF_EN (1 << 16) +#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) +#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff) +#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff) +#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff) +#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff) +#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16) +#define DDRMC_CR31_TXSR(v) ((v) & 0xffff) +#define DDRMC_CR33_EN_QK_SREF (1 << 16) +#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) +#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) +#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) +#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) +#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) +#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) +#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1 +#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16) +#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff) +#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16) +#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff) +#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) +#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) +#define DDRMC_CR70_REF_PER_ZQ(v) (v) +#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) +#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) +#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) +#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) +#define DDRMC_CR74_BANKSPLT_EN (1 << 24) +#define DDRMC_CR74_ADDR_CMP_EN (1 << 16) +#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8) +#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff) +#define DDRMC_CR75_RW_PG_EN (1 << 24) +#define DDRMC_CR75_RW_EN (1 << 16) +#define DDRMC_CR75_PRI_EN (1 << 8) +#define DDRMC_CR75_PLEN 1 +#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24) +#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16) +#define DDRMC_CR76_W2R_SPLT_EN (1 << 8) +#define DDRMC_CR76_CS_EN 1 +#define DDRMC_CR77_CS_MAP (1 << 24) +#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) +#define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) +#define DDRMC_CR79_CTLUPD_AREF (1 << 24) +#define DDRMC_CR82_INT_MASK 0x1fffffff +#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) +#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) +#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) +#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) +#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) +#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) +#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) +#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) +#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) +#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) +#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) +#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16) +#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24) +#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16) +#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8) +#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24) +#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16) +#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) +#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) +#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) +#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) +#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) +#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) +#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) +#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) +#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) +#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) +#define DDRMC_CR155_AXI0_AWCACHE (1 << 10) +#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) +#define DDRMC_CR158_TWR(v) ((v) & 0x3f) + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 sbmr1; + u32 srsr; + u32 secr; + u32 gpsr; + u32 sicr; + u32 simr; + u32 sbmr2; + u32 gpr0; + u32 gpr1; + u32 gpr2; + u32 gpr3; + u32 gpr4; + u32 hab0; + u32 hab1; + u32 hab2; + u32 hab3; + u32 hab4; + u32 hab5; + u32 misc0; + u32 misc1; + u32 misc2; + u32 misc3; +}; + +/* Periodic Interrupt Timer (PIT) */ +struct pit_reg { + u32 mcr; + u32 recv0[55]; + u32 ltmr64h; + u32 ltmr64l; + u32 recv1[6]; + u32 ldval0; + u32 cval0; + u32 tctrl0; + u32 tflg0; + u32 ldval1; + u32 cval1; + u32 tctrl1; + u32 tflg1; + u32 ldval2; + u32 cval2; + u32 tctrl2; + u32 tflg2; + u32 ldval3; + u32 cval3; + u32 tctrl3; + u32 tflg3; + u32 ldval4; + u32 cval4; + u32 tctrl4; + u32 tflg4; + u32 ldval5; + u32 cval5; + u32 tctrl5; + u32 tflg5; + u32 ldval6; + u32 cval6; + u32 tctrl6; + u32 tflg6; + u32 ldval7; + u32 cval7; + u32 tctrl7; + u32 tflg7; +}; + +/* Watchdog Timer (WDOG) */ +struct wdog_regs { + u16 wcr; + u16 wsr; + u16 wrsr; + u16 wicr; + u16 wmcr; +}; + +/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */ +struct ddrmr_regs { + u32 cr[162]; + u32 rsvd[94]; + u32 phy[53]; +}; + +/* On-Chip One Time Programmable Controller (OCOTP) */ +struct ocotp_regs { + u32 ctrl; + u32 ctrl_set; + u32 ctrl_clr; + u32 ctrl_tog; + u32 timing; + u32 rsvd0[3]; + u32 data; + u32 rsvd1[3]; + u32 read_ctrl; + u32 rsvd2[3]; + u32 read_fuse_data; + u32 rsvd3[7]; + u32 scs; + u32 scs_set; + u32 scs_clr; + u32 scs_tog; + u32 crc_addr; + u32 rsvd4[3]; + u32 crc_value; + u32 rsvd5[3]; + u32 version; + u32 rsvd6[0xdb]; + + struct fuse_bank { + u32 fuse_regs[0x20]; + } bank[16]; +}; + +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[3]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[0x17]; +}; + +struct fuse_bank4_regs { + u32 sjc_resp0; + u32 rsvd0[3]; + u32 sjc_resp1; + u32 rsvd1[3]; + u32 mac_addr0; + u32 rsvd2[3]; + u32 mac_addr1; + u32 rsvd3[3]; + u32 mac_addr2; + u32 rsvd4[3]; + u32 mac_addr3; + u32 rsvd5[3]; + u32 gp1; + u32 rsvd6[3]; + u32 gp2; + u32 rsvd7[3]; +}; + +/* UART */ +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; + +/* MSCM Interrupt Router */ +struct mscm_ir { + u32 ircp0ir; + u32 ircp1ir; + u32 rsvd1[6]; + u32 ircpgir; + u32 rsvd2[23]; + u16 irsprc[112]; + u16 rsvd3[848]; +}; + +#endif /* __ASSEMBLER__*/ + +#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h new file mode 100644 index 0000000000..1c728fa6b7 --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -0,0 +1,101 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IOMUX_VF610_H__ +#define __IOMUX_VF610_H__ + +#include <asm/imx-common/iomux-v3.h> + +/* Pad control groupings */ +#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm + +enum { + VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), +}; + +#endif /* __IOMUX_VF610_H__ */ diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 5f11d7b72e..1b94a99c54 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -581,7 +581,7 @@ (0xFF << EMIF_SYS_ADDR_SHIFT)) #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 -#define EMIF_EXT_PHY_CTRL_CONST_REG 0x13 +#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14 /* Reg mapping structure */ struct emif_reg_struct { @@ -855,13 +855,10 @@ struct dmm_lisa_map_regs { #define DPD_ENABLE 1 /* Maximum delay before Low Power Modes */ -#ifndef CONFIG_OMAP54XX -#define REG_CS_TIM 0xF -#else #define REG_CS_TIM 0x0 -#endif -#define REG_SR_TIM 0xF -#define REG_PD_TIM 0xF +#define REG_SR_TIM 0x0 +#define REG_PD_TIM 0x0 + /* EMIF_PWR_MGMT_CTRL register */ #define EMIF_PWR_MGMT_CTRL (\ @@ -1113,6 +1110,7 @@ struct emif_regs { u32 freq; u32 sdram_config_init; u32 sdram_config; + u32 sdram_config2; u32 ref_ctrl; u32 sdram_tim1; u32 sdram_tim2; diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 0b4e76333e..ebf54cf187 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -121,6 +121,24 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 << 3) #define PAD_CTL_DSE_34ohm (7 << 3) +#elif defined(CONFIG_VF610) + +#define PAD_MUX_MODE_SHIFT 20 + +#define PAD_CTL_SPEED_MED (1 << 12) +#define PAD_CTL_SPEED_HIGH (3 << 12) + +#define PAD_CTL_DSE_50ohm (3 << 6) +#define PAD_CTL_DSE_25ohm (6 << 6) +#define PAD_CTL_DSE_20ohm (7 << 6) + +#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PKE (1 << 3) +#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) + +#define PAD_CTL_OBE_IBE_ENABLE (3 << 0) + #else #define PAD_CTL_DVS (1 << 13) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index baeef4e5bb..0dbe81b59c 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -29,7 +29,7 @@ #include <common.h> -#define NUM_SYS_CLKS 8 +#define NUM_SYS_CLKS 7 struct prcm_regs { /* cm1.ckgen */ @@ -242,6 +242,8 @@ struct prcm_regs { u32 cm_l3init_fsusb_clkctrl; u32 cm_l3init_ocp2scp1_clkctrl; + u32 prm_irqstatus_mpu_2; + /* cm2.l4per */ u32 cm_l4per_clkstctrl; u32 cm_l4per_dynamicdep; @@ -301,6 +303,7 @@ struct prcm_regs { /* l4 wkup regs */ u32 cm_abe_pll_ref_clksel; u32 cm_sys_clksel; + u32 cm_abe_pll_sys_clksel; u32 cm_wkup_clkstctrl; u32 cm_wkup_l4wkup_clkctrl; u32 cm_wkup_wdtimer1_clkctrl; @@ -328,6 +331,8 @@ struct prcm_regs { u32 prm_sldo_mpu_ctrl; u32 prm_sldo_mm_setup; u32 prm_sldo_mm_ctrl; + u32 prm_abbldo_mpu_setup; + u32 prm_abbldo_mpu_ctrl; u32 cm_div_m4_dpll_core; u32 cm_div_m5_dpll_core; @@ -346,10 +351,15 @@ struct prcm_regs { u32 cm_l3init_usbphy_clkctrl; u32 cm_l4per_mcbsp4_clkctrl; u32 prm_vc_cfg_channel; + + /* SCRM stuff, used by some boards */ + u32 scrm_auxclk0; + u32 scrm_auxclk1; }; struct omap_sys_ctrl_regs { u32 control_status; + u32 control_std_fuse_opp_vdd_mpu_2; u32 control_core_mmr_lock1; u32 control_core_mmr_lock2; u32 control_core_mmr_lock3; @@ -362,6 +372,7 @@ struct omap_sys_ctrl_regs { u32 control_ldosram_iva_voltage_ctrl; u32 control_ldosram_mpu_voltage_ctrl; u32 control_ldosram_core_voltage_ctrl; + u32 control_usbotghs_ctrl; u32 control_padconf_core_base; u32 control_paconf_global; u32 control_paconf_mode; @@ -394,6 +405,7 @@ struct omap_sys_ctrl_regs { u32 control_ddrio_0; u32 control_ddrio_1; u32 control_ddrio_2; + u32 control_ddr_control_ext_0; u32 control_lpddr2io1_0; u32 control_lpddr2io1_1; u32 control_lpddr2io1_2; @@ -419,6 +431,7 @@ struct omap_sys_ctrl_regs { u32 control_port_emif2_sdram_config; u32 control_emif1_sdram_config_ext; u32 control_emif2_sdram_config_ext; + u32 control_wkup_ldovbb_mpu_voltage_ctrl; u32 control_smart1nopmio_padconf_0; u32 control_smart1nopmio_padconf_1; u32 control_padconf_mode; @@ -494,11 +507,25 @@ struct pmic_data { u32 start_code; unsigned gpio; int gpio_en; + u32 i2c_slave_addr; + void (*pmic_bus_init)(void); + int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); +}; + +/** + * struct volts_efuse_data - efuse definition for voltage + * @reg: register address for efuse + * @reg_bits: Number of bits in a register address, mandatory. + */ +struct volts_efuse_data { + u32 reg; + u8 reg_bits; }; struct volts { u32 value; u32 addr; + struct volts_efuse_data efuse; struct pmic_data *pmic; }; @@ -506,6 +533,9 @@ struct vcores_data { struct volts mpu; struct volts core; struct volts mm; + struct volts gpu; + struct volts eve; + struct volts iva; }; extern struct prcm_regs const **prcm; @@ -545,9 +575,9 @@ void enable_non_essential_clocks(void); void scale_vcores(struct vcores_data const *); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); - -/* Max value for DPLL multiplier M */ -#define OMAP_DPLL_MAX_N 127 +void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, + u32 txdone, u32 txdone_mask, u32 opp); +s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); /* HW Init Context */ #define OMAP_INIT_CONTEXT_SPL 0 @@ -555,11 +585,32 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 +/* ABB */ +#define OMAP_ABB_NOMINAL_OPP 0 +#define OMAP_ABB_FAST_OPP 1 +#define OMAP_ABB_SLOW_OPP 3 +#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0) +#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1) +#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2) +#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6) +#define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0) +#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2) +#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1) +#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8) + static inline u32 omap_revision(void) { extern u32 *const omap_si_rev; return *omap_si_rev; } + +#define OMAP54xx 0x54000000 + +static inline u8 is_omap54xx(void) +{ + extern u32 *const omap_si_rev; + return ((*omap_si_rev & 0xFF000000) == OMAP54xx); +} #endif /* diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index b545fb79bc..8b1c8ed4bf 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -27,7 +27,7 @@ void __flush_cache(unsigned long start, unsigned long size) { -#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136) +#if defined(CONFIG_ARM1136) void arm1136_cache_flush(void); arm1136_cache_flush(); diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a9657d190f..a5bffb8da6 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -97,13 +97,13 @@ ENTRY(_main) * 'here' but relocated. */ - ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */ + ldr sp, [r8, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr r8, [r8, #GD_BD] /* r8 = gd->bd */ sub r8, r8, #GD_SIZE /* new GD is below bd */ adr lr, here - ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */ + ldr r0, [r8, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ add lr, lr, r0 ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */ b relocate_code diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index e155556ce2..8f0f9b8de2 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -336,7 +336,6 @@ iomux_v3_cfg_t const ecspi1_pads[] = { void setup_spi(void) { - gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); } diff --git a/board/congatec/cgtqmx6eval/Makefile b/board/congatec/cgtqmx6eval/Makefile new file mode 100644 index 0000000000..ac16c1fe3f --- /dev/null +++ b/board/congatec/cgtqmx6eval/Makefile @@ -0,0 +1,42 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2013 Adeneo Embedded <www.adeneo-embedded.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := cgtqmx6eval.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README new file mode 100644 index 0000000000..bbf0f75a4d --- /dev/null +++ b/board/congatec/cgtqmx6eval/README @@ -0,0 +1,29 @@ +U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board with +qmx6 quad module. + +This file contains information for the port of U-Boot to the Congatec +Conga-QEVAl Evaluation Carrier board with qmx6 quad module. + +1. Boot source, boot from SD card +--------------------------------- + +This version of u-boot works only on the SD card. By default, the +Congatec board can boot only from the SPI-NOR. +But, with the u-boot version provided with the board you can write boot +registers to force the board to reboot and boot from the SD slot. If +"bmode" command is not available from your pre-installed u-boot, these +instruction will produce the same effect: + +conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850 +conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000 +conga-QMX6 U-Boot > reset +resetting ... + +The the board will reboot and, if you have written your SD correctly +the board will use u-boot that live into the SD + +To copy the resulting u-boot.imx to the SD card: + + dd if=u-boot.imx of=/dev/xxx bs=512 seek=2 + +Note: Replace xxx with the device representing the SD card in your system. diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c new file mode 100644 index 0000000000..f70f674b21 --- /dev/null +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Based on mx6qsabrelite.c file + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Leo Sartre, <lsartre@adeneo-embedded.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <mmc.h> +#include <fsl_esdhc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC2_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + gpio_direction_input(IMX_GPIO_NR(1, 4)); + ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); + break; + case USDHC4_BASE_ADDR: + gpio_direction_input(IMX_GPIO_NR(2, 6)); + ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); + break; + default: + printf("Bad USDHC interface\n"); + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + + status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) | + fsl_esdhc_initialize(bis, &usdhc_cfg[1]); + + return status; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Conga-QEVAL QMX6 Quad\n"); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index c45c94b4c0..a4e9254157 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -39,135 +39,43 @@ #include <asm/arch/hardware.h> #include <asm/arch/emif_defs.h> #include <asm/arch/emac_defs.h> +#include <asm/arch/pinmux_defs.h> #include <asm/io.h> #include <nand.h> #include <asm/arch/nand_defs.h> #include <asm/arch/davinci_misc.h> -DECLARE_GLOBAL_DATA_PTR; - -/* SPI0 pin muxer settings */ -static const struct pinmux_config spi0_pins[] = { - { pinmux(7), 1, 3 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(7), 1, 6 }, - { pinmux(7), 1, 7 } -}; - -/* EMIF-A bus pins for 8-bit NAND support on CS3 */ -static const struct pinmux_config emifa_nand_pins[] = { - { pinmux(13), 1, 6 }, - { pinmux(13), 1, 7 }, - { pinmux(14), 1, 0 }, - { pinmux(14), 1, 1 }, - { pinmux(14), 1, 2 }, - { pinmux(14), 1, 3 }, - { pinmux(14), 1, 4 }, - { pinmux(14), 1, 5 }, - { pinmux(15), 1, 7 }, - { pinmux(16), 1, 0 }, - { pinmux(18), 1, 1 }, - { pinmux(18), 1, 4 }, - { pinmux(18), 1, 5 }, -}; - -/* EMAC PHY interface pins */ -static const struct pinmux_config emac_pins[] = { - { pinmux(9), 0, 5 }, - { pinmux(10), 2, 1 }, - { pinmux(10), 2, 2 }, - { pinmux(10), 2, 3 }, - { pinmux(10), 2, 4 }, - { pinmux(10), 2, 5 }, - { pinmux(10), 2, 6 }, - { pinmux(10), 2, 7 }, - { pinmux(11), 2, 0 }, - { pinmux(11), 2, 1 }, -}; - -/* UART pin muxer settings */ -static const struct pinmux_config uart_pins[] = { - { pinmux(8), 2, 7 }, - { pinmux(9), 2, 0 } -}; - -/* I2C pin muxer settings */ -static const struct pinmux_config i2c_pins[] = { - { pinmux(8), 2, 3 }, - { pinmux(8), 2, 4 } -}; - -#ifdef CONFIG_USE_NAND -/* NAND pin muxer settings */ -const struct pinmux_config aemif_pins[] = { - { pinmux(13), 1, 6 }, - { pinmux(13), 1, 7 }, - { pinmux(14), 1, 0 }, - { pinmux(14), 1, 1 }, - { pinmux(14), 1, 2 }, - { pinmux(14), 1, 3 }, - { pinmux(14), 1, 4 }, - { pinmux(14), 1, 5 }, - { pinmux(14), 1, 6 }, - { pinmux(14), 1, 7 }, - { pinmux(15), 1, 0 }, - { pinmux(15), 1, 1 }, - { pinmux(15), 1, 2 }, - { pinmux(15), 1, 3 }, - { pinmux(15), 1, 4 }, - { pinmux(15), 1, 5 }, - { pinmux(15), 1, 6 }, - { pinmux(15), 1, 7 }, - { pinmux(16), 1, 0 }, - { pinmux(16), 1, 1 }, - { pinmux(16), 1, 2 }, - { pinmux(16), 1, 3 }, - { pinmux(16), 1, 4 }, - { pinmux(16), 1, 5 }, - { pinmux(16), 1, 6 }, - { pinmux(16), 1, 7 }, - { pinmux(17), 1, 0 }, - { pinmux(17), 1, 1 }, - { pinmux(17), 1, 2 }, - { pinmux(17), 1, 3 }, - { pinmux(17), 1, 4 }, - { pinmux(17), 1, 5 }, - { pinmux(17), 1, 6 }, - { pinmux(17), 1, 7 }, - { pinmux(18), 1, 0 }, - { pinmux(18), 1, 1 }, - { pinmux(18), 1, 2 }, - { pinmux(18), 1, 3 }, - { pinmux(18), 1, 4 }, - { pinmux(18), 1, 5 }, - { pinmux(18), 1, 6 }, - { pinmux(18), 1, 7 }, - { pinmux(10), 1, 0 } -}; +#ifdef CONFIG_DAVINCI_MMC +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> #endif - -/* USB0_DRVVBUS pin muxer settings */ -static const struct pinmux_config usb_pins[] = { - { pinmux(9), 1, 1 } -}; +DECLARE_GLOBAL_DATA_PTR; static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_SPI_FLASH - PINMUX_ITEM(spi0_pins), + PINMUX_ITEM(spi0_pins_base), + PINMUX_ITEM(spi0_pins_scs0), + PINMUX_ITEM(spi0_pins_ena), #endif - PINMUX_ITEM(uart_pins), - PINMUX_ITEM(i2c_pins), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(i2c0_pins), #ifdef CONFIG_USB_DA8XX PINMUX_ITEM(usb_pins), #endif #ifdef CONFIG_USE_NAND - PINMUX_ITEM(emifa_nand_pins), - PINMUX_ITEM(aemif_pins), + PINMUX_ITEM(emifa_pins), + PINMUX_ITEM(emifa_pins_cs0), + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_cs3), #endif #if defined(CONFIG_DRIVER_TI_EMAC) - PINMUX_ITEM(emac_pins), + PINMUX_ITEM(emac_pins_rmii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(emac_pins_rmii_clk_source), +#endif +#ifdef CONFIG_DAVINCI_MMC + PINMUX_ITEM(mmc0_pins_8bit) #endif }; @@ -177,8 +85,31 @@ static const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_EMAC }, /* image download */ { DAVINCI_LPSC_UART2 }, /* console */ { DAVINCI_LPSC_GPIO }, +#ifdef CONFIG_DAVINCI_MMC + { DAVINCI_LPSC_MMC_SD }, +#endif + +}; + +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd0 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .host_caps = MMC_MODE_8BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, }; +int board_mmc_init(bd_t *bis) +{ + mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); + + printf("%x\n", mmc_sd0.input_clk); + + /* Add slot-0 to mmc subsystem */ + return davinci_mmc_init(bis, &mmc_sd0); +} +#endif + int board_init(void) { #ifndef CONFIG_USE_IRQ diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c index 41ba303ec4..d25e2b37ce 100644 --- a/board/freescale/mx23evk/mx23evk.c +++ b/board/freescale/mx23evk/mx23evk.c @@ -43,6 +43,12 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* Power on LCD */ + gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1); + + /* Set contrast to maximum */ + gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); + return 0; } diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c index 6be8c8d9d0..fd71f7dc1b 100644 --- a/board/freescale/mx23evk/spl_boot.c +++ b/board/freescale/mx23evk/spl_boot.c @@ -27,6 +27,7 @@ #define MUX_CONFIG_SSP1 (MXS_PAD_8MA | MXS_PAD_PULLUP) #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_LCD (MXS_PAD_4MA | MXS_PAD_NOPULL) const iomux_cfg_t iomux_setup[] = { /* DUART */ @@ -96,6 +97,37 @@ const iomux_cfg_t iomux_setup[] = { /* Slot Power Enable */ MX23_PAD_PWM3__GPIO_1_29 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* LCD */ + MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD, + MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */ + MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */ }; #define HW_DRAM_CTL14 (0x38 >> 2) diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index ae6eda343e..beae0e66e2 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -30,6 +30,7 @@ #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) const iomux_cfg_t iomux_setup[] = { /* DUART */ @@ -162,6 +163,38 @@ const iomux_cfg_t iomux_setup[] = { /* I2C */ MX28_PAD_I2C0_SCL__I2C0_SCL, MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* LCD */ + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */ + MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */ }; #define HW_DRAM_CTL29 (0x74 >> 2) diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index de7231bd10..4edd9f4193 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -59,6 +59,12 @@ int board_early_init_f(void) gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1); #endif + /* Power on LCD */ + gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1); + + /* Set contrast to maximum */ + gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1); + return 0; } diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index bfe4868e8a..2a6e3a9192 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -26,12 +26,14 @@ #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/boot_mode.h> #include <mmc.h> #include <fsl_esdhc.h> #include <miiphy.h> #include <netdev.h> #include <asm/arch/sys_proto.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,6 +48,12 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -76,6 +84,45 @@ iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; +/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* + * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, + * Compass Sensor, Accelerometer, Res Touch + */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +iomux_v3_cfg_t const i2c3_pads[] = { + MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const port_exp[] = { + MX6_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); @@ -216,6 +263,16 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */ + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + /* I2C 3 Steer */ + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + gpio_direction_output(IMX_GPIO_NR(1, 15), 1); + imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp)); + return 0; } diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 8ce054e428..862bc3099d 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -308,7 +308,6 @@ iomux_v3_cfg_t const ecspi1_pads[] = { void setup_spi(void) { - gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); } diff --git a/board/freescale/vf610twr/Makefile b/board/freescale/vf610twr/Makefile new file mode 100644 index 0000000000..74162281ae --- /dev/null +++ b/board/freescale/vf610twr/Makefile @@ -0,0 +1,39 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg new file mode 100644 index 0000000000..b00d4c1cd3 --- /dev/null +++ b/board/freescale/vf610twr/imximage.cfg @@ -0,0 +1,33 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include <asm/imx-common/imximage.cfg> + +/* image version */ +IMAGE_VERSION 2 + +/* Boot Offset 0x400, valid for both SD and NAND boot */ +BOOT_OFFSET FLASH_OFFSET_STANDARD diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c new file mode 100644 index 0000000000..f14df8b6e1 --- /dev/null +++ b/board/freescale/vf610twr/vf610twr.c @@ -0,0 +1,407 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-vf610.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) + +#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) + +void setup_iomux_ddr(void) +{ + static const iomux_v3_cfg_t ddr_pads[] = { + VF610_PAD_DDR_A15__DDR_A_15, + VF610_PAD_DDR_A15__DDR_A_15, + VF610_PAD_DDR_A14__DDR_A_14, + VF610_PAD_DDR_A13__DDR_A_13, + VF610_PAD_DDR_A12__DDR_A_12, + VF610_PAD_DDR_A11__DDR_A_11, + VF610_PAD_DDR_A10__DDR_A_10, + VF610_PAD_DDR_A9__DDR_A_9, + VF610_PAD_DDR_A8__DDR_A_8, + VF610_PAD_DDR_A7__DDR_A_7, + VF610_PAD_DDR_A6__DDR_A_6, + VF610_PAD_DDR_A5__DDR_A_5, + VF610_PAD_DDR_A4__DDR_A_4, + VF610_PAD_DDR_A3__DDR_A_3, + VF610_PAD_DDR_A2__DDR_A_2, + VF610_PAD_DDR_A1__DDR_A_1, + VF610_PAD_DDR_BA2__DDR_BA_2, + VF610_PAD_DDR_BA1__DDR_BA_1, + VF610_PAD_DDR_BA0__DDR_BA_0, + VF610_PAD_DDR_CAS__DDR_CAS_B, + VF610_PAD_DDR_CKE__DDR_CKE_0, + VF610_PAD_DDR_CLK__DDR_CLK_0, + VF610_PAD_DDR_CS__DDR_CS_B_0, + VF610_PAD_DDR_D15__DDR_D_15, + VF610_PAD_DDR_D14__DDR_D_14, + VF610_PAD_DDR_D13__DDR_D_13, + VF610_PAD_DDR_D12__DDR_D_12, + VF610_PAD_DDR_D11__DDR_D_11, + VF610_PAD_DDR_D10__DDR_D_10, + VF610_PAD_DDR_D9__DDR_D_9, + VF610_PAD_DDR_D8__DDR_D_8, + VF610_PAD_DDR_D7__DDR_D_7, + VF610_PAD_DDR_D6__DDR_D_6, + VF610_PAD_DDR_D5__DDR_D_5, + VF610_PAD_DDR_D4__DDR_D_4, + VF610_PAD_DDR_D3__DDR_D_3, + VF610_PAD_DDR_D2__DDR_D_2, + VF610_PAD_DDR_D1__DDR_D_1, + VF610_PAD_DDR_D0__DDR_D_0, + VF610_PAD_DDR_DQM1__DDR_DQM_1, + VF610_PAD_DDR_DQM0__DDR_DQM_0, + VF610_PAD_DDR_DQS1__DDR_DQS_1, + VF610_PAD_DDR_DQS0__DDR_DQS_0, + VF610_PAD_DDR_RAS__DDR_RAS_B, + VF610_PAD_DDR_WE__DDR_WE_B, + VF610_PAD_DDR_ODT1__DDR_ODT_0, + VF610_PAD_DDR_ODT0__DDR_ODT_1, + }; + + imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); +} + +void ddr_phy_init(void) +{ + struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; + + writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); + writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); + writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); + writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]); + + writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); + writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); + writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]); + writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]); + + writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); + writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); + writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); + writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]); + + writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); + writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); + writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); + writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]); + + writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); + writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); + writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); + writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]); + + writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, + &ddrmr->phy[50]); +} + +void ddr_ctrl_init(void) +{ + struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; + + writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); + writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); + writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]); + + writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]); + writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]); + writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) | + DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]); + writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) | + DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]); + writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]); + writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12), + &ddrmr->cr[17]); + writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]); + + writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); + writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT | + DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); + + writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]); + writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); + writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]); + + writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); + writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); + writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]); + writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]); + + writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]); + writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]); + writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); + writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]); + + writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]); + writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | + DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); + + writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]); + writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056), + &ddrmr->cr[48]); + + writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]); + writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]); + writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); + + writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]); + writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]); + + writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | + DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); + writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | + DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255), + &ddrmr->cr[74]); + writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | + DDRMC_CR75_PLEN, &ddrmr->cr[75]); + writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | + DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]); + writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | + DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); + writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); + writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]); + + writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); + + writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0, + &ddrmr->cr[87]); + writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); + writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); + + writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); + writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]); + + writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]); + writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]); + writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]); + + writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), + &ddrmr->cr[117]); + writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), + &ddrmr->cr[118]); + + writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2), + &ddrmr->cr[120]); + writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2), + &ddrmr->cr[121]); + writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | + DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); + writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1), + &ddrmr->cr[123]); + writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]); + + writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]); + writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), + &ddrmr->cr[132]); + writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | + DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), + &ddrmr->cr[139]); + + writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | + DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]); + writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), + &ddrmr->cr[155]); + writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); + + ddr_phy_init(); + + writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); + + udelay(200); +} + +int dram_init(void) +{ + setup_iomux_ddr(); + + ddr_ctrl_init(); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t uart1_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static void setup_iomux_enet(void) +{ + static const iomux_v3_cfg_t enet0_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {ESDHC1_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* eSDHC1 is always present */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + static const iomux_v3_cfg_t esdhc1_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), + }; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + imx_iomux_v3_setup_multiple_pads( + esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +static void clock_init(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; + + clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, + CCM_CCGR0_UART1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, + CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, + CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | + CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | + CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, + CCM_CCGR3_ANADIG_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, + CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | + CCM_CCGR4_GPC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, + CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, + CCM_CCGR7_SDHC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, + CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); + + clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, + ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); + clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, + ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); + + clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, + CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); + clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, + CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | + CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | + CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | + CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | + CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | + CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); + clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, + CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | + CCM_CACRR_ARM_CLK_DIV(0)); + clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, + CCM_CSCMR1_ESDHC1_CLK_SEL(3)); + clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, + CCM_CSCDR1_RMII_CLK_EN); + clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, + CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0)); + clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, + CCM_CSCMR2_RMII_CLK_SEL(0)); +} + +static void mscm_init(void) +{ + struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; + int i; + + for (i = 0; i < MSCM_IRSPRC_NUM; i++) + writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + clock_init(); + mscm_init(); + + setup_iomux_uart(); + setup_iomux_enet(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: vf610twr\n"); + + return 0; +} diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 923461a390..7f0330dc03 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -28,7 +28,7 @@ #include <asm/gpio.h> #include <asm/omap_gpio.h> #include <asm/arch/dss.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include "errno.h" #include <i2c.h> #ifdef CONFIG_USB_EHCI diff --git a/board/ti/omap2420h4/Makefile b/board/icpdas/lp8x4x/Makefile index cddd7e6985..cbe6aa9ad4 100644 --- a/board/ti/omap2420h4/Makefile +++ b/board/icpdas/lp8x4x/Makefile @@ -1,9 +1,7 @@ # -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# ICPDAS LP-8x4x Support # -# See file CREDITS for list of people who contributed to this -# project. +# Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com> # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -25,15 +23,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := omap2420h4.o mem.o sys_info.o -SOBJS := lowlevel_init.o +COBJS := lp8x4x.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c new file mode 100644 index 0000000000..76f070056b --- /dev/null +++ b/board/icpdas/lp8x4x/lp8x4x.c @@ -0,0 +1,147 @@ +/* + * ICP DAS LP-8x4x Support + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * adapted from Voipac PXA270 Support by + * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/regs-mmc.h> +#include <asm/arch/pxa.h> +#include <netdev.h> +#include <serial.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ +int board_init(void) +{ + /* We have RAM, disable cache */ + dcache_disable(); + icache_disable(); + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int dram_init(void) +{ + pxa2xx_dram_init(); + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + +#ifdef CONFIG_CMD_USB +int usb_board_init(void) +{ + writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); + + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); + + while (readl(UHCHR) & UHCHR_FSBIR) + continue; /* required by checkpath.pl */ + + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); + + /* Clear any OTG Pin Hold */ + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); + + writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); + writel(readl(UHCRHDA) | 0x100, UHCRHDA); + + /* Set port power control mask bits, only 3 ports. */ + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); + + /* enable port 2 */ + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | + UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); + + return 0; +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); + udelay(11); + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); + + writel(readl(UHCCOMS) | 1, UHCCOMS); + udelay(10); + + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); + + return; +} +#endif + +#ifdef CONFIG_DRIVER_DM9000 +void lp8x4x_eth1_mac_init(void) +{ + u8 eth1addr[8]; + int i; + u8 reg; + + eth_getenv_enetaddr_by_index("eth", 1, eth1addr); + if (!is_valid_ether_addr(eth1addr)) + return; + + for (i = 0, reg = 0x10; i < 6; i++, reg++) { + writeb(reg, (u8 *)(DM9000_IO_2)); + writeb(eth1addr[i], (u8 *)(DM9000_DATA_2)); + } +} + +int board_eth_init(bd_t *bis) +{ + lp8x4x_eth1_mac_init(); + return dm9000_initialize(bis); +} +#endif diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index eda9199bbe..b9448873c8 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -160,7 +160,7 @@ int ethernet_present(void) } #endif -int initialize_unit_leds(void) +static int initialize_unit_leds(void) { /* * Init the unit LEDs per default they all are @@ -181,7 +181,7 @@ int initialize_unit_leds(void) } #if defined(CONFIG_BOOTCOUNT_LIMIT) -void set_bootcount_addr(void) +static void set_bootcount_addr(void) { uchar buf[32]; unsigned int bootcountaddr; diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index 8347cf9ce9..5c73098888 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -31,7 +31,7 @@ #include <asm/omap_gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/dss.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <i2c.h> #include <spartan3.h> #include <asm/gpio.h> diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 73bf853165..638cc4d68b 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -514,6 +514,7 @@ int board_eth_init(bd_t *bis) eth_setenv_enetaddr("ethaddr", mac_addr); } +#ifdef CONFIG_DRIVER_TI_CPSW if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = @@ -529,6 +530,7 @@ int board_eth_init(bd_t *bis) printf("Error %d registering CPSW switch\n", rv); else n += rv; +#endif /* * diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 04c95fd376..338a241ce7 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -29,19 +29,29 @@ #include <asm/arch/mux_dra7xx.h> const struct pad_conf_entry core_padconf_array_essential[] = { - {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */ - {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */ - {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */ - {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */ - {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */ - {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */ - {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */ - {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */ - {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */ - {UART1_TXD, (M0)}, /* UART1_TXD */ - {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */ - {UART1_RTSN, (M0)}, /* UART1_RTSN */ - {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */ - {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */ + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ + {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ + {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ + {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ + {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ }; #endif /* _MUX_DATA_DRA7XX_H_ */ diff --git a/board/ti/omap2420h4/config.mk b/board/ti/omap2420h4/config.mk deleted file mode 100644 index e5dff69a15..0000000000 --- a/board/ti/omap2420h4/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2004 -# Texas Instruments, <www.ti.com> -# -# TI H4 board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 -# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -#CONFIG_SYS_TEXT_BASE = 0x80e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -#CONFIG_SYS_TEXT_BASE = 0x40270000 - - -# Handy to get symbols to debug ROM version. -#CONFIG_SYS_TEXT_BASE = 0x0 -CONFIG_SYS_TEXT_BASE = 0x08000000 -#CONFIG_SYS_TEXT_BASE = 0x04000000 diff --git a/board/ti/omap2420h4/lowlevel_init.S b/board/ti/omap2420h4/lowlevel_init.S deleted file mode 100644 index 731c552e7a..0000000000 --- a/board/ti/omap2420h4/lowlevel_init.S +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/omap2420.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = PRCM_CLKCFG_CTRL - addr of valid reg - * R1 = CM_CLKEN_PLL - addr dpll ctlr reg - * R2 = dpll value - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - ******************************************************************************/ -.global go_to_speed - go_to_speed: - sub sp, sp, #0x4 /* get some stack space */ - str r4, [sp] /* save r4's value */ - - /* move into fast relock bypass */ - ldr r8, pll_ctl_add - mov r4, #0x2 - str r4, [r8] - ldr r4, pll_stat -block: - ldr r8, [r4] /* wait for bypass to take effect */ - and r8, r8, #0x3 - cmp r8, #0x1 - bne block - - /* set new dpll dividers _after_ in bypass */ - ldr r4, pll_div_add - ldr r8, pll_div_val - str r8, [r4] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r4, cfg3_0_addr - ldr r8, cfg3_0_val - str r8, [r4] - ldr r4, cfg4_0_addr - ldr r8, cfg4_0_val - str r8, [r4] - ldr r4, cfg1_0_addr - ldr r8, [r4] - orr r8, r8, #0x3 /* up gpmc divider */ - str r8, [r4] - - /* setup to 2x loop though code. The first loop pre-loads the - * icache, the 2nd commits the prcm config, and locks the dpll - */ - mov r4, #0x1000 /* spin spin spin */ - mov r8, #0x4 /* first pass condition & set registers */ - cmp r8, #0x4 -2: - ldrne r8, [r3] /* DPLL lock check */ - and r8, r8, #0x7 - cmp r8, #0x2 - beq 4f -3: - subeq r8, r8, #0x1 - streq r8, [r0] /* commit dividers (2nd time) */ - nop -lloop1: - sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop1 - mov r4, #0x40000 - cmp r8, #0x1 - nop - streq r2, [r1] /* lock dpll (2nd time) */ - nop -lloop2: - sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop2 - mov r4, #0x40000 - cmp r8, #0x1 - nop - ldreq r8, [r3] /* get lock condition for dpll */ - cmp r8, #0x4 /* first time though? */ - bne 2b - moveq r8, #0x2 /* set to dpll check condition. */ - beq 3b /* if condition not true branch */ -4: - ldr r4, [sp] - add sp, sp, #0x4 /* return stack space */ - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -cfg3_0_addr: - .word GPMC_CONFIG3_0 -cfg3_0_val: - .word H4_24XX_GPMC_CONFIG3_0 -cfg4_0_addr: - .word GPMC_CONFIG4_0 -cfg4_0_val: - .word H4_24XX_GPMC_CONFIG4_0 -cfg1_0_addr: - .word GPMC_CONFIG1_0 -pll_ctl_add: - .word CM_CLKEN_PLL -pll_stat: - .word CM_IDLEST_CKGEN -pll_div_add: - .word CM_CLKSEL1_PLL -pll_div_val: - .word DPLL_VAL /* DPLL setting (300MHz default) */ - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK diff --git a/board/ti/omap2420h4/mem.c b/board/ti/omap2420h4/mem.c deleted file mode 100644 index ba3f12aded..0000000000 --- a/board/ti/omap2420h4/mem.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/omap2420.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> - -/************************************************************ - * sdelay() - simple spin loop. Will be constant time as - * its generally used in 12MHz bypass conditions only. This - * is necessary until timers are accessible. - * - * not inline to increase chances its in cache when called - *************************************************************/ -void sdelay (unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/********************************************************************************* - * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default). - * -- called from SRAM, or Flash (using temp SRAM stack). - *********************************************************************************/ -void prcm_init(void) -{ - u32 div; - void (*f_lock_pll) (u32, u32, u32, u32); - extern void *_end_vect, *_start; - - f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE); - - __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ - __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ - __raw_writel(0, CM_ICLKEN1_CORE); - __raw_writel(0, CM_ICLKEN2_CORE); - - __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */ - __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */ - __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */ - __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */ - - div = BUS_DIV; - __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */ - sdelay(1000); - - if(running_in_sram()){ - /* If running fully from SRAM this is OK. The Flash bus drops out for just a little. - * but then comes back. If running from Flash this sequence kills you, thus you need - * to run it using CONFIG_PARTIAL_SRAM. - */ - __raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */ - wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */ - sdelay(1000); - /* set clock selection and dpll dividers. */ - __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */ - __raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */ - sdelay(10000); - __raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */ - sdelay(10000); - wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */ - }else if(running_in_flash()){ - /* if running from flash, need to jump to small relocated code area in SRAM. - * This is the only safe spot to do configurations from. - */ - (*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN); - } - - __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */ - wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */ - sdelay(1000); -} - -/************************************************************************** - * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow - * command line mem=xyz use all memory with out discontigious support - * compiled in. Could do it at the ATAG, but there really is two banks... - * Called as part of 2nd phase DDR init. - **************************************************************************/ -void make_cs1_contiguous(void) -{ - u32 size, a_add_low, a_add_high; - - size = get_sdr_cs_size(SDRC_CS0_OSET); - size /= SZ_32M; /* find size to offset CS1 */ - a_add_high = (size & 3) << 8; /* set up low field */ - a_add_low = (size & 0x3C) >> 2; /* set up high field */ - __raw_writel((a_add_high|a_add_low),SDRC_CS_CFG); - -} - -/******************************************************** - * mem_ok() - test used to see if timings are correct - * for a part. Helps in gussing which part - * we are currently using. - *******************************************************/ -u32 mem_ok(void) -{ - u32 val1, val2; - u32 pattern = 0x12345678; - - __raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */ - __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */ - __raw_writel(0x0,OMAP2420_SDRC_CS0+4); /* remove pattern off the bus */ - val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */ - val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ - - if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed*/ - return(0); - else - return(1); -} - - -/******************************************************** - * sdrc_init() - init the sdrc chip selects CS0 and CS1 - * - early init routines, called from flash or - * SRAM. - *******************************************************/ -void sdrc_init(void) -{ - #define EARLY_INIT 1 - do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */ -} - -/************************************************************************* - * do_sdrc_init(): initialize the SDRAM for use. - * -called from low level code with stack only. - * -code sets up SDRAM timing and muxing for 2422 or 2420. - * -optimal settings can be placed here, or redone after i2c - * inspection of board info - * - * This is a bit ugly, but should handle all memory moduels - * used with the H4. The first time though this code from s_init() - * we configure the first chip select. Later on we come back and - * will configure the 2nd chip select if it exists. - * - **************************************************************************/ -void do_sdrc_init(u32 offset, u32 early) -{ - u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype; - sdrc_data_t *sdata; /* do not change type */ - u32 a, b, r; - - static const sdrc_data_t sdrc_2422 = - { - H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0, - H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR, - 0, H4_2422_SDRC_DLLAB_CTRL - }; - static const sdrc_data_t sdrc_2420 = - { - H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR, - H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0, - H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR, - H4_2420_SDRC_DLLAB_CTRL - }; - - if (offset == SDRC_CS0_OSET) - cs0 = common = 1; /* int regs shared between both chip select */ - - cpu = get_cpu_type(); - rev = get_cpu_rev(); - - /* warning generated, though code generation is correct. this may bite later, - * but is ok for now. there is only so much C code you can do on stack only - * operation. - */ - if (cpu == CPU_2422){ - sdata = (sdrc_data_t *)&sdrc_2422; - pass_type = STACKED; - } else{ - sdata = (sdrc_data_t *)&sdrc_2420; - pass_type = IP_DDR; - } - - __asm__ __volatile__("": : :"memory"); /* limit compiler scope */ - - if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) { - if(mtype == DDR_COMBO){ - pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */ - pass_type = COMBO_DDR; /* CS1 config */ - __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER); - } - if(rev != CPU_2420_2422_ES1) /* for es2 and above smooth things out */ - make_cs1_contiguous(); - } - -next_mem_type: - if (common) { /* do a SDRC reset between types to clear regs*/ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */ - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */ - __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */ - __raw_writel(sdata->sdrc_sharing, SDRC_SHARING); -#ifdef POWER_SAVE - __raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG); - __raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING); - __raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER); -#endif - } - - if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */ - __raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset); - else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset); - } else if (pass_type == IP_SDR){ /* ip sdr-CS0 */ - __raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset); - } - - a = sdata->sdrc_actim_ctrla_0; - b = sdata->sdrc_actim_ctrlb_0; - r = sdata->sdrc_dllab_ctrl; - - /* work around ES1 DDR issues */ - if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){ - a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1; - b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1; - r = H4_242x_SDRC_RFR_CTRL_ES1; - } - - if (cs0) { - __raw_writel(a, SDRC_ACTIM_CTRLA_0); - __raw_writel(b, SDRC_ACTIM_CTRLB_0); - } else { - __raw_writel(a, SDRC_ACTIM_CTRLA_1); - __raw_writel(b, SDRC_ACTIM_CTRLB_1); - } - __raw_writel(r, SDRC_RFR_CTRL+offset); - - /* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0+offset); - sdelay(5000); /* susposed to be 100us per design spec for mddr/msdr */ - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset); - - /* - * CSx SDRC Mode Register - * Burst length = (4 - DDR) (2-SDR) - * Serial mode - * CAS latency = x - */ - if(pass_type == IP_SDR) - __raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset); - else - __raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset); - - /* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/ - if (rev == CPU_2420_2422_ES1){ - dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */ - __raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7) - ,SMS_CLASS_ARB0);/* enable bust complete for lcd */ - } - else - dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */ - - /* enable & load up DLL with good value for 75MHz, and set phase to 90 - * ES1 recommends 90 phase, ES2 recommends 72 phase. - */ - if (common && (pass_type != IP_SDR)) { - __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL); - __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL); - __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL); - __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL); - } - sdelay(90000); - - if(mem_ok()) - return; /* STACKED, other configued type */ - ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */ - goto next_mem_type; -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - u32 mux=0, mtype, mwidth, rev, tval; - - rev = get_cpu_rev(); - if (rev == CPU_2420_2422_ES1) - tval = 1; - else - tval = 0; /* disable bit switched meaning */ - - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CONFIG_SYS_NAND_BOOT - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#else - __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif - - /* discover bus connection from sysboot */ - if (is_gpmc_muxed() == GPMC_MUXED) - mux = BIT9; - mtype = get_gpmc0_type(); - mwidth = get_gpmc0_width(); - - /* setup cs0 */ - __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ - sdelay(1000); - -#ifdef CONFIG_SYS_NAND_BOOT - __raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0); -#else - __raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0); -#endif - -#ifdef PRCM_CONFIG_III - __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); -#endif - __raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0); - __raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0); -#ifdef PRCM_CONFIG_III - __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); - __raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0); -#endif - __raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */ - sdelay(2000); - - /* setup cs1 */ - __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */ - sdelay(1000); - __raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1); - __raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1); - __raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1); - __raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1); - __raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1); - __raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1); - __raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */ - sdelay(2000); -} diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c deleted file mode 100644 index 532e989bac..0000000000 --- a/board/ti/omap2420h4/omap2420h4.c +++ /dev/null @@ -1,867 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <netdev.h> -#include <asm/arch/omap2420.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/mem.h> -#include <i2c.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -void wait_for_command_complete(unsigned int wd_base); - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - gpmc_init(); /* in SRAM or SDRM, finish GPMC */ - - gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */ - gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */ - - return 0; -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_sram(void) -{ - /* if GP device unlock device SRAM for general use */ - if (get_device_type() == GP_DEVICE) { - __raw_writel(0xFF, A_REQINFOPERM0); - __raw_writel(0xCFDE, A_READPERM0); - __raw_writel(0xCFDE, A_WRITEPERM0); - } -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called path is with sram stack. - **********************************************************/ -void s_init(void) -{ - int in_sdram = running_in_sdram(); - - watchdog_init(); - set_muxconf_regs(); - delay(100); - try_unlock_sram(); - - if(!in_sdram) - prcm_init(); - - peripheral_enable(); - icache_enable(); - if (!in_sdram) - sdrc_init(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - ether_init(); /* better done here so timers are init'ed */ - return(0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * The ROM takes care of the secure one. Of the 3 GP ones, - * 1 can reset us directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); - -#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/ - __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR); - wait_for_command_complete(WD3_BASE); - __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR); - - __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR); - wait_for_command_complete(WD4_BASE); - __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR); -#endif -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base+WWPS); - } while (pending); -} - -/******************************************************************* - * Routine:ether_init - * Description: take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - ******************************************************************/ -void ether_init (void) -{ -#ifdef CONFIG_LAN91C96 - int cnt = 20; - - __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */ - - __raw_writew(0x0, LAN_RESET_REGISTER); - do { - __raw_writew(0x1, LAN_RESET_REGISTER); - udelay (100); - if (cnt == 0) - goto h4reset_err_out; - --cnt; - } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); - - cnt = 20; - - do { - __raw_writew(0x0, LAN_RESET_REGISTER); - udelay (100); - if (cnt == 0) - goto h4reset_err_out; - --cnt; - } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); - udelay (1000); - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (1000); - - h4reset_err_out: - return; -#endif -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - unsigned int size0=0,size1=0; - u32 mtype, btype; - u8 chg_on = 0x5; /* enable charge of back up battery */ - u8 vmode_on = 0x8C; - #define NOT_EARLY 0 - - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */ - - btype = get_board_type(); - mtype = get_mem_type(); - - display_board_info(btype); - if (btype == BOARD_H4_MENELAUS){ - update_mux(btype,mtype); /* combo part on menelaus */ - i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */ - i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */ - } - - if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { - do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */ - } - size0 = get_sdr_cs_size(SDRC_CS0_OSET); - size1 = get_sdr_cs_size(SDRC_CS1_OSET); - - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, size0 + size1); - - return 0; -} - -void dram_init_banksize(void) -{ - unsigned int size0, size1; - u32 rev; - - rev = get_cpu_rev(); - size0 = get_sdr_cs_size(SDRC_CS0_OSET); - size1 = get_sdr_cs_size(SDRC_CS1_OSET); - - if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */ - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - else /* ES2 and above can remap at 32MB granularity */ - gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; - gd->bd->bi_dram[1].size = size1; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; -} - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware - *********************************************************/ -void set_muxconf_regs (void) -{ - muxSetupSDRC(); - muxSetupGPMC(); - muxSetupUsb0(); - muxSetupUart3(); - muxSetupI2C1(); - muxSetupUART1(); - muxSetupLCD(); - muxSetupCamera(); - muxSetupMMCSD(); - muxSetupTouchScreen(); - muxSetupHDQ(); -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void peripheral_enable(void) -{ - unsigned int v, if_clks=0, func_clks=0; - - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */ - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CONFIG_SYS_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - delay(1000); - -#ifndef KERNEL_UPDATED - { -#define V1 0xffffffff -#define V2 0x00000007 - - __raw_writel(V1, CM_FCLKEN1_CORE); - __raw_writel(V2, CM_FCLKEN2_CORE); - __raw_writel(V1, CM_ICLKEN1_CORE); - __raw_writel(V1, CM_ICLKEN2_CORE); - } -#endif -} - -/**************************************** - * Routine: muxSetupUsb0 (ostboot) - * Description: Setup usb muxing - *****************************************/ -void muxSetupUsb0(void) -{ - volatile uint8 *MuxConfigReg; - volatile uint32 *otgCtrlReg; - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT; - *MuxConfigReg &= (uint8)(~0x1F); - - /* setup for USB VBus detection */ - otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL; - *otgCtrlReg |= 0x00040000; /* bit 18 */ -} - -/**************************************** - * Routine: muxSetupUart3 (ostboot) - * Description: Setup uart3 muxing - *****************************************/ -void muxSetupUart3(void) -{ - volatile uint8 *MuxConfigReg; - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX; - *MuxConfigReg &= (uint8)(~0x1F); -} - -/**************************************** - * Routine: muxSetupI2C1 (ostboot) - * Description: Setup i2c muxing - *****************************************/ -void muxSetupI2C1(void) -{ - volatile unsigned char *MuxConfigReg; - - /* I2C1 Clock pin configuration, PIN = M19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* I2C1 Data pin configuration, PIN = L15 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* Pull-up required on data line */ - /* external pull-up already present. */ - /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */ -} - -/**************************************** - * Routine: muxSetupUART1 (ostboot) - * Description: Set up uart1 muxing - *****************************************/ -void muxSetupUART1(void) -{ - volatile unsigned char *MuxConfigReg; - - /* UART1_CTS pin configuration, PIN = D21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RTS pin configuration, PIN = H21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_TX pin configuration, PIN = L20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RX pin configuration, PIN = T21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -/**************************************** - * Routine: muxSetupLCD (ostboot) - * Description: Setup lcd muxing - *****************************************/ -void muxSetupLCD(void) -{ - volatile unsigned char *MuxConfigReg; - - /* LCD_D0 pin configuration, PIN = Y7 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D1 pin configuration, PIN = P10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D2 pin configuration, PIN = V8 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D3 pin configuration, PIN = Y8 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D4 pin configuration, PIN = W8 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D5 pin configuration, PIN = R10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D6 pin configuration, PIN = Y9 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D7 pin configuration, PIN = V9 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D8 pin configuration, PIN = W9 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D9 pin configuration, PIN = P11 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D10 pin configuration, PIN = V10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D11 pin configuration, PIN = Y10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D12 pin configuration, PIN = W10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D13 pin configuration, PIN = R11 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D14 pin configuration, PIN = V11 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D15 pin configuration, PIN = W11 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D16 pin configuration, PIN = P12 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D17 pin configuration, PIN = R12 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_PCLK pin configuration, PIN = W6 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_VSYNC pin configuration, PIN = V7 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_HSYNC pin configuration, PIN = Y6 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_ACBIAS pin configuration, PIN = W7 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -/**************************************** - * Routine: muxSetupCamera (ostboot) - * Description: Setup camera muxing - *****************************************/ -void muxSetupCamera(void) -{ - volatile unsigned char *MuxConfigReg; - - /* CAMERA_RSTZ pin configuration, PIN = Y16 */ - /* CAM_RST is connected through the I2C IO expander.*/ - /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/ - /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */ - - /* CAMERA_XCLK pin configuration, PIN = U3 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_LCLK pin configuration, PIN = V5 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_VSYNC pin configuration, PIN = U2 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_HSYNC pin configuration, PIN = T3 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT0 pin configuration, PIN = T4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT1 pin configuration, PIN = V2 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT2 pin configuration, PIN = V3 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT3 pin configuration, PIN = U4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT4 pin configuration, PIN = W2 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT5 pin configuration, PIN = V4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT6 pin configuration, PIN = W3 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT7 pin configuration, PIN = Y2 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT8 pin configuration, PIN = Y4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT9 pin configuration, PIN = V6 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -/**************************************** - * Routine: muxSetupMMCSD (ostboot) - * Description: set up MMC muxing - *****************************************/ -void muxSetupMMCSD(void) -{ - volatile unsigned char *MuxConfigReg; - - /* SDMMC_CLKI pin configuration, PIN = H15 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_CLKO pin configuration, PIN = G19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_CMD pin configuration, PIN = H18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DAT0 pin configuration, PIN = F20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DAT1 pin configuration, PIN = H14 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DAT2 pin configuration, PIN = E19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DAT3 pin configuration, PIN = D19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DDIR0 pin configuration, PIN = F19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_DDIR1 pin configuration, PIN = E20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_DDIR2 pin configuration, PIN = F18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_DDIR3 pin configuration, PIN = E18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_CDIR pin configuration, PIN = G18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/ - /* MMC_CD for 2422IP=K1 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14, - *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ - - /* MMC_WP pin configuration, PIN = B4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13, - *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ -} - -/****************************************** - * Routine: muxSetupTouchScreen (ostboot) - * Description: Set up touch screen muxing - *******************************************/ -void muxSetupTouchScreen(void) -{ - volatile unsigned char *MuxConfigReg; - - /* SPI1_CLK pin configuration, PIN = U18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SPI1_MOSI pin configuration, PIN = V20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SPI1_MISO pin configuration, PIN = T18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SPI1_nCS0 pin configuration, PIN = U19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* PEN_IRQ pin configuration, PIN = P20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR, - *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ -} - -/**************************************** - * Routine: muxSetupHDQ (ostboot) - * Description: setup 1wire mux - *****************************************/ -void muxSetupHDQ(void) -{ - volatile unsigned char *MuxConfigReg; - - /* HDQ_SIO pin configuration, PIN = N18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -/*************************************************************** - * Routine: muxSetupGPMC (ostboot) - * Description: Configures balls which cam up in protected mode - ***************************************************************/ -void muxSetupGPMC(void) -{ - volatile uint8 *MuxConfigReg; - volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C; - - /* gpmc_io_dir */ - *MCR = 0x19000000; - - /* NOR FLASH CS0 */ - /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3, - *MuxConfigReg = 0x00 ; - - /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3, - *MuxConfigReg = 0x01 ; - - /* MPDB(Multi Port Debug Port) CS1 */ - /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1, - *MuxConfigReg = 0x00 ; - - /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2, - *MuxConfigReg = 0x00 ; -} - -/**************************************************************** - * Routine: muxSetupSDRC (ostboot) - * Description: Configures balls which come up in protected mode - ****************************************************************/ -void muxSetupSDRC(void) -{ - volatile uint8 *MuxConfigReg; - - /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1, - *MuxConfigReg = 0x00 ; - - /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2, - *MuxConfigReg = 0x00 ; - - /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3, - *MuxConfigReg = 0x00; - - if (get_cpu_type() == CPU_2422) { - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0, - *MuxConfigReg = 0x1b; - } -} - -/***************************************************************************** - * Routine: update_mux() - * Description: Update balls which are different beween boards. All should be - * updated to match functionaly. However, I'm only updating ones - * which I'll be using for now. When power comes into play they - * all need updating. - *****************************************************************************/ -void update_mux(u32 btype,u32 mtype) -{ - u32 cpu, base = OMAP2420_CTRL_BASE; - cpu = get_cpu_type(); - - if (btype == BOARD_H4_MENELAUS) { - if (cpu == CPU_2420) { - /* PIN = B3, GPIO.0->KBR5, mode 3, (pun?),-DO-*/ - __raw_writeb(0x3, base+0x30); - /* PIN = B13, GPIO.38->KBC6, mode 3, (pun?)-DO-*/ - __raw_writeb(0x3, base+0xa3); - /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/ - /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/ - /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/ - /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/ - /* PIN = M1 (HSUSBOTG) */ - /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/ - __raw_writeb(0x3, base+0x9d); - /* PIN = U32, (WLAN_CLKREQ) */ - /* PIN = Y11, WLAN */ - /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */ - __raw_writeb(0x3, base+0xe7); - /* PIN = AA8, mDOC */ - /* PIN = AA10, BT */ - /* PIN = AA13, WLAN */ - /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */ - __raw_writeb(0x3, base+0x10e); - /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */ - __raw_writeb(0x3, base+0x110); - /* PIN = J15 HHUSB */ - /* PIN = H19 HSUSB */ - /* PIN = W13, P13, R13, W16 ... */ - /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */ - __raw_writeb(0x3, base+0xde); - /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */ - __raw_writeb(0x0, base+0x12c); - /* PIN = AA17->sys_clkreq mode 0 -DO- */ - __raw_writeb(0x0, base+0x136); - } else if (cpu == CPU_2422) { - /* PIN = B3, GPIO.0->nc, mode 3, set above (pun?)*/ - /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/ - /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/ - /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/ - /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/ - __raw_writeb(0x0, base+0x92); - /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/ - /* PIN = M1 (HSUSBOTG) */ - /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/ - __raw_writeb(0x3, base+0x10c); - /* PIN = U32, (WLAN_CLKREQ) */ - /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */ - __raw_writeb(0x3, base+0x30); - /* PIN = AA8, mDOC */ - /* PIN = AA10, BT */ - /* PIN = AA12, WLAN */ - /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */ - __raw_writeb(0x3, base+0x10e); - /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */ - __raw_writeb(0x3, base+0x110); - /* PIN = J15 HHUSB */ - /* PIN = H19 HSUSB */ - /* PIN = W13, P13, R13, W16 ... */ - /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */ - __raw_writeb(0x3, base+0xde); - /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */ - __raw_writeb(0x0, base+0x12c); - /* PIN = AA17->sys_clkreq mode 0 -DO- */ - __raw_writeb(0x0, base+0x136); - } - - } else if (btype == BOARD_H4_SDP) { - if (cpu == CPU_2420) { - /* PIN = B3, GPIO.0->nc mode 3, set above (pun?)*/ - /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/ - /* Pin = Y11 VLNQ */ - /* Pin = AA4 VLNQ */ - /* Pin = AA6 VLNQ */ - /* Pin = AA8 VLNQ */ - /* Pin = AA10 VLNQ */ - /* Pin = AA12 VLNQ */ - /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */ - __raw_writeb(0x3, base+0x10e); - /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */ - __raw_writeb(0x3, base+0x110); - /* PIN = J15 MDOC_nDMAREQ */ - /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */ - __raw_writeb(0x3, base+0x114); - /* PIN = W13, V12, P13, R13, W19, W16 ... */ - /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */ - } else if (cpu == CPU_2422) { - /* PIN = B3, GPIO.0->MMC_CD, mode 3, set above */ - /* PIN = B13, GPIO.38->wlan_int, mode 3, (pun?)*/ - /* Pin = Y11 VLNQ */ - /* Pin = AA4 VLNQ */ - /* Pin = AA6 VLNQ */ - /* Pin = AA8 VLNQ */ - /* Pin = AA10 VLNQ */ - /* Pin = AA12 VLNQ */ - /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */ - __raw_writeb(0x3, base+0x10e); - /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */ - __raw_writeb(0x3, base+0x110); - /* PIN = J15 MDOC_nDMAREQ */ - /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */ - __raw_writeb(0x3, base+0x114); - /* PIN = W13, V12, P13, R13, W19, W16 ... */ - /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */ - } - } -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/ti/omap2420h4/sys_info.c b/board/ti/omap2420h4/sys_info.c deleted file mode 100644 index b12011e04a..0000000000 --- a/board/ti/omap2420h4/sys_info.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/omap2420.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mem.h> /* get mem tables */ -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <i2c.h> - -/************************************************************************** - * get_prod_id() - get id info from chips - ***************************************************************************/ -static u32 get_prod_id(void) -{ - u32 p; - p = __raw_readl(PRODUCTION_ID); /* get production ID */ - return((p & CPU_242X_PID_MASK) >> 16); -} - -/************************************************************************** - * get_cpu_type() - low level get cpu type - * - no C globals yet. - * - just looking to say if this is a 2422 or 2420 or ... - * - to start with we will look at switch settings.. - * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics - * (mux for 2420, non-mux for 2422). - ***************************************************************************/ -u32 get_cpu_type(void) -{ - u32 v; - - switch(get_prod_id()){ - case 1:;/* 2420 */ - case 2: return(CPU_2420); break; /* 2420 pop */ - case 4: return(CPU_2422); break; - case 8: return(CPU_2423); break; - default: break; /* early 2420/2422's unmarked */ - } - - v = __raw_readl(TAP_IDCODE_REG); - v &= CPU_24XX_ID_MASK; - if (v == CPU_2420_CHIPID) { /* currently 2420 and 2422 have same id */ - if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */ - return(CPU_2420); - else - return(CPU_2422); - } else - return(CPU_2420); /* don't know, say 2420 */ -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return(v+1); /* currently 2422 and 2420 match up */ -} -/**************************************************** - * is_mem_sdr() - return 1 if mem type in use is SDR - ****************************************************/ -u32 is_mem_sdr(void) -{ - volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET); - if(*burst == H4_2420_SDRC_MR_0_SDR) - return(1); - return(0); -} - -/*********************************************************** - * get_mem_type() - identify type of mDDR part used. - * 2422 uses stacked DDR, 2 parts CS0/CS1. - * 2420 may have 1 or 2, no good way to know...only init 1... - * when eeprom data is up we can select 1 more. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 cpu, sdr = is_mem_sdr(); - - cpu = get_cpu_type(); - if (cpu == CPU_2422 || cpu == CPU_2423) - return(DDR_STACKED); - - if(get_prod_id() == 0x2) - return(XDR_POP); - - if (get_board_type() == BOARD_H4_MENELAUS) - if(sdr) - return(SDR_DISCRETE); - else - return(DDR_COMBO); - else - if(sdr) /* SDP + SDR kit */ - return(SDR_DISCRETE); - else - return(DDR_DISCRETE); /* origional SDP */ -} - -/*********************************************************************** - * get_cs0_size() - get size of chip select 0/1 - ************************************************************************/ -u32 get_sdr_cs_size(u32 offset) -{ - u32 size; - size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */ - size &= 0x2FF; /* remove unwanted bits */ - size *= SZ_2M; /* find size in MB */ - return(size); -} - -/*********************************************************************** - * get_board_type() - get board type based on current production stats. - * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info. - * when they are available we can get info from there. This should - * be correct of all known boards up until today. - ************************************************************************/ -u32 get_board_type(void) -{ - if (i2c_probe(I2C_MENELAUS) == 0) - return(BOARD_H4_MENELAUS); - else - return(BOARD_H4_SDP); -} - -/****************************************************************** - * get_sysboot_value() - get init word settings (dip switch on h4) - ******************************************************************/ -inline u32 get_sysboot_value(void) -{ - return(0x00000FFF & __raw_readl(CONTROL_STATUS)); -} - -/*************************************************************************** - * get_gpmc0_base() - Return current address hardware will be - * fetching from. The below effectively gives what is correct, its a bit - * mis-leading compared to the TRM. For the most general case the mask - * needs to be also taken into account this does work in practice. - * - for u-boot we currently map: - * -- 0 to nothing, - * -- 4 to flash - * -- 8 to enent - * -- c to wifi - ****************************************************************************/ -u32 get_gpmc0_base(void) -{ - u32 b; - - b = __raw_readl(GPMC_CONFIG7_0); - b &= 0x1F; /* keep base [5:0] */ - b = b << 24; /* ret 0x0b000000 */ - return(b); -} - -/***************************************************************** - * is_gpmc_muxed() - tells if address/data lines are multiplexed - *****************************************************************/ -u32 is_gpmc_muxed(void) -{ - u32 mux; - mux = get_sysboot_value(); - if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3)) - return(GPMC_MUXED); /* NAND Boot mode */ - if (mux & BIT1) /* if mux'ed */ - return(GPMC_MUXED); - else - return(GPMC_NONMUXED); -} - -/************************************************************************ - * get_gpmc0_type() - read sysboot lines to see type of memory attached - ************************************************************************/ -u32 get_gpmc0_type(void) -{ - u32 type; - type = get_sysboot_value(); - if ((type & (BIT3|BIT2)) == (BIT3|BIT2)) - return(TYPE_NAND); - else - return(TYPE_NOR); -} - -/******************************************************************* - * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) - *******************************************************************/ -u32 get_gpmc0_width(void) -{ - u32 width; - width = get_sysboot_value(); - if ((width & 0xF) == (BIT3|BIT2)) - return(WIDTH_8BIT); - else - return(WIDTH_16BIT); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return(1); - if (i==bound) - return(0); - } while (1); -} - -/********************************************************************* - * display_board_info() - print banner with board info. - *********************************************************************/ -void display_board_info(u32 btype) -{ - static const char cpu_2420 [] = "2420"; /* cpu type */ - static const char cpu_2422 [] = "2422"; - static const char cpu_2423 [] = "2423"; - static const char db_men [] = "Menelaus"; /* board type */ - static const char db_ip [] = "IP"; - static const char mem_sdr [] = "mSDR"; /* memory type */ - static const char mem_ddr [] = "mDDR"; - static const char t_tst [] = "TST"; /* security level */ - static const char t_emu [] = "EMU"; - static const char t_hs [] = "HS"; - static const char t_gp [] = "GP"; - static const char unk [] = "?"; - - const char *cpu_s, *db_s, *mem_s, *sec_s; - u32 cpu, rev, sec; - - rev = get_cpu_rev(); - cpu = get_cpu_type(); - sec = get_device_type(); - - if(is_mem_sdr()) - mem_s = mem_sdr; - else - mem_s = mem_ddr; - - if(cpu == CPU_2423) - cpu_s = cpu_2423; - else if (cpu == CPU_2422) - cpu_s = cpu_2422; - else - cpu_s = cpu_2420; - - if(btype == BOARD_H4_MENELAUS) - db_s = db_men; - else - db_s = db_ip; - - switch(sec){ - case TST_DEVICE: sec_s = t_tst; break; - case EMU_DEVICE: sec_s = t_emu; break; - case HS_DEVICE: sec_s = t_hs; break; - case GP_DEVICE: sec_s = t_gp; break; - default: sec_s = unk; - } - - printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1); - printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s); -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = 242x IP platform (first 2xx boards) - * 1 = 242x Menelaus platfrom. - *************************************************************************/ -u32 get_board_rev(void) -{ - u32 rev = 0; - u32 btype = get_board_type(); - - if (btype == BOARD_H4_MENELAUS){ - rev = 1; - } - return(rev); -} - -/******************************************************** - * get_base(); get upper addr of current execution - *******************************************************/ -u32 get_base(void) -{ - u32 val; - __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); - val &= 0xF0000000; - val >>= 28; - return(val); -} - -/******************************************************** - * get_base2(); get 2upper addr of current execution - *******************************************************/ -u32 get_base2(void) -{ - u32 val; - __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); - val &= 0xFF000000; - val >>= 24; - return(val); -} - -/******************************************************** - * running_in_flash() - tell if currently running in - * flash. - *******************************************************/ -u32 running_in_flash(void) -{ - if (get_base() < 4) - return(1); /* in flash */ - return(0); /* running in SRAM or SDRAM */ -} - -/******************************************************** - * running_in_sram() - tell if currently running in - * sram. - *******************************************************/ -u32 running_in_sram(void) -{ - if (get_base() == 4) - return(1); /* in SRAM */ - return(0); /* running in FLASH or SDRAM */ -} -/******************************************************** - * running_in_sdram() - tell if currently running in - * flash. - *******************************************************/ -u32 running_in_sdram(void) -{ - if (get_base() > 4) - return(1); /* in sdram */ - return(0); /* running in SRAM or FLASH */ -} - -/************************************************************* - * running_from_internal_boot() - am I a signed NOR image. - *************************************************************/ -u32 running_from_internal_boot(void) -{ - u32 v, base; - - v = get_sysboot_value() & BIT3; - base = get_base2(); - /* if running at mask rom flash address and - * sysboot3 says this was an internal boot - */ - if ((base == 0x08) && v) - return(1); - else - return(0); -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8); - return(mode >>= 8); -} diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 46db1bfe66..90046e896e 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -71,22 +71,26 @@ int misc_init_r(void) void set_muxconf_regs_essential(void) { - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, sizeof(core_padconf_array_essential) / sizeof(struct pad_conf_entry)); - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_essential, sizeof(wkup_padconf_array_essential) / sizeof(struct pad_conf_entry)); } void set_muxconf_regs_non_essential(void) { - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_non_essential, sizeof(core_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_non_essential, sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); } diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 2bbe392d81..90ae29e7c6 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> -#include <asm/arch/clocks.h> +#include <asm/arch/clock.h> #include <asm/arch/gpio.h> #include <asm/gpio.h> @@ -139,16 +139,18 @@ int misc_init_r(void) void set_muxconf_regs_essential(void) { - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, sizeof(core_padconf_array_essential) / sizeof(struct pad_conf_entry)); - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_essential, sizeof(wkup_padconf_array_essential) / sizeof(struct pad_conf_entry)); if (omap_revision() >= OMAP4460_ES1_0) - do_set_mux(CONTROL_PADCONF_WKUP, + do_set_mux((*ctrl)->control_padconf_wkup_base, wkup_padconf_array_essential_4460, sizeof(wkup_padconf_array_essential_4460) / sizeof(struct pad_conf_entry)); @@ -156,27 +158,29 @@ void set_muxconf_regs_essential(void) void set_muxconf_regs_non_essential(void) { - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_non_essential, sizeof(core_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); if (omap_revision() < OMAP4460_ES1_0) - do_set_mux(CONTROL_PADCONF_CORE, + do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array_non_essential_4430, sizeof(core_padconf_array_non_essential_4430) / sizeof(struct pad_conf_entry)); else - do_set_mux(CONTROL_PADCONF_CORE, + do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array_non_essential_4460, sizeof(core_padconf_array_non_essential_4460) / sizeof(struct pad_conf_entry)); - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_non_essential, sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); if (omap_revision() < OMAP4460_ES1_0) - do_set_mux(CONTROL_PADCONF_WKUP, + do_set_mux((*ctrl)->control_padconf_wkup_base, wkup_padconf_array_non_essential_4430, sizeof(wkup_padconf_array_non_essential_4430) / sizeof(struct pad_conf_entry)); diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 4c1a4f7e78..5dd1ba3cb4 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -72,16 +72,18 @@ int misc_init_r(void) void set_muxconf_regs_essential(void) { - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, sizeof(core_padconf_array_essential) / sizeof(struct pad_conf_entry)); - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_essential, sizeof(wkup_padconf_array_essential) / sizeof(struct pad_conf_entry)); if (omap_revision() >= OMAP4460_ES1_0) - do_set_mux(CONTROL_PADCONF_WKUP, + do_set_mux((*ctrl)->control_padconf_wkup_base, wkup_padconf_array_essential_4460, sizeof(wkup_padconf_array_essential_4460) / sizeof(struct pad_conf_entry)); @@ -89,16 +91,18 @@ void set_muxconf_regs_essential(void) void set_muxconf_regs_non_essential(void) { - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_non_essential, sizeof(core_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_non_essential, sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); if (omap_revision() < OMAP4460_ES1_0) { - do_set_mux(CONTROL_PADCONF_WKUP, + do_set_mux((*ctrl)->control_padconf_wkup_base, wkup_padconf_array_non_essential_4430, sizeof(wkup_padconf_array_non_essential_4430) / sizeof(struct pad_conf_entry)); diff --git a/board/wandboard/README b/board/wandboard/README index e0b0b33020..ce83bbe4c5 100644 --- a/board/wandboard/README +++ b/board/wandboard/README @@ -14,12 +14,12 @@ Building U-boot for Wandboard To build U-Boot for the Wandboard Dual Lite version: -$ make wanboard_dl_config +$ make wandboard_dl_config $ make To build U-Boot for the Wandboard Solo version: -$ make wanboard_solo_config +$ make wandboard_solo_config $ make Flashing U-boot into the SD card diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index bb983528b9..5666cbf26f 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -10,9 +10,11 @@ */ #include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/iomux.h> #include <asm/arch/imx-regs.h> #include <asm/arch/mx6-pins.h> +#include <asm/arch/mxc_hdmi.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> @@ -21,9 +23,11 @@ #include <asm/sizes.h> #include <common.h> #include <fsl_esdhc.h> +#include <ipu_pixfmt.h> #include <mmc.h> #include <miiphy.h> #include <netdev.h> +#include <linux/fb.h> DECLARE_GLOBAL_DATA_PTR; @@ -206,6 +210,88 @@ int board_phy_config(struct phy_device *phydev) return 0; } +#if defined(CONFIG_VIDEO_IPUV3) +static void enable_hdmi(void) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +static struct fb_videomode const hdmi = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +}; + +int board_video_skip(void) +{ + int ret; + + ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); + + if (ret) + printf("HDMI cannot be configured: %d\n", ret); + + enable_hdmi(); + + return ret; +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + int reg; + + /* Turn on IPU clock */ + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; + writel(reg, &mxc_ccm->CCGR3); + + /* Turn on HDMI PHY clock */ + reg = readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK + | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + + /* clear HDMI PHY reset */ + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK + | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK + | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) + | (CHSCCDR_PODF_DIVIDE_BY_3 + << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + | (CHSCCDR_IPU_PRE_CLK_540M_PFD + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + int board_eth_init(bd_t *bis) { int ret; @@ -222,9 +308,21 @@ int board_eth_init(bd_t *bis) int board_early_init_f(void) { setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ diff --git a/boards.cfg b/boards.cfg index e2a8d42ab4..1e598cb7e2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -52,7 +52,6 @@ flea3 arm arm1136 - CarMedi mx35pdk arm arm1136 - freescale mx35 woodburn arm arm1136 - - mx35 woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg -omap2420h4 arm arm1136 - ti omap24xx tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x rpi_b arm arm1176 rpi_b raspberrypi bcm2835 integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T @@ -266,12 +265,14 @@ mx53loco arm armv7 mx53loco freesca mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg +cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL titanium arm armv7 titanium freescale mx6 titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg +vf610twr arm armv7 vf610twr freescale vf610 vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg eco5pk arm armv7 eco5pk 8dtech omap3 nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 @@ -347,6 +348,7 @@ pdnb3 arm ixp pdnb3 prodriv scpu arm ixp pdnb3 prodrive - pdnb3:SCPU balloon3 arm pxa h2200 arm pxa +lp8x4x arm pxa lp8x4x icpdas lubbock arm pxa palmld arm pxa palmtc arm pxa diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp index 9a5331153e..7a2863cfd2 100644 --- a/doc/README.mxc_ocotp +++ b/doc/README.mxc_ocotp @@ -2,6 +2,7 @@ Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP) on MXC This IP can be found on the following SoCs: + - Vybrid VF610, - i.MX6. Note that this IP is different from albeit similar to the IPs of the same name diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 9223f6e436..a0f1fa30f8 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -96,3 +96,4 @@ R5200 ColdFire - 48ead7a 2008-03-31 Zachary P. L CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs <matthias.fuchs@esd-electronics.com> PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk <wd@denx.de> PCIPPC6 powerpc MPC740/MPC750 - - Wolfgang Denk <wd@denx.de> +omap2420h4 arm omap24xx - 2013-06-04 Richard Woodruff <r-woodruff2@ti.com> diff --git a/doc/README.vf610 b/doc/README.vf610 new file mode 100644 index 0000000000..38cf5cfd20 --- /dev/null +++ b/doc/README.vf610 @@ -0,0 +1,10 @@ +U-Boot for Freescale Vybrid VF610 + +This file contains information for the port of U-Boot to the Freescale Vybrid +VF610 SoC. + +1. CONVENTIONS FOR FUSE ASSIGNMENTS +----------------------------------- + +1.1 MAC Address: It is stored in fuse bank 4, with the 16 msbs in word 2 and the + 32 lsbs in word 3. diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 54e9b1586f..ef38d71725 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -18,6 +18,20 @@ * * Adapted for OMAP2420 I2C, r-woodruff2@ti.com * + * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions + * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4 + * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older + * OMAPs and derivatives as well. The only anticipated exception would + * be the OMAP2420, which shall require driver modification. + * - Rewritten i2c_read to operate correctly with all types of chips + * (old function could not read consistent data from some I2C slaves). + * - Optimized i2c_write. + * - New i2c_probe, performs write access vs read. The old probe could + * hang the system under certain conditions (e.g. unconfigured pads). + * - The read/write/probe functions try to identify unconfigured bus. + * - Status functions now read irqstatus_raw as per TRM guidelines + * (except for OMAP243X and OMAP34XX). + * - Driver now supports up to I2C5 (OMAP5). */ #include <common.h> @@ -31,8 +45,11 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_TIMEOUT 1000 +/* Absolutely safe for status update at 100 kHz I2C: */ +#define I2C_WAIT 200 + static int wait_for_bb(void); -static u16 wait_for_pin(void); +static u16 wait_for_event(void); static void flush_fifo(void); /* @@ -137,10 +154,14 @@ void i2c_init(int speed, int slaveadd) /* own address */ writew(slaveadd, &i2c_base->oa); writew(I2C_CON_EN, &i2c_base->con); - - /* have to enable intrrupts or OMAP i2c module doesn't work */ +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + /* + * Have to enable interrupts for OMAP2/3, these IPs don't have + * an 'irqstatus_raw' register and we shall have to poll 'stat' + */ writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); + I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); +#endif udelay(1000); flush_fifo(); writew(0xFFFF, &i2c_base->stat); @@ -150,88 +171,6 @@ void i2c_init(int speed, int slaveadd) bus_initialized[current_bus] = 1; } -static int i2c_read_byte(u8 devaddr, u16 regoffset, u8 alen, u8 *value) -{ - int i2c_error = 0; - u16 status; - int i = 2 - alen; - u8 tmpbuf[2] = {(regoffset) >> 8, regoffset & 0xff}; - u16 w; - - /* wait until bus not busy */ - if (wait_for_bb()) - return 1; - - /* one byte only */ - writew(alen, &i2c_base->cnt); - /* set slave address */ - writew(devaddr, &i2c_base->sa); - /* no stop bit needed here */ - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | - I2C_CON_TRX, &i2c_base->con); - - /* send register offset */ - while (1) { - status = wait_for_pin(); - if (status == 0 || status & I2C_STAT_NACK) { - i2c_error = 1; - goto read_exit; - } - if (status & I2C_STAT_XRDY) { - w = tmpbuf[i++]; -#if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \ - defined(CONFIG_OMAP54XX)) - w |= tmpbuf[i++] << 8; -#endif - writew(w, &i2c_base->data); - writew(I2C_STAT_XRDY, &i2c_base->stat); - } - if (status & I2C_STAT_ARDY) { - writew(I2C_STAT_ARDY, &i2c_base->stat); - break; - } - } - - /* set slave address */ - writew(devaddr, &i2c_base->sa); - /* read one byte from slave */ - writew(1, &i2c_base->cnt); - /* need stop bit here */ - writew(I2C_CON_EN | I2C_CON_MST | - I2C_CON_STT | I2C_CON_STP, - &i2c_base->con); - - /* receive data */ - while (1) { - status = wait_for_pin(); - if (status == 0 || status & I2C_STAT_NACK) { - i2c_error = 1; - goto read_exit; - } - if (status & I2C_STAT_RRDY) { -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \ - defined(CONFIG_OMAP54XX) - *value = readb(&i2c_base->data); -#else - *value = readw(&i2c_base->data); -#endif - writew(I2C_STAT_RRDY, &i2c_base->stat); - } - if (status & I2C_STAT_ARDY) { - writew(I2C_STAT_ARDY, &i2c_base->stat); - break; - } - } - -read_exit: - flush_fifo(); - writew(0xFFFF, &i2c_base->stat); - writew(0, &i2c_base->cnt); - return i2c_error; -} - static void flush_fifo(void) { u16 stat; @@ -241,13 +180,7 @@ static void flush_fifo(void) while (1) { stat = readw(&i2c_base->stat); if (stat == I2C_STAT_RRDY) { -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \ - defined(CONFIG_OMAP54XX) readb(&i2c_base->data); -#else - readw(&i2c_base->data); -#endif writew(I2C_STAT_RRDY, &i2c_base->stat); udelay(1000); } else @@ -255,6 +188,10 @@ static void flush_fifo(void) } } +/* + * i2c_probe: Use write access. Allows to identify addresses that are + * write-only (like the config register of dual-port EEPROMs) + */ int i2c_probe(uchar chip) { u16 status; @@ -263,61 +200,81 @@ int i2c_probe(uchar chip) if (chip == readw(&i2c_base->oa)) return res; - /* wait until bus not busy */ + /* Wait until bus is free */ if (wait_for_bb()) return res; - /* try to read one byte */ - writew(1, &i2c_base->cnt); - /* set slave address */ + /* No data transfer, slave addr only */ + writew(0, &i2c_base->cnt); + /* Set slave address */ writew(chip, &i2c_base->sa); - /* stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); - - while (1) { - status = wait_for_pin(); - if (status == 0 || status & I2C_STAT_AL) { - res = 1; - goto probe_exit; - } - if (status & I2C_STAT_NACK) { - res = 1; - writew(0xff, &i2c_base->stat); - writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); - - if (wait_for_bb()) - res = 1; - - break; - } - if (status & I2C_STAT_ARDY) { - writew(I2C_STAT_ARDY, &i2c_base->stat); - break; - } - if (status & I2C_STAT_RRDY) { - res = 0; -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \ - defined(CONFIG_OMAP54XX) - readb(&i2c_base->data); -#else - readw(&i2c_base->data); -#endif - writew(I2C_STAT_RRDY, &i2c_base->stat); - } + /* Stop bit needed here */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, &i2c_base->con); + + status = wait_for_event(); + + if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { + /* + * With current high-level command implementation, notifying + * the user shall flood the console with 127 messages. If + * silent exit is desired upon unconfigured bus, remove the + * following 'if' section: + */ + if (status == I2C_STAT_XRDY) + printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", + current_bus, status); + + goto pr_exit; } -probe_exit: + /* Check for ACK (!NAK) */ + if (!(status & I2C_STAT_NACK)) { + res = 0; /* Device found */ + udelay(I2C_WAIT); /* Required by AM335X in SPL */ + /* Abort transfer (force idle state) */ + writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ + udelay(1000); + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | + I2C_CON_STP, &i2c_base->con); /* STP */ + } +pr_exit: flush_fifo(); - /* don't allow any more data in... we don't want it. */ - writew(0, &i2c_base->cnt); writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); return res; } +/* + * i2c_read: Function now uses a single I2C read transaction with bulk transfer + * of the requested number of bytes (note that the 'i2c md' command + * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is + * defined in the board config header, this transaction shall be with + * Repeated Start (Sr) between the address and data phases; otherwise + * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). + * The address (reg offset) may be 0, 1 or 2 bytes long. + * Function now reads correctly from chips that return more than one + * byte of data per addressed register (like TI temperature sensors), + * or that do not need a register address at all (such as some clock + * distributors). + */ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { - int i; + int i2c_error = 0; + u16 status; + + if (alen < 0) { + puts("I2C read: addr len < 0\n"); + return 1; + } + if (len < 0) { + puts("I2C read: data len < 0\n"); + return 1; + } + if (buffer == NULL) { + puts("I2C read: NULL pointer passed\n"); + return 1; + } if (alen > 2) { printf("I2C read: addr len %d not supported\n", alen); @@ -329,24 +286,122 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) return 1; } - for (i = 0; i < len; i++) { - if (i2c_read_byte(chip, addr + i, alen, &buffer[i])) { - puts("I2C read: I/O error\n"); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 1; + /* Wait until bus not busy */ + if (wait_for_bb()) + return 1; + + /* Zero, one or two bytes reg address (offset) */ + writew(alen, &i2c_base->cnt); + /* Set slave address */ + writew(chip, &i2c_base->sa); + + if (alen) { + /* Must write reg offset first */ +#ifdef CONFIG_I2C_REPEATED_START + /* No stop bit, use Repeated Start (Sr) */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | + I2C_CON_TRX, &i2c_base->con); +#else + /* Stop - Start (P-S) */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | + I2C_CON_TRX, &i2c_base->con); +#endif + /* Send register offset */ + while (1) { + status = wait_for_event(); + /* Try to identify bus that is not padconf'd for I2C */ + if (status == I2C_STAT_XRDY) { + i2c_error = 2; + printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n", + current_bus, status); + goto rd_exit; + } + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", + status); + goto rd_exit; + } + if (alen) { + if (status & I2C_STAT_XRDY) { + alen--; + /* Do we have to use byte access? */ + writeb((addr >> (8 * alen)) & 0xff, + &i2c_base->data); + writew(I2C_STAT_XRDY, &i2c_base->stat); + } + } + if (status & I2C_STAT_ARDY) { + writew(I2C_STAT_ARDY, &i2c_base->stat); + break; + } } } + /* Set slave address */ + writew(chip, &i2c_base->sa); + /* Read len bytes from slave */ + writew(len, &i2c_base->cnt); + /* Need stop bit here */ + writew(I2C_CON_EN | I2C_CON_MST | + I2C_CON_STT | I2C_CON_STP, + &i2c_base->con); - return 0; + /* Receive data */ + while (1) { + status = wait_for_event(); + /* + * Try to identify bus that is not padconf'd for I2C. This + * state could be left over from previous transactions if + * the address phase is skipped due to alen=0. + */ + if (status == I2C_STAT_XRDY) { + i2c_error = 2; + printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n", + current_bus, status); + goto rd_exit; + } + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + goto rd_exit; + } + if (status & I2C_STAT_RRDY) { + *buffer++ = readb(&i2c_base->data); + writew(I2C_STAT_RRDY, &i2c_base->stat); + } + if (status & I2C_STAT_ARDY) { + writew(I2C_STAT_ARDY, &i2c_base->stat); + break; + } + } + +rd_exit: + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); + return i2c_error; } +/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { int i; u16 status; int i2c_error = 0; - u16 w; - u8 tmpbuf[2] = {addr >> 8, addr & 0xff}; + + if (alen < 0) { + puts("I2C write: addr len < 0\n"); + return 1; + } + + if (len < 0) { + puts("I2C write: data len < 0\n"); + return 1; + } + + if (buffer == NULL) { + puts("I2C write: NULL pointer passed\n"); + return 1; + } if (alen > 2) { printf("I2C write: addr len %d not supported\n", alen); @@ -355,92 +410,137 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) if (addr + len > (1 << 16)) { printf("I2C write: address 0x%x + 0x%x out of range\n", - addr, len); + addr, len); return 1; } - /* wait until bus not busy */ + /* Wait until bus not busy */ if (wait_for_bb()) return 1; - /* start address phase - will write regoffset + len bytes data */ - /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */ + /* Start address phase - will write regoffset + len bytes data */ writew(alen + len, &i2c_base->cnt); - /* set slave address */ + /* Set slave address */ writew(chip, &i2c_base->sa); - /* stop bit needed here */ + /* Stop bit needed here */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, &i2c_base->con); - - /* Send address and data */ - for (i = -alen; i < len; i++) { - status = wait_for_pin(); - + I2C_CON_STP, &i2c_base->con); + + while (alen) { + /* Must write reg offset (one or two bytes) */ + status = wait_for_event(); + /* Try to identify bus that is not padconf'd for I2C */ + if (status == I2C_STAT_XRDY) { + i2c_error = 2; + printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", + current_bus, status); + goto wr_exit; + } if (status == 0 || status & I2C_STAT_NACK) { i2c_error = 1; - printf("i2c error waiting for data ACK (status=0x%x)\n", - status); - goto write_exit; + printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", + status); + goto wr_exit; } - if (status & I2C_STAT_XRDY) { - w = (i < 0) ? tmpbuf[2+i] : buffer[i]; -#if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \ - defined(CONFIG_OMAP54XX)) - w |= ((++i < 0) ? tmpbuf[2+i] : buffer[i]) << 8; -#endif - writew(w, &i2c_base->data); + alen--; + writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data); + writew(I2C_STAT_XRDY, &i2c_base->stat); + } else { + i2c_error = 1; + printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n", + status); + goto wr_exit; + } + } + /* Address phase is over, now write data */ + for (i = 0; i < len; i++) { + status = wait_for_event(); + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + printf("i2c_write: error waiting for data ACK (status=0x%x)\n", + status); + goto wr_exit; + } + if (status & I2C_STAT_XRDY) { + writeb(buffer[i], &i2c_base->data); writew(I2C_STAT_XRDY, &i2c_base->stat); } else { i2c_error = 1; - printf("i2c bus not ready for Tx (i=%d)\n", i); - goto write_exit; + printf("i2c_write: bus not ready for data Tx (i=%d)\n", + i); + goto wr_exit; } } -write_exit: +wr_exit: flush_fifo(); writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); return i2c_error; } +/* + * Wait for the bus to be free by checking the Bus Busy (BB) + * bit to become clear + */ static int wait_for_bb(void) { int timeout = I2C_TIMEOUT; u16 stat; writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { +#else + /* Read RAW status */ + while ((stat = readw(&i2c_base->irqstatus_raw) & + I2C_STAT_BB) && timeout--) { +#endif writew(stat, &i2c_base->stat); - udelay(1000); + udelay(I2C_WAIT); } if (timeout <= 0) { - printf("timed out in wait_for_bb: I2C_STAT=%x\n", - readw(&i2c_base->stat)); + printf("Timed out in wait_for_bb: status=%04x\n", + stat); return 1; } writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ return 0; } -static u16 wait_for_pin(void) +/* + * Wait for the I2C controller to complete current action + * and update status + */ +static u16 wait_for_event(void) { u16 status; int timeout = I2C_TIMEOUT; do { - udelay(1000); + udelay(I2C_WAIT); +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) status = readw(&i2c_base->stat); +#else + /* Read RAW status */ + status = readw(&i2c_base->irqstatus_raw); +#endif } while (!(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | I2C_STAT_AL)) && timeout--); if (timeout <= 0) { - printf("timed out in wait_for_pin: I2C_STAT=%x\n", - readw(&i2c_base->stat)); + printf("Timed out in wait_for_event: status=%04x\n", + status); + /* + * If status is still 0 here, probably the bus pads have + * not been configured for I2C, and/or pull-ups are missing. + */ + printf("Check if pads/pull-ups of bus %d are properly configured\n", + current_bus); writew(0xFFFF, &i2c_base->stat); status = 0; } @@ -450,28 +550,36 @@ static u16 wait_for_pin(void) int i2c_set_bus_num(unsigned int bus) { - if ((bus < 0) || (bus >= I2C_BUS_MAX)) { - printf("Bad bus: %d\n", bus); + if (bus >= I2C_BUS_MAX) { + printf("Bad bus: %x\n", bus); return -1; } -#if I2C_BUS_MAX == 4 - if (bus == 3) - i2c_base = (struct i2c *)I2C_BASE4; - else - if (bus == 2) + switch (bus) { + default: + bus = 0; /* Fall through */ + case 0: + i2c_base = (struct i2c *)I2C_BASE1; + break; + case 1: + i2c_base = (struct i2c *)I2C_BASE2; + break; +#if (I2C_BUS_MAX > 2) + case 2: i2c_base = (struct i2c *)I2C_BASE3; - else + break; +#if (I2C_BUS_MAX > 3) + case 3: + i2c_base = (struct i2c *)I2C_BASE4; + break; +#if (I2C_BUS_MAX > 4) + case 4: + i2c_base = (struct i2c *)I2C_BASE5; + break; #endif -#if I2C_BUS_MAX == 3 - if (bus == 2) - i2c_base = (struct i2c *)I2C_BASE3; - else #endif - if (bus == 1) - i2c_base = (struct i2c *)I2C_BASE2; - else - i2c_base = (struct i2c *)I2C_BASE1; +#endif + } current_bus = bus; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index afdfa886e8..975b2c5ba4 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -113,23 +113,21 @@ static void omap5_pbias_config(struct mmc *mmc) u32 value = 0; value = readl((*ctrl)->control_pbias); - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; + value &= ~SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(10); /* wait 10 us */ + value &= ~SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias); palmas_mmc1_poweron_ldo(); value = readl((*ctrl)->control_pbias); - value &= ~SDCARD_BIAS_HIZ_MODE; - value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; + value |= SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias); - - value = readl((*ctrl)->control_pbias); - if (value & (1 << 23)) { - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; - writel(value, (*ctrl)->control_pbias); - } + udelay(150); /* wait 150 us */ + value |= SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(150); /* wait 150 us */ } #endif diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4dbcdca4a0..da95e285b7 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -516,9 +516,7 @@ static int fec_open(struct eth_device *edev) #ifdef FEC_QUIRK_ENET_MAC { u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; - u32 rcr = (readl(&fec->eth->r_cntrl) & - ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | - FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; + u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; if (speed == _1000BASET) ecr |= FEC_ECNTRL_SPEED; else if (speed != _100BASET) diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 09c832d8b6..2d275a7614 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -25,28 +25,137 @@ void palmas_init_settings(void) { - return; +#ifdef CONFIG_PALMAS_SMPS7_FPWM + int err; + /* + * Set SMPS7 (1.8 V I/O supply on platforms with TWL6035/37) to + * forced PWM mode. This reduces noise (but affects efficiency). + */ + u8 val = SMPS_MODE_SLP_FPWM | SMPS_MODE_ACT_FPWM; + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS7_CTRL, val); + if (err) + printf("palmas: could not force PWM for SMPS7: err = %d\n", + err); +#endif } int palmas_mmc1_poweron_ldo(void) { u8 val = 0; - /* set LDO9 TWL6035 to 3V */ - val = 0x2b; /* (3 -.9)*28 +1 */ - - if (palmas_i2c_write_u8(0x48, LDO9_VOLTAGE, val)) { - printf("twl6035: could not set LDO9 voltage.\n"); +#if defined(CONFIG_DRA7XX) + /* + * Currently valid for the dra7xx_evm board: + * Set TPS659038 LDO1 to 3.0 V + */ + val = LDO_VOLT_3V0; + if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, val)) { + printf("tps65903x: could not set LDO1 voltage.\n"); + return 1; + } + /* TURN ON LDO1 */ + val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val)) { + printf("tps65903x: could not turn on LDO1.\n"); return 1; } + return 0; +#else + /* + * We assume that this is a OMAP543X + TWL603X board: + * Set TWL6035/37 LDO9 to 3.0 V + */ + val = LDO_VOLT_3V0; + return twl603x_mmc1_set_ldo9(val); +#endif +} - /* TURN ON LDO9 */ - val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; +/* + * On some OMAP5 + TWL603X hardware the SD card socket and LDO9_IN are + * powered by an external 3.3 V regulator, while the output of LDO9 + * supplies VDDS_SDCARD for the OMAP5 interface only. This implies that + * LDO9 could be set to 'bypass' mode when required (e.g. for 3.3 V cards). + */ +int twl603x_mmc1_set_ldo9(u8 vsel) +{ + u8 cval = 0, vval = 0; /* Off by default */ + int err; - if (palmas_i2c_write_u8(0x48, LDO9_CTRL, val)) { - printf("twl6035: could not turn on LDO9.\n"); - return 1; + if (vsel) { + /* Turn on */ + if (vsel > LDO_VOLT_3V3) { + /* Put LDO9 in bypass */ + cval = LDO9_BYP_EN | RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + vval = LDO_VOLT_3V3; + } else { + cval = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + vval = vsel & 0x3f; + } + } + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_VOLTAGE, vval); + if (err) { + printf("twl603x: could not set LDO9 %s: err = %d\n", + vsel > LDO_VOLT_3V3 ? "bypass" : "voltage", err); + return err; } + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_CTRL, cval); + if (err) + printf("twl603x: could not turn %s LDO9: err = %d\n", + cval ? "on" : "off", err); + return err; +} - return 0; +#ifdef CONFIG_PALMAS_AUDPWR +/* + * Turn audio codec power and 32 kHz clock on/off. Use for + * testing OMAP543X + TWL603X + TWL604X boards only. + */ +int twl603x_audio_power(u8 on) +{ + u8 cval = 0, vval = 0, c32k = 0; + int err; + + if (on) { + vval = SMPS_VOLT_2V1; + cval = SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO; + c32k = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + } + /* Set SMPS9 to 2.1 V (for TWL604x), or to 0 (off) */ + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS9_VOLTAGE, vval); + if (err) { + printf("twl603x: could not set SMPS9 voltage: err = %d\n", + err); + return err; + } + /* Turn on or off SMPS9 */ + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS9_CTRL, cval); + if (err) { + printf("twl603x: could not turn SMPS9 %s: err = %d\n", + cval ? "on" : "off", err); + return err; + } + /* Output 32 kHz clock on or off */ + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, CLK32KGAUDIO_CTRL, c32k); + if (err) + printf("twl603x: could not turn CLK32KGAUDIO %s: err = %d\n", + c32k ? "on" : "off", err); + return err; +} +#endif + +/* + * Enable/disable back-up battery (or super cap) charging on TWL6035/37. + * Please use defined BB_xxx values. + */ +int twl603x_enable_bb_charge(u8 bb_fields) +{ + u8 val = bb_fields & 0x0f; + int err; + + val |= (VRTC_EN_SLP | VRTC_EN_OFF | VRTC_PWEN); + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, BB_VRTC_CTRL, val); + if (err) + printf("twl603x: could not set BB_VRTC_CTRL to 0x%02x: err = %d\n", + val, err); + return err; } diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 442b7ea0df..0f954a5f33 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o +COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 7f013ab33c..d77c25fa9b 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -74,13 +74,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ defined(CONFIG_TI814X) -#if defined(CONFIG_APTIX) - /* /13 mode so Aptix 6MHz can hit 115200 */ - serial_out(3, &com_port->mdr1); -#else /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); -#endif #endif /* CONFIG_OMAP */ } diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c new file mode 100644 index 0000000000..51d56662c6 --- /dev/null +++ b/drivers/serial/serial_lpuart.c @@ -0,0 +1,132 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include <serial.h> +#include <linux/compiler.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> + +#define US1_TDRE (1 << 7) +#define US1_RDRF (1 << 5) +#define UC2_TE (1 << 3) +#define UC2_RE (1 << 2) + +DECLARE_GLOBAL_DATA_PTR; + +struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE; + +static void lpuart_serial_setbrg(void) +{ + u32 clk = mxc_get_clock(MXC_UART_CLK); + u16 sbr; + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + sbr = (u16)(clk / (16 * gd->baudrate)); + /* place adjustment later - n/32 BRFA */ + + __raw_writeb(sbr >> 8, &base->ubdh); + __raw_writeb(sbr & 0xff, &base->ubdl); +} + +static int lpuart_serial_getc(void) +{ + u8 status; + + while (!(__raw_readb(&base->us1) & US1_RDRF)) + WATCHDOG_RESET(); + + status = __raw_readb(&base->us1); + status |= US1_RDRF; + __raw_writeb(status, &base->us1); + + return __raw_readb(&base->ud); +} + +static void lpuart_serial_putc(const char c) +{ + if (c == '\n') + serial_putc('\r'); + + while (!(__raw_readb(&base->us1) & US1_TDRE)) + WATCHDOG_RESET(); + + __raw_writeb(c, &base->ud); +} + +/* + * Test whether a character is in the RX buffer + */ +static int lpuart_serial_tstc(void) +{ + if (__raw_readb(&base->urcfifo) == 0) + return 0; + + return 1; +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +static int lpuart_serial_init(void) +{ + u8 ctrl; + + ctrl = __raw_readb(&base->uc2); + ctrl &= ~UC2_RE; + ctrl &= ~UC2_TE; + __raw_writeb(ctrl, &base->uc2); + + __raw_writeb(0, &base->umodem); + __raw_writeb(0, &base->uc1); + + /* provide data bits, parity, stop bit, etc */ + + serial_setbrg(); + + __raw_writeb(UC2_RE | UC2_TE, &base->uc2); + + return 0; +} + +static struct serial_device lpuart_serial_drv = { + .name = "lpuart_serial", + .start = lpuart_serial_init, + .stop = NULL, + .setbrg = lpuart_serial_setbrg, + .putc = lpuart_serial_putc, + .puts = default_serial_puts, + .getc = lpuart_serial_getc, + .tstc = lpuart_serial_tstc, +}; + +void lpuart_serial_initialize(void) +{ + serial_register(&lpuart_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &lpuart_serial_drv; +} diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index b92eef4db9..3c07da3597 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -151,12 +151,7 @@ static int calc_divisor (NS16550_t port) } #endif -#ifdef CONFIG_APTIX -#define MODE_X_DIV 13 -#else #define MODE_X_DIV 16 -#endif - /* Compute divisor value. Normally, we should simply return: * CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate * but we need to round that value by adding 0.5. diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c index c7876ed094..a395ebcc67 100644 --- a/drivers/usb/musb/omap3.c +++ b/drivers/usb/musb/omap3.c @@ -30,6 +30,7 @@ * MA 02111-1307 USA */ +#include <asm/omap_common.h> #include <twl4030.h> #include <twl6030.h> #include "omap3.h" @@ -135,7 +136,8 @@ int musb_platform_init(void) #endif #ifdef CONFIG_OMAP4430 - u32 *usbotghs_control = (u32 *)(CTRL_BASE + 0x33C); + u32 *usbotghs_control = + (u32 *)((*ctrl)->control_usbotghs_ctrl); *usbotghs_control = 0x15; #endif platform_needs_initialization = 0; diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 461ff6e860..b189419358 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -39,6 +39,11 @@ static GraphicDevice panel; * setenv videomode * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066, * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0 + * + * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel: + * setenv videomode + * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851, + * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0 */ static void mxs_lcd_init(GraphicDevice *panel, diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index d57578df6c..b9bbbc6339 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,7 +27,7 @@ LIB := $(obj)libwatchdog.o COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610)) COBJS-y += imx_watchdog.o endif COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h new file mode 100644 index 0000000000..13638587f1 --- /dev/null +++ b/include/configs/cgtqmx6eval.h @@ -0,0 +1,194 @@ +/* + * + * Congatec Conga-QEVAl board configuration file. + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Based on Freescale i.MX6Q Sabre Lite board configuration file. + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Leo Sartre, <lsartre@adeneo-embedded.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_CGTQMX6EVAL_H +#define __CONFIG_CGTQMX6EVAL_H + +#define CONFIG_MX6 + +#include "mx6_common.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MACH_TYPE 4122 + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "boot_dir=/boot\0" \ + "console=ttymxc1\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr=0x11000000\0" \ + "boot_fdt=try\0" \ + "mmcdev=1\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${boot_dir}/${uimage}\0" \ + "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \ + "${boot_dir}/${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else "\ + "echo ERR: Fail to boot from mmc; " \ + "fi; " \ + "fi; " \ + "else echo ERR: Fail to boot from mmc; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "CGT-QMX6-Quad U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_CGTQMX6EVAL_H */ diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 198892ba57..00e92a6850 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -36,6 +36,7 @@ #define CONFIG_MACH_DAVINCI_DA830_EVM #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA830 /* TI DA830 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE @@ -226,6 +227,28 @@ #define CONFIG_CMD_SAVEENV #endif +/* SD/MMC configuration */ +#ifndef CONFIG_USE_NAND +#define CONFIG_MMC +#define CONFIG_DAVINCI_MMC_SD1 +#define CONFIG_GENERIC_MMC +#define CONFIG_DAVINCI_MMC +#endif + +/* + * Enable MMC commands only when + * MMC support is present + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_DA8XX) +#define CONFIG_DOS_PARTITION /* include support for FAT/storage */ +#define CONFIG_CMD_FAT /* include support for FAT cmd */ +#endif + +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#endif + #if !defined(CONFIG_USE_NAND) && \ !defined(CONFIG_USE_NOR) && \ !defined(CONFIG_USE_SPIFLASH) @@ -244,8 +267,6 @@ #define CONFIG_USB_STORAGE /* MSC class support */ #define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ -#define CONFIG_CMD_FAT /* inclue support for FAT/storage */ -#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */ #ifdef CONFIG_USB_KEYBOARD /* HID class support */ #define CONFIG_SYS_USB_EVENT_POLL diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 28a306ba8e..0eea28c80a 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -28,11 +28,17 @@ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H +/* High Level Configuration Options */ +#define CONFIG_DRA7XX /* in a TI DRA7XX core */ #define CONFIG_ENV_IS_NOWHERE /* For now. */ #include <configs/omap5_common.h> -#define CONFIG_DRA7XX /* in a TI DRA7XX core */ #define CONFIG_SYS_PROMPT "DRA752 EVM # " +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 UART1_BASE +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_OMAP_ABE_SYSCK #endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h new file mode 100644 index 0000000000..026f32134a --- /dev/null +++ b/include/configs/lp8x4x.h @@ -0,0 +1,262 @@ +/* + * ICP DAS LP-8x4x configuration file + * + * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */ +#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */ +#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X +#define CONFIG_SYS_TEXT_BASE 0x00000000 + +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOOTCOMMAND \ + "bootm 80000;" + +#define CONFIG_BOOTARGS \ + "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ + "init=/sbin/init rootfstype=ext3" + +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_LZMA /* LZMA compression support */ +#undef CONFIG_OF_LIBFDT + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_CONS_INDEX 3 +#define CONFIG_BAUDRATE 115200 + +/* + * Bootloader Components Configuration + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_USB +#undef CONFIG_LCD +#undef CONFIG_CMD_IDE + +/* + * Networking Configuration + * chip on the ICPDAS LINPAC board + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x0C000000 +#define DM9000_IO 0x0C000000 +#define DM9000_DATA 0x0C004000 +#define DM9000_IO_2 0x0D000000 +#define DM9000_DATA_2 0x0D004000 +#define CONFIG_NET_RETRY_COUNT 10 + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#endif + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 + +#undef CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE 1 + +/* + * Clock Configuration + */ +#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0xa0008000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +/* Use first 64kb bank of the internal SRAM */ +#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 + +/* + * NOR FLASH + */ +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x40000 + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } + +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_PROTECTION 1 + +#define CONFIG_ENV_IS_IN_FLASH 1 + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPSR0_VAL 0x0808c014 +#define CONFIG_SYS_GPSR1_VAL 0x00cf0002 +#define CONFIG_SYS_GPSR2_VAL 0x0221c000 +#define CONFIG_SYS_GPSR3_VAL 0x00020000 + +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x0000ab80 +#define CONFIG_SYS_GPCR2_VAL 0x00100000 +#define CONFIG_SYS_GPCR3_VAL 0x0 + +#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4 +#define CONFIG_SYS_GPDR1_VAL 0xfcffab83 +#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff +#define CONFIG_SYS_GPDR3_VAL 0x00021b81 + +#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018 +#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402 +#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c +#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 + +#define CONFIG_SYS_PSSR_VAL 0x32 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x005002c0 +#define CONFIG_SYS_CCCR 0x02000290 +#define CONFIG_SYS_CLKCFG 0x0000000b + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2 +#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc +#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9 +#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 +#define CONFIG_SYS_MDREFR_VAL 0x2093e018 +#define CONFIG_SYS_MDCNFG_VAL 0x890009d1 +#define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000001 +#define CONFIG_SYS_MCMEM0_VAL 0x0000c497 +#define CONFIG_SYS_MCMEM1_VAL 0x0000c497 +#define CONFIG_SYS_MCATT0_VAL 0x0000c497 +#define CONFIG_SYS_MCATT1_VAL 0x0000c497 +#define CONFIG_SYS_MCIO0_VAL 0x00008407 +#define CONFIG_SYS_MCIO1_VAL 0x00008407 + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_VOIPAC_LCD +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_BOARD_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x" +#define CONFIG_USB_STORAGE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index e5a15a451c..3a58afee9a 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -60,6 +60,7 @@ #define CONFIG_CMD_MMC #define CONFIG_CMD_USB #define CONFIG_CMD_BOOTZ +#define CONFIG_VIDEO /* Memory configurations */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ @@ -133,6 +134,22 @@ #define CONFIG_USB_STORAGE #endif +/* Framebuffer support */ +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) +#endif + /* Boot Linux */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 54d01f9ed8..de69182b4f 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -64,6 +64,7 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_NAND #define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_VIDEO /* Memory configurations */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ @@ -235,6 +236,22 @@ #endif #endif +/* Framebuffer support */ +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) +#endif + /* Boot Linux */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 41974b1262..b0a965fbba 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -118,7 +118,7 @@ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \ + "mmcpart=2\0" \ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ "update_sd_firmware_filename=u-boot.imx\0" \ "update_sd_firmware=" \ @@ -240,7 +240,6 @@ #define CONFIG_ENV_SIZE (8 * 1024) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_OF_LIBFDT diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h index 7298a7692e..bfaa420ed0 100644 --- a/include/configs/mx6qsabre_common.h +++ b/include/configs/mx6qsabre_common.h @@ -97,7 +97,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \ + "mmcpart=1\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "update_sd_firmware=" \ "if test ${ip_dyn} = yes; then " \ diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 1583c11aab..76f7812069 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -35,7 +35,12 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */ #endif +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + #endif /* __MX6QSABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h index 3b8d752eed..44f07cbe45 100644 --- a/include/configs/mx6qsabresd.h +++ b/include/configs/mx6qsabresd.h @@ -29,7 +29,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ -#define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */ #endif #endif /* __MX6QSABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 8a94efdd6d..19dcdd605c 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -59,7 +59,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_LOADADDR 0x82000000 #define CONFIG_SYS_TEXT_BASE 0x87800000 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h deleted file mode 100644 index 04e8d3ad51..0000000000 --- a/include/configs/omap2420h4.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Richard Woodruff <r-woodruff2@ti.com> - * Kshitij Gupta <kshitij@ti.com> - * - * Configuration settings for the 242x TI H4 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2420 1 /* which is in a 2420 */ -#define CONFIG_OMAP2420H4 1 /* and on a H4 board */ -/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ -/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ - -#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 - -/* Clock config to target*/ -#define PRCM_CONFIG_II 1 -/* #define PRCM_CONFIG_III 1 */ - -#include <asm/arch/omap2420.h> /* get chip and board defs */ - -/* On H4, NOR and NAND flash are mutual exclusive. - Define this if you want to use NAND - */ -/*#define CONFIG_SYS_NAND_BOOT */ - -#ifdef CONFIG_APTIX -#define V_SCLK 1500000 -#else -#define V_SCLK 12000000 -#endif - -/* input clock of PLL */ -/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ -#define CONFIG_SYS_CLK_FREQ V_SCLK - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) - -/* - * Hardware drivers - */ - -/* - * SMC91c96 Etherent - */ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300) -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#ifdef CONFIG_APTIX -#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */ -#else -#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ -#endif - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ -#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on H4 */ - - /* - * I2C configuration - */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP24XX_I2C - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#ifdef CONFIG_SYS_NAND_BOOT - #define CONFIG_CMD_DHCP - #define CONFIG_CMD_I2C - #define CONFIG_CMD_NAND - #define CONFIG_CMD_JFFS2 -#else - #define CONFIG_CMD_DHCP - #define CONFIG_CMD_I2C - #define CONFIG_CMD_JFFS2 - - #undef CONFIG_CMD_SOURCE -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTDELAY 3 - -#ifdef NFS_BOOT_DEFAULTS -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" -#else -#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" -#endif - -#define CONFIG_NETMASK 255.255.254.0 -#define CONFIG_IPADDR 128.247.77.90 -#define CONFIG_SERVERIP 128.247.77.158 -#define CONFIG_BOOTFILE "uImage" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifdef CONFIG_APTIX -# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # " -#else -# define CONFIG_SYS_PROMPT "OMAP242x H4 # " -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) - -#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ - -/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. - */ -#ifdef CONFIG_APTIX -#define V_PTV 3 -#else -#define V_PTV 7 /* use with 12MHz/128 */ -#endif - -#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 -#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ -#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 - -#define PHYS_FLASH_SECT_SIZE SZ_128K -#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE_1 SZ_32M -#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ -#define PHYS_FLASH_SIZE_2 SZ_32M - -#define PHYS_SRAM 0x4020F800 -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 } - -#ifdef CONFIG_SYS_NAND_BOOT -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */ -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_256K) -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ -#endif - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_SYS_JFFS2_MEM_NAND - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=omap2420-1" -#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)" -*/ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index d6448b0529..3e5d36b21e 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -45,10 +45,6 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 38400000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - #define CONFIG_MISC_INIT_R #define CONFIG_OF_LIBFDT 1 diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index deb5e9fd5e..ddf2ad4fc2 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -45,10 +45,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -/* Clock Defines */ -#define V_OSCK 19200000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - #define CONFIG_MISC_INIT_R #define CONFIG_OF_LIBFDT @@ -81,10 +77,6 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 UART3_BASE - -#define CONFIG_BAUDRATE 115200 /* CPU */ #define CONFIG_ARCH_CPU_INIT @@ -246,6 +238,10 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PALMAS_POWER +#endif + /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 9e0339b31b..dea05bc911 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -35,10 +35,9 @@ #include <configs/omap5_common.h> -/* TWL6035 */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PALMAS_POWER -#endif +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CONFIG_BAUDRATE 115200 /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h new file mode 100644 index 0000000000..77fe893b75 --- /dev/null +++ b/include/configs/vf610twr.h @@ -0,0 +1,140 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale Vybrid vf610twr board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <config_cmd_default.h> + +#define CONFIG_VF610 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MACH_TYPE 4146 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_FSL_LPUART +#define LPUART_BASE UART1_BASE + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_UART_PORT (1) +#define CONFIG_BAUDRATE 115200 + +#undef CONFIG_CMD_IMLS + +#define CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_TEXT_BASE 0x3f008000 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > " +#undef CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80010000 +#define CONFIG_SYS_MEMTEST_END 0x87C00000 + +#define CONFIG_SYS_LOAD_ADDR 0x80010000 + +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical memory map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (128 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC + +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#endif diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 9d7ec3f6ff..5593f1c533 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -29,7 +29,7 @@ #define CONFIG_REVISION_TAG /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT @@ -86,6 +86,21 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 + #if defined(CONFIG_MX6DL) #define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb" #elif defined(CONFIG_MX6S) @@ -103,7 +118,7 @@ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \ + "mmcpart=2\0" \ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ "update_sd_firmware_filename=u-boot.imx\0" \ "update_sd_firmware=" \ @@ -217,7 +232,6 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_OFFSET (6 * 64 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ diff --git a/include/palmas.h b/include/palmas.h index 3b185896d6..aff48b5dfc 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -26,17 +26,90 @@ #include <common.h> #include <i2c.h> -/* I2C chip addresses */ -#define PALMAS_CHIP_ADDR 0x48 +/* I2C chip addresses, TW6035/37 */ +#define TWL603X_CHIP_P1 0x48 /* Page 1 */ +#define TWL603X_CHIP_P2 0x49 /* Page 2 */ +#define TWL603X_CHIP_P3 0x4a /* Page 3 */ -/* 0x1XY translates to page 1, register address 0xXY */ +/* TPS659038/39 */ +#define TPS65903X_CHIP_P1 0x58 /* Page 1 */ + +/* Page 1 registers (0x1XY translates to page 1, reg addr 0xXY): */ + +/* LDO1 control/voltage */ +#define LDO1_CTRL 0x50 +#define LDO1_VOLTAGE 0x51 + +/* LDO9 control/voltage */ #define LDO9_CTRL 0x60 #define LDO9_VOLTAGE 0x61 -/* Bit field definitions for LDOx_CTRL */ -#define LDO_ON (1 << 4) -#define LDO_MODE_SLEEP (1 << 2) -#define LDO_MODE_ACTIVE (1 << 0) +/* LDOUSB control/voltage */ +#define LDOUSB_CTRL 0x64 +#define LDOUSB_VOLTAGE 0x65 + +/* Control of 32 kHz audio clock */ +#define CLK32KGAUDIO_CTRL 0xd5 + +/* SYSEN2_CTRL for VCC_3v3_AUX supply on the sEVM */ +#define SYSEN2_CTRL 0xd9 + +/* + * Bit field definitions for LDOx_CTRL, SYSENx_CTRL + * and some other xxx_CTRL resources: + */ +#define LDO9_BYP_EN (1 << 6) /* LDO9 only! */ +#define RSC_STAT_ON (1 << 4) /* RO status bit! */ +#define RSC_MODE_SLEEP (1 << 2) +#define RSC_MODE_ACTIVE (1 << 0) + +/* Some LDO voltage values */ +#define LDO_VOLT_OFF 0 +#define LDO_VOLT_1V8 0x13 +#define LDO_VOLT_3V0 0x2b +#define LDO_VOLT_3V3 0x31 +/* Request bypass, LDO9 only */ +#define LDO9_BYPASS 0x3f + +/* SMPS7_CTRL */ +#define SMPS7_CTRL 0x30 + +/* SMPS9_CTRL */ +#define SMPS9_CTRL 0x38 +#define SMPS9_VOLTAGE 0x3b + +/* Bit field definitions for SMPSx_CTRL */ +#define SMPS_MODE_ACT_AUTO 1 +#define SMPS_MODE_ACT_ECO 2 +#define SMPS_MODE_ACT_FPWM 3 +#define SMPS_MODE_SLP_AUTO (1 << 2) +#define SMPS_MODE_SLP_ECO (2 << 2) +#define SMPS_MODE_SLP_FPWM (3 << 2) + +/* + * Some popular SMPS voltages, all with RANGE=1; note + * that RANGE cannot be changed on the fly + */ +#define SMPS_VOLT_OFF 0 +#define SMPS_VOLT_1V2 0x90 +#define SMPS_VOLT_1V8 0xae +#define SMPS_VOLT_2V1 0xbd +#define SMPS_VOLT_3V0 0xea +#define SMPS_VOLT_3V3 0xf9 + +/* Backup Battery & VRTC Control */ +#define BB_VRTC_CTRL 0xa8 +/* Bit definitions for BB_VRTC_CTRL */ +#define VRTC_EN_SLP (1 << 6) +#define VRTC_EN_OFF (1 << 5) +#define VRTC_PWEN (1 << 4) +#define BB_LOW_ICHRG (1 << 3) +#define BB_HIGH_ICHRG (0 << 3) +#define BB_VSEL_3V0 (0 << 1) +#define BB_VSEL_2V5 (1 << 1) +#define BB_VSEL_3V15 (2 << 1) +#define BB_VSEL_VBAT (3 << 1) +#define BB_CHRG_EN (1 << 0) /* * Functions to read and write from TPS659038/TWL6035/TWL6037 @@ -54,5 +127,8 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) void palmas_init_settings(void); int palmas_mmc1_poweron_ldo(void); +int twl603x_mmc1_set_ldo9(u8 vsel); +int twl603x_audio_power(u8 on); +int twl603x_enable_bb_charge(u8 bb_fields); #endif /* PALMAS_H */ diff --git a/spl/Makefile b/spl/Makefile index 8b655c485a..d8fe948ff0 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -88,7 +88,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) +ifneq (,$(CONFIG_MX23)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif @@ -98,10 +98,6 @@ LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o endif -ifneq ($(CONFIG_MX23)$(CONFIG_MX35),) -LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o -endif - # Add GCC lib ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o diff --git a/tools/Makefile b/tools/Makefile index 26eb50082f..4630f03dc5 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -130,28 +130,21 @@ LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_DATA_H) LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H) LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_DATA_H) +# Generic logo ifeq ($(LOGO_BMP),) LOGO_BMP= logos/denx.bmp + +# Use board logo and fallback to vendor +ifneq ($(wildcard logos/$(BOARD).bmp),) +LOGO_BMP= logos/$(BOARD).bmp +else +ifneq ($(wildcard logos/$(VENDOR).bmp),) +LOGO_BMP= logos/$(VENDOR).bmp endif -ifeq ($(VENDOR),atmel) -LOGO_BMP= logos/atmel.bmp -endif -ifeq ($(VENDOR),esd) -LOGO_BMP= logos/esd.bmp -endif -ifeq ($(VENDOR),freescale) -LOGO_BMP= logos/freescale.bmp -endif -ifeq ($(VENDOR),ronetix) -LOGO_BMP= logos/ronetix.bmp -endif -ifeq ($(VENDOR),syteco) -LOGO_BMP= logos/syteco.bmp -endif -ifeq ($(VENDOR),intercontrol) -LOGO_BMP= logos/intercontrol.bmp endif +endif # !LOGO_BMP + # now $(obj) is defined HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) diff --git a/tools/logos/wandboard.bmp b/tools/logos/wandboard.bmp Binary files differnew file mode 100644 index 0000000000..7f288a8e8e --- /dev/null +++ b/tools/logos/wandboard.bmp |
