diff options
| author | Jerry Huang <Chang-Ming.Huang@freescale.com> | 2010-01-15 16:52:54 +0800 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-09-29 17:32:28 -0400 |
| commit | ce5663b7342354ab98c34ae0cb77bc9f8472f7b8 (patch) | |
| tree | 502d6a8d95b9a175021bb73e0f1ac6e921ebbdd5 | |
| parent | bba7ca13f590e8122cd8c49c6b62ae836c9338a6 (diff) | |
SDHCI: fixed the clock mask and the max clock
The max clock of MMC is 52MHz, and the clock mask is wrong.
Therefore, fixed them.
Signed-off-by: Jerry Huang <Changm-Ming.Huang@freescale.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 2 | ||||
| -rw-r--r-- | include/fsl_esdhc.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9812b00e62..3c068d6a17 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -350,7 +350,7 @@ static int esdhc_initialize(bd_t *bis) mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; mmc->f_min = 400000; - mmc->f_max = MIN(gd->sdhc_clk, 50000000); + mmc->f_max = MIN(gd->sdhc_clk, 52000000); mmc_register(mmc); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89b8304d5f..eac6a2bd48 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -32,7 +32,7 @@ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 -#define SYSCTL_CLOCK_MASK 0x00000fff +#define SYSCTL_CLOCK_MASK 0x0000fff0 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 |