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authorNick Thompson <nick.thompson@ge.com>2009-12-12 17:13:10 -0500
committerSudhakar Rajashekhara <sudhakar.raj@ti.com>2010-01-14 10:36:48 +0530
commitc6669d99af36f8f43dfca8b2d2eec980ab4ae1e4 (patch)
treec0589eb2e64068d38253a29f482bb48f84ec6cee
parente91e4180f75415d17b3a3da66f71cb34e0310403 (diff)
Davinci: NAND enable ECC even when not in NAND boot mode
Davinci: NAND enable ECC even when not in NAND boot mode Davinci: NAND enable ECC even when not in NAND boot mode On Davinci platforms, the default NAND device is enabled (for ECC) in low level boot code when NAND boot mode is used. If booting in another mode, NAND ECC is not enabled. The driver should make sure ECC is enabled regardless of boot mode if NAND is configured in U-Boot. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
-rw-r--r--drivers/mtd/nand/davinci_nand.c2
-rw-r--r--include/asm-arm/arch-davinci/emif_defs.h3
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 1ad802a61d..90e038e871 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -87,6 +87,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
(void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
val = readl(&emif_regs->NANDFCR);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
writel(val, &emif_regs->NANDFCR);
}
@@ -219,6 +220,7 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
*/
val = readl(&emif_regs->NANDFCR);
val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_START;
writel(val, &emif_regs->NANDFCR);
diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h
index d67292f4b4..8fd4e01b8e 100644
--- a/include/asm-arm/arch-davinci/emif_defs.h
+++ b/include/asm-arm/arch-davinci/emif_defs.h
@@ -66,11 +66,10 @@ typedef struct {
typedef emif_registers *emifregs;
+#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2))
#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
-
#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
-
#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)