diff options
| author | David Ungar <david.ungar@timesys.com> | 2010-10-11 14:25:39 -0400 |
|---|---|---|
| committer | David Ungar <david.ungar@timesys.com> | 2010-10-11 14:39:35 -0400 |
| commit | 9b83d00ca602bcfd69497a323bcc84fec4597e56 (patch) | |
| tree | c2cdfd0da79911926d77867b0848db9c276f8916 | |
| parent | e1e13454669f4bc3756f80a216bf418ed0692215 (diff) | |
LOLO support patch
| -rw-r--r-- | cpu/arm_cortexa8/omap3/board.c | 42 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/omap3/cache.c | 4 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/start.S | 5 |
3 files changed, 32 insertions, 19 deletions
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index b8db9783b8..1e25253e0b 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -131,24 +131,32 @@ void setup_auxcr() { unsigned long i; volatile unsigned int j; - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - /* Enabling ASA */ - __asm__ __volatile__("orr r0, r0, #0x10"); - /* Enable L1NEON */ - __asm__ __volatile__("orr r0, r0, #1 << 5"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + /* Enabling ASA and L1NEON */ + i |= 0x30; + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1"::"r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + /* Enabling ASA */ + __asm__ __volatile__("orr r0, r0, #0x10"); + /* Enable L1NEON */ + __asm__ __volatile__("orr r0, r0, #1 << 5"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } } /****************************************************************************** diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c index 0d5b444be1..2c8b39f246 100644 --- a/cpu/arm_cortexa8/omap3/cache.c +++ b/cpu/arm_cortexa8/omap3/cache.c @@ -44,7 +44,7 @@ void l2_cache_enable(void) if (get_cpu_rev() >= CPU_3XX_ES20) { __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1"::"r"(i)); } else { /* Save r0, r12 and restore them after usage */ __asm__ __volatile__("mov %0, r12":"=r"(j)); @@ -74,7 +74,7 @@ void l2_cache_disable(void) if (get_cpu_rev() >= CPU_3XX_ES20) { __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1"::"r"(i)); } else { /* Save r0, r12 and restore them after usage */ __asm__ __volatile__("mov %0, r12":"=r"(j)); diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S index 6bd65521bd..61b3dc98dc 100644 --- a/cpu/arm_cortexa8/start.S +++ b/cpu/arm_cortexa8/start.S @@ -433,11 +433,16 @@ v7_flush_dcache_all: cmp r0, #0x3 @ check if the device type is @ GP moveq r12, #0x1 @ set up to invalide L2 +#ifndef CONFIG_OMAP3_LOGIC + @ On OMAP3_LOGIC boards, u-boot is launched from LoLo + @ which does the SMI call to invalidate the cache. If done + @ twice, the OMAP35x chip resets.... smi: .word 0x01600070 @ Call SMI monitor (smieq) cmp r7, #0x3 @ compare again in case its @ lost beq finished_inval @ if GP device, inval done @ above +#endif mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr |