ENGR00229456 Support for 64bit DDR configuration for ARD

Added support for 64bit DDR configuration
on DL chip. On ARD platform

Signed-off-by: Alejandro Sierra <b18039@freescale.com>

9 files changed, 125 insertions, 16 deletions

diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S
index 498e14783d..3aa195dc06 100644
--- a/board/freescale/mx6q_sabreauto/flash_header.S
+++ b/board/freescale/mx6q_sabreauto/flash_header.S
@@ -321,6 +321,123 @@ MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0)
 
 MXC_DCD_ITEM(125, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
 
+#elif defined CONFIG_MX6DL_DDR3
+
+dcd_hdr:          .word 0x40B002D2 /* Tag=0xD2, Len=85*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x04AC02CC /* Tag=0xCC, Len=85*8 + 4, Param=0x04 */
+
+# IOMUXC_BASE_ADDR  = 0x20e0000
+# DDR IO TYPE
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
+# Clock
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
+# Address
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
+# Control
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4, 0x00000030)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8, 0x00000030)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
+# Data Strobe
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00000000)
+
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc, 0x00000028)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0, 0x00000028)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4c4, 0x00000028)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c8, 0x00000028)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4cc, 0x00000028)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4d0, 0x00000028)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4d4, 0x00000028)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d8, 0x00000028)
+# DATA
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x760, 0x00000000)
+
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x764, 0x00000028)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x770, 0x00000028)
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x778, 0x00000028)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x77c, 0x00000028)
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x780, 0x00000028)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000028)
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x78c, 0x00000028)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x748, 0x00000028)
+
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x470, 0x00000028)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x474, 0x00000028)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x478, 0x00000028)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x47c, 0x00000028)
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x480, 0x00000028)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x484, 0x00000028)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x488, 0x00000028)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x48c, 0x00000028)
+# MMDC_P0_BASE_ADDR = 0x021b0000
+# MMDC_P1_BASE_ADDR = 0x021b4000
+# Calibrations
+# ZQ
+MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
+# write leveling
+MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
+MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
+# DQS gating, read delay, write delay calibration values
+# based on calibration compare of 0x00ffff00
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42120218)
+MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x02030203)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x4302031A)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x027B0249)
+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4A494C4A)
+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x3A373345)
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3F36)
+MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x48334736)
+# read data bit delay
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+# Complete calibration by forced measurment
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+# MMDC init:
+# in DDR3, 64-bit mode, only MMDC0 is initiated:
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x004, 0x00020025)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
+
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x00c, 0x676B5313)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8B63)
+
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x030, 0x006B1023)
+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x400, 0x11420000)
+MXC_DCD_ITEM(73, MMDC_P1_BASE_ADDR + 0x400, 0x11420000)
+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
+
+# Initialize 2GB DDR3 - Micron MT41J128M
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x05208030)
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+# final DDR setup
+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x004, 0x00025565)
+MXC_DCD_ITEM(84, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)
+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+
 #else
 
 dcd_hdr:          .word 0x40B002D2 /* Tag=0xD2, Len=85*8 + 4 + 4, Ver=0x40 */
diff --git a/include/configs/mx6dl_sabreauto.h b/include/configs/mx6dl_sabreauto.h
index 1288947000..f92d14c4cf 100644
--- a/include/configs/mx6dl_sabreauto.h
+++ b/include/configs/mx6dl_sabreauto.h
@@ -28,8 +28,7 @@
 #define CONFIG_ARMV7	/* This is armv7 Cortex-A9 CPU core */
 #define CONFIG_MXC
 #define CONFIG_MX6DL
-#define CONFIG_MX6SOLO_DDR3
-#define CONFIG_DDR_32BIT
+#define CONFIG_MX6DL_DDR3
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
 #define CONFIG_FLASH_HEADER_OFFSET 0x400
diff --git a/include/configs/mx6dl_sabreauto_mfg.h b/include/configs/mx6dl_sabreauto_mfg.h
index d7c0c5682b..ae2af4606e 100644
--- a/include/configs/mx6dl_sabreauto_mfg.h
+++ b/include/configs/mx6dl_sabreauto_mfg.h
@@ -29,8 +29,7 @@
 #define CONFIG_ARMV7	/* This is armv7 Cortex-A9 CPU core */
 #define CONFIG_MXC
 #define CONFIG_MX6DL
-#define CONFIG_MX6SOLO_DDR3
-#define CONFIG_DDR_32BIT
+#define CONFIG_MX6DL_DDR3
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
 #define CONFIG_FLASH_HEADER_OFFSET 0x400
diff --git a/include/configs/mx6dl_sabreauto_nand.h b/include/configs/mx6dl_sabreauto_nand.h
index 0570841049..9ee9c03f42 100644
--- a/include/configs/mx6dl_sabreauto_nand.h
+++ b/include/configs/mx6dl_sabreauto_nand.h
@@ -28,8 +28,7 @@
 #define CONFIG_ARMV7	/* This is armv7 Cortex-A9 CPU core */
 #define CONFIG_MXC
 #define CONFIG_MX6DL
-#define CONFIG_MX6SOLO_DDR3
-#define CONFIG_DDR_32BIT
+#define CONFIG_MX6DL_DDR3
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
 #define CONFIG_FLASH_HEADER_OFFSET 0x400
diff --git a/include/configs/mx6dl_sabreauto_nand_mfg.h b/include/configs/mx6dl_sabreauto_nand_mfg.h
index b3e2972e4c..4592a80e00 100644
--- a/include/configs/mx6dl_sabreauto_nand_mfg.h
+++ b/include/configs/mx6dl_sabreauto_nand_mfg.h
@@ -29,8 +29,7 @@
 #define CONFIG_ARMV7	/* This is armv7 Cortex-A9 CPU core */
 #define CONFIG_MXC
 #define CONFIG_MX6DL
-#define CONFIG_MX6SOLO_DDR3
-#define CONFIG_DDR_32BIT
+#define CONFIG_MX6DL_DDR3
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
 #define CONFIG_FLASH_HEADER_OFFSET 0x400
diff --git a/include/configs/mx6dl_sabreauto_spi-nor.h b/include/configs/mx6dl_sabreauto_spi-nor.h
index 93d33702de..d04a99f4ae 100644
--- a/include/configs/mx6dl_sabreauto_spi-nor.h
+++ b/include/configs/mx6dl_sabreauto_spi-nor.h
@@ -28,8 +28,7 @@
 #define CONFIG_ARMV7	/* This is armv7 Cortex-A9 CPU core */
 #define CONFIG_MXC
 #define CONFIG_MX6DL
-#define CONFIG_MX6SOLO_DDR3
-#define CONFIG_DDR_32BIT
+#define CONFIG_MX6DL_DDR3
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
 #define CONFIG_FLASH_HEADER_OFFSET 0x400
diff --git a/include/configs/mx6dl_sabreauto_spi-nor_mfg.h b/include/configs/mx6dl_sabreauto_spi-nor_mfg.h
index 8ad6b717c0..d8cbf75096 100644
--- a/include/configs/mx6dl_sabreauto_spi-nor_mfg.h
+++ b/include/configs/mx6dl_sabreauto_spi-nor_mfg.h
@@ -29,8 +29,7 @@
 #define CONFIG_ARMV7	/* This is armv7 Cortex-A9 CPU core */
 #define CONFIG_MXC
 #define CONFIG_MX6DL
-#define CONFIG_MX6SOLO_DDR3
-#define CONFIG_DDR_32BIT
+#define CONFIG_MX6DL_DDR3
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
 #define CONFIG_FLASH_HEADER_OFFSET 0x400
diff --git a/include/configs/mx6dl_sabreauto_weimnor.h b/include/configs/mx6dl_sabreauto_weimnor.h
index 10bc0edd9d..bbe87a1ec5 100644
--- a/include/configs/mx6dl_sabreauto_weimnor.h
+++ b/include/configs/mx6dl_sabreauto_weimnor.h
@@ -28,8 +28,7 @@
 #define CONFIG_ARMV7	/* This is armv7 Cortex-A9 CPU core */
 #define CONFIG_MXC
 #define CONFIG_MX6DL
-#define CONFIG_MX6SOLO_DDR3
-#define CONFIG_DDR_32BIT
+#define CONFIG_MX6DL_DDR3
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
 #define CONFIG_MX6_CLK32	   32768
diff --git a/include/configs/mx6dl_sabreauto_weimnor_mfg.h b/include/configs/mx6dl_sabreauto_weimnor_mfg.h
index 52012234c4..1965985a2a 100644
--- a/include/configs/mx6dl_sabreauto_weimnor_mfg.h
+++ b/include/configs/mx6dl_sabreauto_weimnor_mfg.h
@@ -29,8 +29,7 @@
 #define CONFIG_ARMV7	/* This is armv7 Cortex-A9 CPU core */
 #define CONFIG_MXC
 #define CONFIG_MX6DL
-#define CONFIG_MX6SOLO_DDR3
-#define CONFIG_DDR_32BIT
+#define CONFIG_MX6DL_DDR3
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
 #define CONFIG_FLASH_HEADER_OFFSET 0x400