ENGR00214866 MX6SL ARM2, UBoot : Apply V0.91 LPDDR2 Script

Validation team released lateset LPDDR2 script V0.91, See
"http://compass.freescale.net/livelink/livelin
k?func=ll&objId=226435628&objAction=browse&viewType=1"
This change is necessary for bus freq scaling

Apply it for both DCD mode and plugin mode.

Signed-off-by: Eric Sun <jian.sun@freescale.com>

1 files changed, 397 insertions, 463 deletions

diff --git a/board/freescale/mx6sl_arm2/flash_header.S b/board/freescale/mx6sl_arm2/flash_header.S
index 5ff908f3cb..4348cb3893 100644
--- a/board/freescale/mx6sl_arm2/flash_header.S
+++ b/board/freescale/mx6sl_arm2/flash_header.S
@@ -66,32 +66,36 @@ write_dcd_cmd:    .word 0x044402CC /* Tag=0xCC, Len=72*8 + 4, Param=0x04 */
 /*========================================================================*/
 /* Revision History*/
 /* v0.1 : Init pre-silicon version for Samsung K4P8G304EB-AGC1 on CPU LPDDR2
-   board. It's currently soldered, not PoPed.*/
+          board. It's currently soldered, not PoPed.*/
 /* v0.2 : CCM, IO, LPDDR_2ch config fixed*/
 
 /* If someone is playing this init on different DDR device, or on PoPed board,
    please feedback me with result.*/
 /* boaz.perlman@freescale.com*/
+
+/* v0.9 : RALAT 5->3 (improved operation at low freq). CK_FT0_DCC=CK_FT1_DCC=1
+          (Improved SDCLK signal shape)*/
+/* v0.91 : IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0/1 programming is removed, as this
+           got no effect on SDCKE drive strength, pull activiticy.*/
 /*========================================================================*/
 
-/* wait = on*/
+/*wait = on*/
 /*========================================================================*/
 /* Disable	WDOG*/
 /*========================================================================*/
 /*setmem /16	0x020bc000 =	0x30*/
 
-
 /*========================================================================*/
 /* Enable all clocks (they are disabled by ROM code)*/
 /*========================================================================*/
-/* setmem /32	0x020c4068 =	0xffffffff*/
-/* setmem /32	0x020c406c =	0xffffffff*/
-/* setmem /32	0x020c4070 =	0xffffffff*/
-/* setmem /32	0x020c4074 =	0xffffffff*/
-/* setmem /32	0x020c4078 =	0xffffffff*/
-/* setmem /32	0x020c407c =	0xffffffff*/
-/* setmem /32	0x020c4080 =	0xffffffff*/
-/* setmem /32	0x020c4084 =	0xffffffff*/
+/*setmem /32	0x020c4068 =	0xffffffff*/
+/*setmem /32	0x020c406c =	0xffffffff*/
+/*setmem /32	0x020c4070 =	0xffffffff*/
+/*setmem /32	0x020c4074 =	0xffffffff*/
+/*setmem /32	0x020c4078 =	0xffffffff*/
+/*setmem /32	0x020c407c =	0xffffffff*/
+/*setmem /32	0x020c4080 =	0xffffffff*/
+/*setmem /32	0x020c4084 =	0xffffffff*/
 
 /*DDR clk to 400MHz*/
 /*CCM_BASE_ADDR = 0x020c4000*/
@@ -100,74 +104,70 @@ MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x018, 0x00260324)
 /*========================================================================*/
 /* IOMUX*/
 /*========================================================================*/
-/* Megrez note: IOMUX configs specify absolute addr in Arik IOMUXC.
-   Changes to Megrez addr.*/
+/* Megrez note: IOMUX configs specify absolute addr in Arik IOMUXC. Changes to
+   Megrez addr.*/
 /* Megrez note: Good chance that drive strength change is required. to change
    them all by editing the LSB value "38"-> ""30" or "28"*/
 /* Megrez note: Timing also can be tweaked by drive strength values. It is
-   mainly by giving SDCLk and SDQS different values than the sampled
-   signals*/
+   mainly by giving SDCLk and SDQS different values than the sampled signals*/
 
-/* IOMUXC_BASE_ADDR = 0x020e0000*/
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0*/
+/*IOMUXC_BASE_ADDR = 0x020e0000*/
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0*/
 MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x344, 0x00003030)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1*/
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1*/
 MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x348, 0x00003030)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2*/
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2*/
 MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x34c, 0x00003030)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3*/
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3*/
 MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x350, 0x00003030)
 
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0*/
-MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x30c, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1*/
-MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x310, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2*/
-MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x314, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3*/
-MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x318, 0x00000038)
-
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS*/
-MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x300, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS*/
-MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x31c, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0*/
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0*/
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x30c, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1*/
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x310, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2*/
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x314, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3*/
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x318, 0x00000030)
+
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS*/
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x300, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS*/
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x31c, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0*/
 MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x338, 0x00000030)
 
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET*/
-MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x320, 0x00080038)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0*/
-MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x330, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1*/
-MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x334, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group
-   Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS*/
-MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x32c, 0x00000000)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0*/
-MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x33c, 0x00000008)
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1*/
-MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x340, 0x00000008)
-/* IOMUXC_SW_PAD_CTL_GRP_B0DS*/
-MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_GRP_B1DS*/
-MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x5cc, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_GRP_B2DS*/
-MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x5d4, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_GRP_B3DS*/
-MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5d8, 0x00000038)
-
-/* IOMUXC_SW_PAD_CTL_GRP_ADDDS*/
-MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_GRP_CTLDS*/
-MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x5c8, 0x00000038)
-/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL*/
-MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x5b0, 0x00020000)
-/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE*/
-MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5b4, 0x00000000)
-/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE*/
-MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5c0, 0x00020000)
-/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE*/
-MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x5d0, 0x00080000)
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET*/
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x320, 0x00080030)
+
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control
+  Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS*/
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x32c, 0x00000000)
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0*/
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x33c, 0x00000008)
+/*IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1*/
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x340, 0x00000008)
+/*IOMUXC_SW_PAD_CTL_GRP_B0DS*/
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_GRP_B1DS*/
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x5cc, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_GRP_B2DS*/
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x5d4, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_GRP_B3DS*/
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x5d8, 0x00000030)
+
+/*IOMUXC_SW_PAD_CTL_GRP_ADDDS*/
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_GRP_CTLDS*/
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5c8, 0x00000030)
+/*IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL*/
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5b0, 0x00020000)
+/*IOMUXC_SW_PAD_CTL_GRP_DDRPKE*/
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x5b4, 0x00000000)
+/*IOMUXC_SW_PAD_CTL_GRP_DDRMODE*/
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x5c0, 0x00020000)
+/*IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE*/
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5d0, 0x00080000)
 
 /*========================================================================*/
 /* DDR Controller Registers*/
@@ -183,180 +183,184 @@ MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x5d0, 0x00080000)
 /* Column address: 	10*/
 /* Data bus width	32*/
 /*========================================================================*/
-/* MMDC_P0_BASE_ADDR = 0x021b0000*/
-/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up*/
-MXC_DCD_ITEM(29, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+/*MMDC_P0_BASE_ADDR = 0x021b0000*/
+/*MMDC0_MDSCR, set the Configuration request bit during MMDC set up*/
+MXC_DCD_ITEM(27, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
 
-/*LPDDR2 ZQ params*/
 /*setmem /32      0x021b085c = 0x1b5f01ff*/
 /*LPDDR2 ZQ params*/
-MXC_DCD_ITEM(30, MMDC_P0_BASE_ADDR + 0x85c, 0x1b4700c7)
+/*LPDDR2 ZQ params*/
+MXC_DCD_ITEM(28, MMDC_P0_BASE_ADDR + 0x85c, 0x1b4700c7)
 
 /*========================================================================*/
 /* Calibration setup.*/
 /**/
 /*========================================================================*/
 
-/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration*/
-MXC_DCD_ITEM(31, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
+/*DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration*/
+MXC_DCD_ITEM(29, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
 
-/* Megrez note: If entire word fails, CA bus might be involved. Try
-   changing this:*/
+/* Megrez note: If entire word fails, CA bus might be involved. Try changing
+   this:*/
 /*ca bus abs delay*/
-MXC_DCD_ITEM(32, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
+MXC_DCD_ITEM(30, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
 
 /* values of 20,40,50,60,7f tried. no difference seen*/
 
 /* Megrez note: This is also for CA bus. A bit-bit fine tuning.*/
-/* DDR_PHY_P1_MPWRCADL*/
 /*setmem /32	0x021b48bc =	0x00055555*/
+/*DDR_PHY_P1_MPWRCADL*/
 
 /*frc_msr.*/
-MXC_DCD_ITEM(33, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(31, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
 
-/* DDR_PHY_P0_MPREDQBY0DL3*/
-MXC_DCD_ITEM(34, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
-/* DDR_PHY_P0_MPREDQBY1DL3*/
-MXC_DCD_ITEM(35, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
-/* DDR_PHY_P0_MPREDQBY2DL3*/
-MXC_DCD_ITEM(36, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
-/* DDR_PHY_P0_MPREDQBY3DL3*/
-MXC_DCD_ITEM(37, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+/*DDR_PHY_P0_MPREDQBY0DL3*/
+MXC_DCD_ITEM(32, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+/*DDR_PHY_P0_MPREDQBY1DL3*/
+MXC_DCD_ITEM(33, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+/*DDR_PHY_P0_MPREDQBY2DL3*/
+MXC_DCD_ITEM(34, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+/*DDR_PHY_P0_MPREDQBY3DL3*/
+MXC_DCD_ITEM(35, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
 
 /*write delayes:*/
 /*all byte 0 data & dm delayed by 3*/
-MXC_DCD_ITEM(38, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
+MXC_DCD_ITEM(36, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
 /*all byte 1 data & dm delayed by 3*/
-MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
+MXC_DCD_ITEM(37, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
 /*all byte 2 data & dm delayed by 3*/
-MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
+MXC_DCD_ITEM(38, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
 /*all byte 3 data & dm delayed by 3*/
-MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
+MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
 
 /* Read and write data delay, per byte.*/
-/* For optimized DDR operation it is recommended to run mmdc_calibration on
-   your board, and replace 4 delay register assigns with resulted values*/
+/* For optimized DDR operation it is recommended to run mmdc_calibration on your
+   board, and replace 4 delay register assigns with resulted values*/
 /* Note:*/
 /* a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
-   should be skipped, or the write/read calibration comming after
-   that will stall*/
+   should be skipped, or the write/read calibration comming after that will
+   stall*/
 /* b. The calibration code that runs for both MMDC0 & MMDC1 should be used.*/
 
-/*it is strongly recommended to run calibration on your board,
-  and replace bellow values:*/
+/*it is strongly recommended to run calibration on your board, and replace
+  bellow values:*/
 
-/* Megrez note: New set of values is required for the following 2
-   delay registers. Try running calibration code as in Arik APN.*/
+/* Megrez note: New set of values is required for the following 2 delay
+   registers. Try running calibration code as in Arik APN.*/
 
 /*Read calibration*/
-MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x848, 0x4241444a)
+MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x848, 0x4241444a)
 
 /*Write calibration*/
-MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x850, 0x3030312b)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x850, 0x3030312b)
 
 /*dqs gating dis*/
-MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
-MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x0)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x840, 0x00000000)
 
-/* Megrez note: Try enabling and changing the clock
-   delay, as part of the calibration:*/
-/*clk delay*/
+/* Megrez note: Try enabling and changing the clock delay, as part of the
+   calibration:*/
 /*setmem /32 0x021b0858 = 0xa00*/
+/*clk delay*/
+
+/*fine tune duty cyc to low*/
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x8c0, 0x24911492)
 
 /*frc_msr*/
-MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
 
 /*========================================================================*/
 /* Calibration setup end*/
 /*========================================================================*/
+
 /* Channel0 - startng address 0x80000000*/
 
-/* MMDC0_MDCFG0*/
 /*setmem /32	0x021b000c =	0x3f436133*/
 /* MMDC0_MDCFG0*/
-MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x00c, 0x33374133)
-/* MMDC0_MDPDC*/
-MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x004, 0x00020024)
-/* MMDC0_MDCFG1*/
-MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x010, 0x00100A82)
-/* MMDC0_MDCFG2*/
-MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x014, 0x00000093)
-
-/* MMDC0_MDMISC*/
-MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x018, 0x00001748)
-/* MMDC0_MDRWD;*/
-MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x02c, 0x0f9f26d2)
-/* MMDC0_MDOR*/
-MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x030, 0x0000020e)
+/*MMDC0_MDCFG0*/
+MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x00c, 0x33374133)
+/*MMDC0_MDPDC - where is tCKSRX and tCKSRE defined in LPDDR2 data sheet?????*/
+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x004, 0x00020024)
+/*MMDC0_MDCFG1*/
+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x010, 0x00100A82)
+/*MMDC0_MDCFG2*/
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x014, 0x00000093)
+
+/*MMDC0_MDMISC. RALAT=3. Try increasing RALAT if case of failures at higher DDR
+  freq*/
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x018, 0x000016c8)
+/*MMDC0_MDRWD;*/
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x02c, 0x0f9f26d2)
+/*MMDC0_MDOR*/
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x030, 0x0000020e)
 
-/* MMDC0_MDCFG3LP*/
 /*setmem /32	0x021b0038 =	0x001a099a*/
 /* MMDC0_MDCFG3LP*/
-MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x038, 0x00190778)
-/* MMDC0_MDOTC*/
-MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x008, 0x00000000)
+/*MMDC0_MDCFG3LP*/
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x038, 0x00190778)
+/*MMDC0_MDOTC*/
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x008, 0x00000000)
 
-/* CS0_END = 0x8fffffff*/
-MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x040, 0x0000004f)
+/*CS0_END = 0x8fffffff*/
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x040, 0x0000004f)
 
-/* MMDC0_MDCTL*/
-MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x000, 0xc3110000)
+/*MMDC0_MDCTL*/
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x000, 0xc3110000)
 
 /* Channel0 : Configure DDR device:*/
-/* Megrez note: Device drive strength change might help,
-   consult device/JEDEC for the values.*/
-/*reset*/
-/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0*/
-MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x01c, 0x003f8030)
-/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff /zq*/
-MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8030)
-/* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=c2*/
-MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x82018030)
-/* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=4. tcl=6, tcwl=3*/
-MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x04028030)
-/* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6*/
-MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x02038030)
-/*reset*/
-/* MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0*/
+/* Megrez note: Device drive strength change might help, consult device/JEDEC
+   for the values.*/
+
+/*MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0  //reset*/
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x01c, 0x003f8030)
+/*MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff /zq*/
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8030)
+/*MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=c2*/
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x01c, 0x82018030)
+/*MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=4. tcl=6, tcwl=3*/
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04028030)
+/*MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6*/
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x02038030)
+
+/* Need to comment out MRW reset command to CS1 - investigating this*/
+/* Also, adding delays before and after this makes no difference*/
 /*setmem /32 0x021b001c = 0x003f8038*/
-/* MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff*/
-MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8038)
-/* MRW: BA=0 CS=1 MR_ADDR=1  MR_OP=c2*/
-MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x82018038)
-/* MRW: BA=0 CS=1 MR_ADDR=2  MR_OP=4. tcl=6, tcwl=3*/
-MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x04028038)
-/* MRW: BA=0 CS=1 MR_ADDR=3  MR_OP=2.drive=240/6*/
-MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x02038038)
-
-/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration*/
-/*setmem /32	0x021b0800 =	0xa1390000*/
-
-/* MMDC0_MDREF*/
-MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x020, 0x00007800)
-
-/* DDR_PHY_P0_MPODTCTRL*/
-MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x818, 0x0)
+/* MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0*/
+/*reset*/
+/*MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff*/
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8038)
+/*MRW: BA=0 CS=1 MR_ADDR=1  MR_OP=c2*/
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x82018038)
+/*MRW: BA=0 CS=1 MR_ADDR=2  MR_OP=4. tcl=6, tcwl=3*/
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x04028038)
+/*MRW: BA=0 CS=1 MR_ADDR=3  MR_OP=2.drive=240/6*/
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x02038038)
 
 /*######################################################*/
-/*calibration values based on calibration compare of 0x00ffff00:*/
-/*Note, these calibration values are based on Freescale's board*/
-/*May need to run calibration on target board to fine tune these*/
-/*######################################################*/
+/*final DDR setup, before operation start:*/
+/*DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration*/
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x800, 0xa1310003)
+
+/*MMDC0_MDREF*/
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x020, 0x00007800)
 
-/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration*/
-MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x800, 0xa1310003)
-/* du /32 0x021b0800*/
-/* du /32 0x021b0800*/
+/*DDR_PHY_P0_MPODTCTRL*/
+/*setmem /32	0x021b0818 =	0*/
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x818, 0x00000000)
 
-/* DDR_PHY_P0_MPMUR0, frc_msr*/
-MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+/*DDR_PHY_P0_MPMUR0, frc_msr*/
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
 
-/* MMDC0_MDSCR, clear this register (especially the configuration bit as
-   initialization is complete)*/
-MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+/*MMDC0_MDPDC now SDCTL power down enabled*/
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x004, 0x00025564)
 
-/* DDR_PHY_P0_MPMUR0, frc_msr*/
-MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+/*MMDC0_MAPSR ADOPT power down enabled*/
+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+/*MMDC0_MDSCR, clear this register (especially the configuration bit as
+  initialization is complete)*/
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
 /*###################put the ddr script here ######################*/
 
 #else
@@ -401,311 +405,241 @@ plugin_start:
 
 /*
  * The following is following Megrez LPDDR init script
- * Ver 0.7
+ * Ver 0.91
  */
-
 /*
  * CCM Configuration
  */
-    ldr r0, =CCM_BASE_ADDR
-
+	ldr r0, =CCM_BASE_ADDR
 /*MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x018, 0x00260324)*/
-    ldr r1, =0x00260324
-    str r1, [r0,#0x18]
-
+	ldr r1, =0x00260324
+	str r1, [r0, #0x018]
 
 /*
  * IOMUX Configuration
  */
-    ldr r0, =IOMUXC_BASE_ADDR
+	ldr r0, =IOMUXC_BASE_ADDR
 /*MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x344, 0x00003030)*/
-    ldr r1, =0x00003030
-    str r1, [r0, #0x344]
-
+	ldr r1, =0x00003030
+	str r1, [r0, #0x344]
 /*MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x348, 0x00003030)*/
-    ldr r1, =0x00003030
-    str r1, [r0, #0x348]
-
+	ldr r1, =0x00003030
+	str r1, [r0, #0x348]
 /*MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x34c, 0x00003030)*/
-    ldr r1, =0x00003030
-    str r1, [r0, #0x34c]
-
+	ldr r1, =0x00003030
+	str r1, [r0, #0x34c]
 /*MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x350, 0x00003030)*/
-    ldr r1, =0x00003030
-    str r1, [r0, #0x350]
-
-/*MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x30c, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x30c]
-
-/*MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x310, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x310]
-
-/*MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x314, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x314]
-
-/*MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x318, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x318]
-
-/*MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x300, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x300]
-
-/*MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x31c, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x31c]
-
+	ldr r1, =0x00003030
+	str r1, [r0, #0x350]
+/*MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x30c, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x30c]
+/*MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x310, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x310]
+/*MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x314, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x314]
+/*MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x318, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x318]
+/*MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x300, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x300]
+/*MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x31c, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x31c]
 /*MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x338, 0x00000030)*/
-    ldr r1, =0x00000030
-    str r1, [r0, #0x338]
-
-/*MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x320, 0x00080038)*/
-    ldr r1, =0x00080038
-    str r1, [r0, #0x320]
-
-/*MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x330, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x330]
-
-/*MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x334, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x334]
-
-/*MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x32c, 0x00000000)*/
-    ldr r1, =0x00000000
-    str r1, [r0, #0x32c]
-
-/*MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x33c, 0x00000008)*/
-    ldr r1, =0x00000008
-    str r1, [r0, #0x33c]
-
-/*MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x340, 0x00000008)*/
-    ldr r1, =0x00000008
-    str r1, [r0, #0x340]
-
-/*MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x5c4]
-
-/*MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x5cc, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x5cc]
-
-/*MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x5d4, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x5d4]
-
-/*MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5d8, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x5d8]
-
-/*MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x5ac]
-
-/*MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x5c8, 0x00000038)*/
-    ldr r1, =0x00000038
-    str r1, [r0, #0x5c8]
-
-/*MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x5b0, 0x00020000)*/
-    ldr r1, =0x00020000
-    str r1, [r0, #0x5b0]
-
-/*MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5b4, 0x00000000)*/
-    ldr r1, =0x00000000
-    str r1, [r0, #0x5b4]
-
-/*MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5c0, 0x00020000)*/
-    ldr r1, =0x00020000
-    str r1, [r0, #0x5c0]
-
-/*MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x5d0, 0x00080000)*/
-    ldr r1, =0x00080000
-    str r1, [r0, #0x5d0]
-
+	ldr r1, =0x00000030
+	str r1, [r0, #0x338]
+/*MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x320, 0x00080030)*/
+	ldr r1, =0x00080030
+	str r1, [r0, #0x320]
+/*MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x32c, 0x00000000)*/
+	ldr r1, =0x00000000
+	str r1, [r0, #0x32c]
+/*MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x33c, 0x00000008)*/
+	ldr r1, =0x00000008
+	str r1, [r0, #0x33c]
+/*MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x340, 0x00000008)*/
+	ldr r1, =0x00000008
+	str r1, [r0, #0x340]
+/*MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5c4]
+/*MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x5cc, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5cc]
+/*MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x5d4, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5d4]
+/*MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x5d8, 0x00000030)*/
+	ldr r1, =0x00000030 str r1, [r0, #0x5d8]
+/*MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5ac]
+/*MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5c8, 0x00000030)*/
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5c8]
+/*MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5b0, 0x00020000)*/
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5b0]
+/*MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x5b4, 0x00000000)*/
+	ldr r1, =0x00000000
+	str r1, [r0, #0x5b4]
+/*MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x5c0, 0x00020000)*/
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5c0]
+/*MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5d0, 0x00080000)*/
+	ldr r1, =0x00080000
+	str r1, [r0, #0x5d0]
 
 /*
  * MMDC Configuration
  */
-    ldr r0, =MMDC_P0_BASE_ADDR
-/*MXC_DCD_ITEM(29, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)*/
-    ldr r1, =0x00008000
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(30, MMDC_P0_BASE_ADDR + 0x85c, 0x1b4700c7)*/
-    ldr r1, =0x1b4700c7
-    str r1, [r0, #0x85c]
-
-/*MXC_DCD_ITEM(31, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)*/
-    ldr r1, =0xa1390003
-    str r1, [r0, #0x800]
-
-/*MXC_DCD_ITEM(32, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)*/
-    ldr r1, =0x00400000
-    str r1, [r0, #0x890]
-
-/*MXC_DCD_ITEM(33, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)*/
-    ldr r1, =0x00000800
-    str r1, [r0, #0x8b8]
-
-/*MXC_DCD_ITEM(34, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)*/
-    ldr r1, =0x33333333
-    str r1, [r0, #0x81c]
-
-/*MXC_DCD_ITEM(35, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)*/
-    ldr r1, =0x33333333
-    str r1, [r0, #0x820]
-
-/*MXC_DCD_ITEM(36, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)*/
-    ldr r1, =0x33333333
-    str r1, [r0, #0x824]
-
-/*MXC_DCD_ITEM(37, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)*/
-    ldr r1, =0x33333333
-    str r1, [r0, #0x828]
-
-/*MXC_DCD_ITEM(38, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)*/
-    ldr r1, =0xf3333333
-    str r1, [r0, #0x82c]
-
-/*MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)*/
-    ldr r1, =0xf3333333
-    str r1, [r0, #0x830]
-
-/*MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)*/
-    ldr r1, =0xf3333333
-    str r1, [r0, #0x834]
-
-/*MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)*/
-    ldr r1, =0xf3333333
-    str r1, [r0, #0x838]
-
-/*MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x848, 0x4241444a)*/
-    ldr r1, =0x4241444a
-    str r1, [r0, #0x848]
-
-/*MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x850, 0x3030312b)*/
-    ldr r1, =0x3030312b
-    str r1, [r0, #0x850]
-
-/*MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)*/
-    ldr r1, =0x20000000
-    str r1, [r0, #0x83c]
-
-/*MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x0)*/
-    ldr r1, =0x0
-    str r1, [r0, #0x840]
-
-/*MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)*/
-    ldr r1, =0x00000800
-    str r1, [r0, #0x8b8]
-
-/*MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x00c, 0x33374133)*/
-    ldr r1, =0x33374133
-    str r1, [r0, #0x00c]
-
-/*MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x004, 0x00020024)*/
-    ldr r1, =0x00020024
-    str r1, [r0, #0x004]
-
-/*MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x010, 0x00100A82)*/
-    ldr r1, =0x00100A82
-    str r1, [r0, #0x010]
-
-/*MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x014, 0x00000093)*/
-    ldr r1, =0x00000093
-    str r1, [r0, #0x014]
-
-/*MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x018, 0x00001748)*/
-    ldr r1, =0x00001748
-    str r1, [r0, #0x018]
-
-/*MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x02c, 0x0f9f26d2)*/
-    ldr r1, =0x0f9f26d2
-    str r1, [r0, #0x02c]
-
-/*MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x030, 0x0000020e)*/
-    ldr r1, =0x0000020e
-    str r1, [r0, #0x030]
-
-/*MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x038, 0x00190778)*/
-    ldr r1, =0x00190778
-    str r1, [r0, #0x038]
-
-/*MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x008, 0x00000000)*/
-    ldr r1, =0x00000000
-    str r1, [r0, #0x008]
-
-/*MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x040, 0x0000004f)*/
-    ldr r1, =0x0000004f
-    str r1, [r0, #0x040]
-
-/*MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x000, 0xc3110000)*/
-    ldr r1, =0xc3110000
-    str r1, [r0, #0x000]
-
-/*MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x01c, 0x003f8030)*/
-    ldr r1, =0x003f8030
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8030)*/
-    ldr r1, =0xff0a8030
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x82018030)*/
-    ldr r1, =0x82018030
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x04028030)*/
-    ldr r1, =0x04028030
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x02038030)*/
-    ldr r1, =0x02038030
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8038)*/
-    ldr r1, =0xff0a8038
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x82018038)*/
-    ldr r1, =0x82018038
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x04028038)*/
-    ldr r1, =0x04028038
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x02038038)*/
-    ldr r1, =0x02038038
-    str r1, [r0, #0x01c]
-
+	ldr r0, =MMDC_P0_BASE_ADDR
+/*MXC_DCD_ITEM(27, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)*/
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(28, MMDC_P0_BASE_ADDR + 0x85c, 0x1b4700c7)*/
+	ldr r1, =0x1b4700c7
+	str r1, [r0, #0x85c]
+/*MXC_DCD_ITEM(29, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)*/
+	ldr r1, =0xa1390003
+	str r1, [r0, #0x800]
+/*MXC_DCD_ITEM(30, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)*/
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+/*MXC_DCD_ITEM(31, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)*/
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+/*MXC_DCD_ITEM(32, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)*/
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+/*MXC_DCD_ITEM(33, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)*/
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+/*MXC_DCD_ITEM(34, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)*/
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+/*MXC_DCD_ITEM(35, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)*/
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+/*MXC_DCD_ITEM(36, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)*/
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x82c]
+/*MXC_DCD_ITEM(37, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)*/
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x830]
+/*MXC_DCD_ITEM(38, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)*/
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x834]
+/*MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)*/
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x838]
+/*MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x848, 0x4241444a)*/
+	ldr r1, =0x4241444a
+	str r1, [r0, #0x848]
+/*MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x850, 0x3030312b)*/
+	ldr r1, =0x3030312b
+	str r1, [r0, #0x850]
+/*MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)*/
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+/*MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x840, 0x00000000)*/
+	ldr r1, =0x00000000
+	str r1, [r0, #0x840]
+/*MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x8c0, 0x24911492)*/
+	ldr r1, =0x24911492
+	str r1, [r0, #0x8c0]
+/*MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)*/
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+/*MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x00c, 0x33374133)*/
+	ldr r1, =0x33374133
+	str r1, [r0, #0x00c]
+/*MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x004, 0x00020024)*/
+	ldr r1, =0x00020024
+	str r1, [r0, #0x004]
+/*MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x010, 0x00100A82)*/
+	ldr r1, =0x00100A82
+	str r1, [r0, #0x010]
+/*MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x014, 0x00000093)*/
+	ldr r1, =0x00000093
+	str r1, [r0, #0x014]
+/*MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x018, 0x000016c8)*/
+	ldr r1, =0x000016c8
+	str r1, [r0, #0x018]
+/*MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x02c, 0x0f9f26d2)*/
+	ldr r1, =0x0f9f26d2
+	str r1, [r0, #0x02c]
+/*MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x030, 0x0000020e)*/
+	ldr r1, =0x0000020e
+	str r1, [r0, #0x030]
+/*MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x038, 0x00190778)*/
+	ldr r1, =0x00190778
+	str r1, [r0, #0x038]
+/*MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x008, 0x00000000)*/
+	ldr r1, =0x00000000
+	str r1, [r0, #0x008]
+/*MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x040, 0x0000004f)*/
+	ldr r1, =0x0000004f
+	str r1, [r0, #0x040]
+/*MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x000, 0xc3110000)*/
+	ldr r1, =0xc3110000
+	str r1, [r0, #0x000]
+/*MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x01c, 0x003f8030)*/
+	ldr r1, =0x003f8030
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8030)*/
+	ldr r1, =0xff0a8030
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x01c, 0x82018030)*/
+	ldr r1, =0x82018030
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04028030)*/
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x02038030)*/
+	ldr r1, =0x02038030
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8038)*/
+	ldr r1, =0xff0a8038
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x82018038)*/
+	ldr r1, =0x82018038
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x04028038)*/
+	ldr r1, =0x04028038
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x02038038)*/
+	ldr r1, =0x02038038
+	str r1, [r0, #0x01c]
+/*MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x800, 0xa1310003)*/
+	ldr r1, =0xa1310003
+	str r1, [r0, #0x800]
 /*MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x020, 0x00007800)*/
-    ldr r1, =0x00007800
-    str r1, [r0, #0x020]
+	ldr r1, =0x00007800
+	str r1, [r0, #0x020]
+/*MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x818, 0x00000000)*/
+	ldr r1, =0x00000000
+	str r1, [r0, #0x818]
+/*MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)*/
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+/*MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x004, 0x00025564)*/
+	ldr r1, =0x00025564
+	str r1, [r0, #0x004]
+/*MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)*/
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+/*MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)*/
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01c]
 
-/*MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x818, 0x0)*/
-    ldr r1, =0x0
-    str r1, [r0, #0x818]
-
-/*MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x800, 0xa1310003)*/
-    ldr r1, =0xa1310003
-    str r1, [r0, #0x800]
-
-/*MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)*/
-    ldr r1, =0x00000800
-    str r1, [r0, #0x8b8]
-
-/*MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)*/
-    ldr r1, =0x00000000
-    str r1, [r0, #0x01c]
-
-/*MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)*/
-    ldr r1, =0x00000800
-    str r1, [r0, #0x8b8]
+/*
+ * End of LPDDR init script
+ */
 
 /*
     The following is to fill in those arguments for this ROM function