diff options
| author | Vishnu Suresh <Vishnu@freescale.com> | 2009-10-07 15:47:46 -0400 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-10-07 15:47:46 -0400 |
| commit | bfce44f397d987c4d0890d4f222a90cf86607b54 (patch) | |
| tree | 39934da8b50b124ef22288767cbf89a08b032919 | |
| parent | 1939b5816adf70a2dcc2e7eb41a816587a8e3c3b (diff) | |
u-boot-2009.03-p2020rdb-eSDHC-IRQ-Bypass-Workaround
AHB2MAG IRQ Bypass Hardware Workaround
This is a workaround for the hardware bug found on the P2020 Rev 1.0.
The DCR[DMA__AHB2MAG_IRQ_BYPASS]is not set automatically upon SoC reset.
This patch sets the bit.
Known Issue: mmcinfo has to be run at the u-boot prompt for this patch code to run.
TODO: Move this code to platform initialization code.
Signed-off-by: Vishnu Suresh <Vishnu@freescale.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 6c17b7f10d..fce4d3d27c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -403,6 +403,10 @@ static int esdhc_init(struct mmc *mmc) /* Enable cache snooping */ out_be32(®s->scr, 0x00000040); +#ifdef CONFIG_P2020 + /* Enable AHB2MAG IRQ Bypass */ + out_be32(®s->scr, regs->scr | 0x00000020); +#endif out_be32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |