NAND boot support for P1 P2 RDB Platforms

Switch options for NAND boot are SW[1:4]='0101"
 To Boot from NAND
 	1. tftp 1000000 u-boot-nand.bin
 	2. nand erase 0 80000
 	3. nand write 1000000 0 80000
 	4. Change the Switch settings to boot from NAND.
 	5. reset the board.


Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>

14 files changed, 1005 insertions, 8 deletions

diff --git a/Makefile b/Makefile
index 81f806fd10..0e185b2454 100644
--- a/Makefile
+++ b/Makefile
@@ -2447,6 +2447,7 @@ MPC8572DS_config:       unconfig
 P2020RDB_config \
 P2020RDB_SDCARD_config \
 P2020RDB_RAMBOOT_config \
+P2020RDB_NAND_config \
 P1021RDB_config \
 P1020RDB_config:	unconfig
 	@mkdir -p $(obj)include
@@ -2460,6 +2461,10 @@ P1020RDB_config:	unconfig
 		echo "#define CONFIG_SYS_RAMBOOT" >> $(obj)include/config.h ; \
 		$(XECHO) "...RAM Boot" ; \
 	fi ;
+	@if [ "$(findstring _NAND_,$@)" ] ; then \
+		echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h ; \
+		$(XECHO) "...NAND Boot" ; \
+	fi ;
 	@$(XECHO) "... setting CONFIG_MP." ;
 	@$(MKCONFIG) -a P10XX_20XX_RDB  ppc mpc85xx p10xx_p20xx_rdb freescale
 	@if [ "$(findstring _SDCARD_,$@)" ] ; then \
@@ -2470,6 +2475,10 @@ P1020RDB_config:	unconfig
 		echo "TEXT_BASE = 0x11001000" > $(obj)board/freescale/p10xx_p20xx_rdb/config.tmp ; \
 		echo "CONFIG_SDCARD_U_BOOT = y" >> $(obj)include/config.mk ; \
 	fi ;
+	@if [ "$(findstring _NAND_,$@)" ] ; then \
+		echo "TEXT_BASE = 0x01001000" > $(obj)board/freescale/p10xx_p20xx_rdb/config.tmp ; \
+		echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
+	fi ;
 
 P1011RDB_config \
 P1012RDB_config:	unconfig
diff --git a/board/freescale/p10xx_p20xx_rdb/config.mk b/board/freescale/p10xx_p20xx_rdb/config.mk
index 9b20d26acf..ec322d4cf0 100644
--- a/board/freescale/p10xx_p20xx_rdb/config.mk
+++ b/board/freescale/p10xx_p20xx_rdb/config.mk
@@ -23,7 +23,9 @@
 #
 #p10xx_20xxerdb board
 #
+ifndef NAND_SPL
 sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+endif
 
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff80000
diff --git a/board/freescale/p10xx_p20xx_rdb/p10xx_p20xx_rdb.c b/board/freescale/p10xx_p20xx_rdb/p10xx_p20xx_rdb.c
index bcd1ca90e0..31646d5939 100644
--- a/board/freescale/p10xx_p20xx_rdb/p10xx_p20xx_rdb.c
+++ b/board/freescale/p10xx_p20xx_rdb/p10xx_p20xx_rdb.c
@@ -121,7 +121,7 @@ phys_size_t initdram(int board_type)
 
 	puts("Initializing....");
 
-#ifdef CONFIG_SDCARD_U_BOOT
+#if defined(CONFIG_SDCARD_U_BOOT) || defined(CONFIG_NAND_U_BOOT)
 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
 
diff --git a/board/freescale/p10xx_p20xx_rdb/u-boot-nand.lds b/board/freescale/p10xx_p20xx_rdb/u-boot-nand.lds
new file mode 100644
index 0000000000..1734b5aafa
--- /dev/null
+++ b/board/freescale/p10xx_p20xx_rdb/u-boot-nand.lds
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  } :text
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg ADDR(.text) - 0x1000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  . = ADDR(.text) + 0x80000;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/config.mk b/config.mk
index 3300b7531c..118bb656aa 100644
--- a/config.mk
+++ b/config.mk
@@ -112,12 +112,16 @@ DBGFLAGS= -g # -DDEBUG
 OPTFLAGS= -Os #-fomit-frame-pointer
 ifndef LDSCRIPT
 #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+else
 ifeq ($(CONFIG_SDCARD_U_BOOT),y)
 LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-sdboot.lds
 else
 LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
 endif
 endif
+endif
 OBJCFLAGS += --gap-fill=0xff
 
 gccincdir := $(shell $(CC) -print-file-name=include)
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 653f327dbf..12e9604779 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Modified by Jason Jin, Jason.jin@freescale.com,
  * 	       Mingkai hu, Mingkai.hu@freescale.com
@@ -141,10 +141,12 @@ void cpu_init_early_f(void)
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
 
+#ifndef CONFIG_NAND_U_BOOT
 	set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		1, 0, BOOKE_PAGESZ_4K, 0);
 
+#endif
 	/* set up CCSR if we want it moved */
 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
 	{
@@ -163,7 +165,10 @@ void cpu_init_early_f(void)
 #endif
 
 	init_laws();
+#ifndef CONFIG_NAND_U_BOOT
+/* To protect DDR TLB from getting invalid */
 	invalidate_tlb(0);
+#endif
 	init_tlbs();
 }
 
@@ -258,8 +263,10 @@ void cpu_init_f (void)
 		out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 #endif
 
+#ifndef CONFIG_NAND_U_BOOT
 	disable_tlb(14);
 	disable_tlb(15);
+#endif
 
 #ifdef CONFIG_CPM2
 	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
diff --git a/cpu/mpc85xx/nand_init.c b/cpu/mpc85xx/nand_init.c
new file mode 100644
index 0000000000..5c48a57a43
--- /dev/null
+++ b/cpu/mpc85xx/nand_init.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm-ppc/io.h>
+
+void cpu_init_f(void)
+{
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+
+	/*
+	 * LCRR - Clock Ratio Register - set up local bus timing
+	 * when needed
+	 */
+	out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
+
+#if defined(CONFIG_NAND_BR_PRELIM)  \
+	&& defined(CONFIG_NAND_OR_PRELIM)
+	out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
+	out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
+#else
+#error  CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
+#endif
+}
+
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 4601c0acd0..1afcd70a80 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. All rights reserved.
  * Copyright (C) 2003  Motorola,Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -185,6 +185,7 @@ _start_e500:
 #endif
 
 #if !defined(CONFIG_SDCARD_U_BOOT)
+#ifndef CONFIG_NAND_U_BOOT
 	/* create a temp mapping in AS=1 to the 4M boot window */
 	lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
 	ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
@@ -236,6 +237,7 @@ _start_e500:
 	mtspr	SPRN_SRR0,r7
 	mtspr	SPRN_SRR1,r6
 	rfi
+#endif
 
 switch_as:
 /* L1 DCache is used for initial RAM */
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index f94053e6fb..01c7e8231f 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -174,6 +174,11 @@ void init_laws(void)
 	gd->used_laws |= (1 << CONFIG_SYS_RESERVED_LAW0);
 #endif
 
+#ifdef CONFIG_NAND_U_BOOT
+	/* To protect DDR LAW */
+	gd->used_laws |= (1 << CONFIG_SYS_RESERVED_LAW1);
+#endif
+
 	for (i = 0; i < num_law_entries; i++) {
 		if (law_table[i].index == -1)
 			set_next_law(law_table[i].addr, law_table[i].size,
diff --git a/include/configs/P10XX_20XX_RDB.h b/include/configs/P10XX_20XX_RDB.h
index 5443cf5aa9..b4ef0064e8 100644
--- a/include/configs/P10XX_20XX_RDB.h
+++ b/include/configs/P10XX_20XX_RDB.h
@@ -223,7 +223,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_RESERVED_LAW0	0
 #endif
 
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#else
 #define CONFIG_SYS_NAND_BASE		0xffa00000
+#endif
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
@@ -232,6 +236,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_NAND	1
 #define CONFIG_NAND_FSL_ELBC	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+#define CONFIG_SYS_NAND_SPL_SIZE     0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE  ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_DST   (0x01000000 - CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x01000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  (0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+
+#ifdef CONFIG_NAND_U_BOOT
+	#define CONFIG_SYS_RESERVED_LAW1  1
+#endif
 
 /* NAND flash config */
 #define CONFIG_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
@@ -248,10 +262,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR)
 
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
-#define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+#ifdef CONFIG_NAND_U_BOOT
+  #define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+  #define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+  #define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+  #define CONFIG_SYS_OR1_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#else
+  #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+  #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+  #define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+  #define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+#endif
 
 #define CONFIG_SYS_VSC7385_BASE	0xffb00000
 
@@ -460,7 +481,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Environment
  */
-#if !defined(CONFIG_SDCARD_U_BOOT)
+#if defined(CONFIG_NAND_U_BOOT)
+#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif !defined(CONFIG_SDCARD_U_BOOT)
 #define CONFIG_ENV_IS_IN_FLASH	1
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR		0xfff80000
diff --git a/nand_spl/board/freescale/p10xx_p20xx_rdb/Makefile b/nand_spl/board/freescale/p10xx_p20xx_rdb/Makefile
new file mode 100644
index 0000000000..8409c09390
--- /dev/null
+++ b/nand_spl/board/freescale/p10xx_p20xx_rdb/Makefile
@@ -0,0 +1,97 @@
+#
+# Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All rights reserved.
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+NAND_SPL := y
+TEXT_BASE := 0xfff00000
+PAD_TO := 0xfff01000
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL
+PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+
+SOBJS	= start.o resetvec.o
+COBJS	= nand_boot_fsl_elbc.o ns16550.o nand_init.o nand_boot.o cache.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:	$(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+$(obj)resetvec.S:
+	@rm -f $(obj)resetvec.S
+	ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+
+$(obj)nand_boot_fsl_elbc.c:
+	@rm -f $(obj)nand_boot_fsl_elbc.c
+	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+	       $(obj)nand_boot_fsl_elbc.c
+
+$(obj)ns16550.c:
+	@rm -f $(obj)ns16550.c
+	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)nand_init.c:
+	@rm -f $(obj)nand_init.c
+	ln -sf $(SRCTREE)/cpu/mpc85xx/nand_init.c $(obj)nand_init.c
+
+$(obj)cache.c:
+	@rm -f $(obj)cache.c
+	ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+
+#########################################################################
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/p10xx_p20xx_rdb/nand_boot.c b/nand_spl/board/freescale/p10xx_p20xx_rdb/nand_boot.c
new file mode 100644
index 0000000000..12efea410e
--- /dev/null
+++ b/nand_spl/board/freescale/p10xx_p20xx_rdb/nand_boot.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm-ppc/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm-ppc/io.h>
+
+#define udelay(x) {int i, j; for (i = 0; i < x; i++) for (j = 0; j < 10000; j++); }
+
+void initsdram(void)
+{
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+
+#if defined(CONFIG_DDR_ECC)
+	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
+	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
+	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
+#endif
+	asm("sync;isync");
+
+	udelay(200);
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+}
+
+void board_init_f_nand(void)
+{
+	u8 sysclk_ratio;
+	uint plat_ratio, bus_clk, sys_clk;
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* initialize selected port with appropriate baud rate */
+#if 0
+	sysclk_ratio = *((volatile unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+	sysclk_ratio &= 0x7;
+	switch (sysclk_ratio) {
+	case 0:
+		sys_clk = 33333000;
+		break;
+	case 1:
+		sys_clk = 39999600;
+		break;
+	case 2:
+		sys_clk = 49999500;
+		break;
+	case 3:
+		sys_clk = 66666000;
+		break;
+	case 4:
+		sys_clk = 83332500;
+		break;
+	case 5:
+		sys_clk = 99999000;
+		break;
+	case 6:
+		sys_clk = 133332000;
+		break;
+	case 7:
+		sys_clk = 166665000;
+		break;
+	}
+#endif
+
+	sys_clk = 66666000;
+	plat_ratio = (gur->porpllsr) & 0x0000003e;
+	plat_ratio >>= 1;
+	bus_clk = plat_ratio * sys_clk;
+	NS16550_init((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500),
+			bus_clk / 16 / CONFIG_BAUDRATE);
+
+
+	/* board specific DDR initialization */
+	initsdram();
+
+	/* copy code to DDR and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, 0,
+			CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
diff --git a/nand_spl/board/freescale/p10xx_p20xx_rdb/start.S b/nand_spl/board/freescale/p10xx_p20xx_rdb/start.S
new file mode 100644
index 0000000000..d392f3e564
--- /dev/null
+++ b/nand_spl/board/freescale/p10xx_p20xx_rdb/start.S
@@ -0,0 +1,457 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2003  Motorola,Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
+ *
+ * The processor starts at 0xfffffffc and the code is first executed in the
+ * last 4K page(0xfffff000-0xffffffff) in flash/rom.
+ *
+ */
+
+#include <config.h>
+#include <mpc85xx.h>
+#include <version.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef	 CONFIG_IDENT_STRING
+#define	 CONFIG_IDENT_STRING ""
+#endif
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r14 to access the GOT
+ */
+	START_GOT
+	GOT_ENTRY(_GOT_TABLE_)
+	END_GOT
+
+/*
+ * e500 Startup -- after reset only the last 4KB of the effective
+ * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
+ * section is located at THIS LAST page and basically does three
+ * things: clear some registers, set up exception tables and
+ * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
+ * continue the boot procedure.
+
+ * Once the boot rom is mapped by TLB entries we can proceed
+ * with normal startup.
+ *
+ */
+
+#define	ENTRY_START \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	ENTRY_END \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.text
+	.globl	_start
+_start:
+	.long	0x27051956		/* U-BOOT Magic Number */
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION
+	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii CONFIG_IDENT_STRING, "\0"
+
+	.align	4
+	.globl _start_e500
+
+_start_e500:
+
+	/* clear registers/arrays not reset by hardware */
+
+	/* L1 */
+	li	r0,2
+	mtspr	L1CSR0,r0	/* invalidate d-cache */
+	mtspr	L1CSR1,r0 	/* invalidate i-cache */
+
+	mfspr	r1,DBSR
+	mtspr	DBSR,r1		/* Clear all valid bits */
+
+	/* Enable L1 Caches early */
+
+	lis	r2,L1CSR0_CPE@H	/* enable parity */
+	ori	r2,r2,L1CSR0_DCE
+	mtspr	L1CSR0,r2	/* enable L1 Dcache */
+	isync
+	mtspr	L1CSR1,r2	/* enable L1 Icache */
+	isync
+	msync
+
+	bl	tlb_entry
+	mr	r5,r0
+	lwzu	r4,0(r5)	/* how many TLB entries we actually use */
+	mtctr	r4
+
+0:	lwzu	r6,4(r5)
+	lwzu	r7,4(r5)
+	lwzu	r8,4(r5)
+	lwzu	r9,4(r5)
+	mtspr	MAS0,r6
+	mtspr	MAS1,r7
+	mtspr	MAS2,r8
+	mtspr	MAS3,r9
+	isync
+	msync
+	tlbwe
+	isync
+	bdnz	0b
+
+/* NOTE: if no enough space for code, try to use default CCSR */
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+	/* Special sequence needed to update CCSRBAR itself */
+	lis	r4,CONFIG_SYS_CCSRBAR_DEFAULT@h
+	ori	r4,r4,CONFIG_SYS_CCSRBAR_DEFAULT@l
+
+	lis	r5,CONFIG_SYS_CCSRBAR@h
+	ori	r5,r5,CONFIG_SYS_CCSRBAR@l
+	srwi	r6,r5,12
+	stw	r6,0(r4)
+	isync
+
+	lis	r5, 0xffff
+	ori	r5,r5, 0xf000
+	lwz	r5,0(r5)
+	isync
+
+	lis	r3,CONFIG_SYS_CCSRBAR@h
+	lwz	r5,CONFIG_SYS_CCSRBAR@l(r3)
+	isync
+#endif
+
+	lis     r7,CONFIG_SYS_CCSRBAR@h
+	ori     r7,r7,CONFIG_SYS_CCSRBAR@l
+	bl	law_entry
+	mr	r6,r0
+	lwzu	r5,0(r6)	/* how many windows we actually use */
+	mtctr	r5
+	li	r2,0x0c28	/* the first pair is reserved for */
+	li	r1,0x0c30	/* boot-over-rio-or-pci */
+0:	lwzu	r4,4(r6)
+	lwzu	r3,4(r6)
+	stwx	r4,r7,r2
+	stwx	r3,r7,r1
+	addi	r2,r2,0x0020
+	addi	r1,r1,0x0020
+	bdnz	0b
+
+	/* Clear and set up some registers. */
+	li	r0,0x0000
+	lis	r1,0xffff
+	mtspr	DEC,r0			/* prevent dec exceptions */
+	mttbl	r0			/* prevent fit & wdt exceptions */
+	mttbu	r0
+	mtspr	TSR,r1			/* clear all timer exception status */
+	mtspr	TCR,r0			/* disable all */
+	mtspr	ESR,r0			/* clear exception syndrome register */
+	mtspr	MCSR,r0			/* machine check syndrome register */
+	mtxer	r0			/* clear integer exception register */
+	isync
+
+	/* Lock L1 DCache as used for initial RAM */
+
+	/* Allocate Initial RAM in data cache.
+	 */
+	lis	r3,CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+	li	r2,512 /* 512*32=16K */
+	mtctr	r2
+	li	r0,0
+1:
+	dcbz	r0,r3
+	dcbtls	0,r0,r3
+	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
+	bdnz	1b
+
+	/* keep current running address = link address */
+	lis	r3,CONFIG_SYS_NAND_BASE@h
+	ori	r3,r3,CONFIG_SYS_NAND_BASE@l
+	addi	r3,r3,_start_cont - _start + _START_OFFSET
+	mtlr	r3
+
+	li	r0,0
+	mtspr	SRR1,r0		/* Keep things disabled for now */
+	mflr	r1
+	mtspr	SRR0,r1
+	rfi
+	isync
+
+	.globl	_start_cont
+_start_cont:
+	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
+	lis	r1,CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
+
+	li	r0,0
+	stwu	r0,-4(r1)
+	stwu	r0,-4(r1)		/* Terminate call chain */
+
+	stwu	r1,-8(r1)		/* Save back chain and move SP */
+	lis	r0,RESET_VECTOR@h	/* Address of reset vector */
+	ori	r0,r0,RESET_VECTOR@l
+	stwu	r1,-8(r1)		/* Save back chain and move SP */
+	stw	r0,+12(r1)		/* Save return addr (underflow vect) */
+
+	GET_GOT
+	bl	cpu_init_f
+	bl	board_init_f_nand
+	isync
+
+	.globl	tlb_entry
+tlb_entry:
+	ENTRY_START
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long (tlb_end-tlb_start)/16
+tlb_start:
+	/* TLB 0 */
+	/* *I*G* - Initial CCSRBAR mapping */
+	.long FSL_BOOKE_MAS0(0, 1, 0)
+	.long FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)
+	.long FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR_DEFAULT,
+			MAS2_I | MAS2_G)
+	.long FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT,
+			0, MAS3_SX | MAS3_SW | MAS3_SR)
+
+	/*
+	 * TLB0		16K	Cacheable, guarded
+	 * Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long FSL_BOOKE_MAS0(0, 0, 0)
+	.long FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)
+	.long FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, MAS2_G)
+	.long FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR,
+			0, MAS3_SX | MAS3_SW | MAS3_SR)
+
+	.long FSL_BOOKE_MAS0(0, 0, 0)
+	.long FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)
+	.long FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+			MAS2_G)
+	.long FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+			0, MAS3_SX | MAS3_SW | MAS3_SR)
+
+	.long FSL_BOOKE_MAS0(0, 0, 0)
+	.long FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)
+	.long FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+			MAS2_G)
+	.long FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+			0, MAS3_SX | MAS3_SW | MAS3_SR)
+
+	.long FSL_BOOKE_MAS0(0, 0, 0)
+	.long FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)
+	.long FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+			MAS2_G)
+	.long FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+			0, MAS3_SX | MAS3_SW | MAS3_SR)
+/*
+	.long FSL_BOOKE_MAS0(0, 0, 0)
+	.long FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)
+	.long FSL_BOOKE_MAS2(PIXIS_BASE, MAS2_I | MAS2_G)
+	.long FSL_BOOKE_MAS3(PIXIS_BASE, 0, MAS3_SX | MAS3_SW | MAS3_SR)
+*/
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	.long FSL_BOOKE_MAS0(1, 0, 0)
+	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4K)
+	.long FSL_BOOKE_MAS2(0xfffff000, MAS2_I | MAS2_G)
+	.long FSL_BOOKE_MAS3(0xfffff000, 0, MAS3_SX | MAS3_SW | MAS3_SR)
+
+	/* *I*G* - CCSRBAR */
+	.long FSL_BOOKE_MAS0(1, 1, 0)
+	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I | MAS2_G)
+	.long FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR, 0, MAS3_SX | MAS3_SW | MAS3_SR)
+
+	/* *I*G* - NAND Flash, localbus */
+	.long FSL_BOOKE_MAS0(1, 8, 0)
+	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
+	.long FSL_BOOKE_MAS2(CONFIG_SYS_NAND_BASE, MAS2_I | MAS2_G)
+	.long FSL_BOOKE_MAS3(CONFIG_SYS_NAND_BASE, 0,
+			MAS3_SX | MAS3_SW | MAS3_SR)
+
+	/* DDR SDRAM */
+	.long FSL_BOOKE_MAS0(1, 9, 0)
+	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+	.long FSL_BOOKE_MAS2(0, 0)
+	.long FSL_BOOKE_MAS3(0, 0, MAS3_SX | MAS3_SW | MAS3_SR)
+
+tlb_end:
+	ENTRY_END
+
+	.globl	law_entry
+law_entry:
+	ENTRY_START
+
+	.long (law_end-law_start)/8
+law_start:
+	.long	0
+	.long	LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+	/* placeholder for LAWAR_TRGT_IF_DDR2 */
+	.long	0
+	.long	0
+
+//	.long	(PIXIS_BASE>>12) & 0xfffff
+//	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_4K)
+
+	.long	(CONFIG_SYS_NAND_BASE>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256K)
+
+law_end:
+	ENTRY_END
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+
+	mr	r1,r3		/* Set new stack pointer		*/
+	mr	r9,r4		/* Save copy of Init Data pointer	*/
+	mr	r10,r5		/* Save copy of Destination Address	*/
+
+	mr	r3,r5				/* Destination Address	*/
+
+        lis     r4, CONFIG_SYS_NAND_BASE@h      /* Source      Address */
+        ori     r4, r4, CONFIG_SYS_NAND_BASE@l
+        li      r5, 0x1000                      /* 4 kbyte bootloader */
+        li      r6, CONFIG_SYS_CACHELINE_SIZE   /* Cache Line Size      */
+
+	/*
+	 * Fix GOT pointer:
+	 *
+	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
+	 *
+	 * Offset:
+	 */
+	sub	r15,r10,r4
+
+	/* First our own GOT */
+	add	r14,r14,r15
+	/* the the one used by the C code */
+	add	r30,r30,r15
+
+	/*
+	 * Now relocate code
+	 */
+
+	cmplw	cr1,r3,r4
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	beq	cr1,4f		/* In place copy is not necessary	*/
+	beq	7f		/* Protect against 0 count		*/
+	mtctr	r0
+	bge	cr1,2f
+
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+1:	lwzu	r0,4(r8)
+	stwu	r0,4(r7)
+	bdnz	1b
+	b	4f
+
+2:	slwi	r0,r0,2
+	add	r8,r4,r0
+	add	r7,r3,r0
+3:	lwzu	r0,-4(r8)
+	stwu	r0,-4(r7)
+	bdnz	3b
+
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4:	cmpwi	r6,0
+	add	r5,r3,r5
+	beq	7f		/* Always flush prefetch queue in any case */
+	subi	r0,r6,1
+	andc	r3,r3,r0
+	mr	r4,r3
+5:	dcbst	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	5b
+	sync			/* Wait for all dcbst to complete on bus */
+	mr	r4,r3
+6:	icbi	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	6b
+7:	sync			/* Wait for all icbi to complete on bus */
+	isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+
+	addi	r0,r10,in_ram - _start + _START_OFFSET
+	mtlr	r0
+	blr				/* NEVER RETURNS! */
+	.globl	in_ram
+in_ram:
+
+        /*
+         * Adjust got table entries to fix pointers to strings
+         */
+        li      r0,__got_entries@sectoff@l
+        la      r4,GOT(_GOT_TABLE_)
+        cmpwi   r0,0
+        mtctr   r0
+        addi    r4,r4,-4
+        beq     4f
+3:      lwzu    r3,4(r4)
+        add     r3,r3,r15
+        stw     r3,0(r4)
+        bdnz    3b
+4:
+	bl	board_init_r
diff --git a/nand_spl/board/freescale/p10xx_p20xx_rdb/u-boot.lds b/nand_spl/board/freescale/p10xx_p20xx_rdb/u-boot.lds
new file mode 100644
index 0000000000..fe51e8d9a8
--- /dev/null
+++ b/nand_spl/board/freescale/p10xx_p20xx_rdb/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc:common)
+SECTIONS
+{
+  .dynsym        : { *(.dynsym)         }
+
+  .resetvec 0xfff00ffc :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .text      :
+  {
+    start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+  }
+  _etext = .;
+
+  .reloc    :
+  {
+    _GOT_TABLE_ = .;
+    *(.got*)
+    __got_end = .;
+  }
+  __got_entries = (__got_end - _GOT_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.rodata*)
+    *(.data*)
+    *(.sdata*)
+  }
+
+  _edata  =  .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss)
+   *(.bss)
+  }
+
+  _end = . ;
+}