diff options
| author | Mingkai Hu <Mingkai.hu@freescale.com> | 2009-10-07 15:47:45 -0400 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-10-07 15:47:45 -0400 |
| commit | 4936f1f873d66e028c5609c5b0ee7c4ef0b0d4df (patch) | |
| tree | da84e0250e02680e7cc275aa8faf95ca9107ade1 | |
| parent | e61155f8535833a701f4f0487efc8c71a0de0d8d (diff) | |
u-boot-2009.03-p2020rdb-eSPI-register-support-MPC8536DS
Add the eSPI register support
This patch borrowed from MPC8536DS Platform SPI Support
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 96eff94b1f..fc601d745f 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -258,6 +258,21 @@ typedef struct ccsr_lbc { } ccsr_lbc_t; /* + * eSPI Registers(0x7000-0x8000) + */ +typedef struct ccsr_espi { + uint mode; /* 0x00 - eSPI mode register */ + uint event; /* 0x04 - eSPI event register */ + uint mask; /* 0x08 - eSPI mask register */ + uint com; /* 0x0c - eSPI command register */ + uint tx; /* 0x10 - eSPI transmit FIFO access register */ + uint rx; /* 0x14 - eSPI receive FIFO access register */ + char res1[8]; /* reserved */ + uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */ + char res2[4048]; /* fill up to 0x1000 */ +} ccsr_espi_t; + +/* * PCI Registers(0x8000-0x9000) */ typedef struct ccsr_pcix { @@ -1691,6 +1706,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) #define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) #define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) +#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) |