U-Boot: DA830: Add NAND 4-bit ECC support

6 files changed, 657 insertions, 18 deletions

diff --git a/cpu/arm926ejs/da8xx/nand.c b/cpu/arm926ejs/da8xx/nand.c
index 396d209a72..fa882e2b10 100644..100755
--- a/cpu/arm926ejs/da8xx/nand.c
+++ b/cpu/arm926ejs/da8xx/nand.c
@@ -51,6 +51,20 @@
 #include <asm/arch/nand_defs.h>
 #include <asm/arch/emif_defs.h>
 
+/* Definitions for 4-bit hardware ECC */
+#define NAND_STATUS_RETRY		5
+#define NAND_TIMEOUT			100
+#define NAND_ECC_BUSY			0xC
+#define NAND_4BITECC_MASK		0x03FF03FF
+#define EMIF_NANDFSR_ECC_STATE_MASK  	0x00000F00
+#define ECC_STATE_NO_ERR		0x0
+#define ECC_STATE_TOO_MANY_ERRS		0x1
+#define ECC_STATE_ERR_CORR_COMP_P	0x2
+#define ECC_STATE_ERR_CORR_COMP_N	0x3
+#define ECC_MAX_CORRECTABLE_ERRORS	0x4
+
+static u_char davinci_ecc_buf[NAND_MAX_OOBSIZE];
+
 extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 
 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
@@ -372,6 +386,523 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
 }
 #endif /* CONFIG_SYS_NAND_HW_ECC */
 
+#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC
+/* flash bbt decriptors */
+static uint8_t nand_davinci_bbt_pattern[] = { 'B', 'b', 't', '0' };
+static uint8_t nand_davinci_mirror_pattern[] = { '1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr nand_davinci_bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 2,
+	.len = 4,
+	.veroffs = 16,
+	.maxblocks = 4,
+	.pattern = nand_davinci_bbt_pattern
+};
+
+static struct nand_bbt_descr nand_davinci_bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 2,
+	.len = 4,
+	.veroffs = 16,
+	.maxblocks = 4,
+	.pattern = nand_davinci_mirror_pattern
+};
+
+static struct nand_ecclayout nand_davinci_4bit_layout = {
+	.eccbytes = 10,
+	.eccpos = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+		   22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+		   38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+		   54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+		},
+	.oobfree = {
+			{.offset = 0, .length = 6},
+			{.offset = 16, .length = 6},
+			{.offset = 32, .length = 6},
+			{.offset = 48, .length = 6},
+		}
+};
+
+static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+	u32 val;
+	emifregs emif_addr;
+	emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
+
+	switch (mode) {
+	case NAND_ECC_WRITE:
+	case NAND_ECC_READ:
+		/*
+		 * Start a new ECC calculation for reading or writing 512 bytes
+		 *  of data.
+		 */
+		val = (emif_addr->NANDFCR & ~(3 << 4)) | (1 << 12);
+		emif_addr->NANDFCR = val;
+		break;
+	case NAND_ECC_READSYN:
+		val = emif_addr->NAND4BITECC1;
+		break;
+	default:
+		break;
+	}
+}
+
+static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
+{
+	emifregs emif_addr;
+
+	emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
+
+	ecc[0] = emif_addr->NAND4BITECC1 & NAND_4BITECC_MASK;
+	ecc[1] = emif_addr->NAND4BITECC2 & NAND_4BITECC_MASK;
+	ecc[2] = emif_addr->NAND4BITECC3 & NAND_4BITECC_MASK;
+	ecc[3] = emif_addr->NAND4BITECC4 & NAND_4BITECC_MASK;
+
+	return 0;
+}
+
+static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
+					   const uint8_t *dat,
+					   uint8_t *ecc_code)
+{
+	unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
+	unsigned int const1 = 0, const2 = 0;
+	unsigned char count1 = 0;
+
+	/*
+	 * Since the NAND_HWECC_SYNDROME option is enabled, this routine is
+	 * only called just after the data and oob have been written.  The
+	 * ECC value calculated by the hardware ECC generator is available
+	 * for us to read.
+	 */
+	nand_davinci_4bit_readecc(mtd, hw_4ecc);
+
+	/*Convert 10 bit ecc value to 8 bit */
+	for (count1 = 0; count1 < 2; count1++) {
+		const2 = count1 * 5;
+		const1 = count1 * 2;
+
+		/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
+		ecc_code[const2] = hw_4ecc[const1] & 0xFF;
+
+		/*
+		 * Take 2 bits as LSB bits from val1 (count1=0) or val5
+		 * (count1=1) and 6 bits from val2 (count1=0) or val5 (count1=1)
+		 */
+		ecc_code[const2 + 1] =
+		    ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
+						      0xFC);
+
+		/*
+		 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
+		 * 4 bits from val3 (count1=0) or val6 (count1=1)
+		 */
+		ecc_code[const2 + 2] =
+		    ((hw_4ecc[const1] >> 22) & 0xF) |
+		    ((hw_4ecc[const1 + 1] << 4) & 0xF0);
+
+		/*
+		 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
+		 * 2 bits from val4 (count1=0) or  val7 (count1=1)
+		 */
+		ecc_code[const2 + 3] =
+		    ((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
+		    ((hw_4ecc[const1 + 1] >> 10) & 0xC0);
+
+		/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
+		ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
+	}
+	return 0;
+}
+
+static int nand_davinci_4bit_compare_ecc(struct mtd_info *mtd,
+					 uint8_t *read_ecc, /* read from NAND */
+					 uint8_t *page_data)
+{
+	struct nand_chip *this = mtd->priv;
+	unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+	int i;
+	unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
+	unsigned short *pspare = NULL, *pspare1 = NULL;
+	unsigned int numErrors, errorAddress, errorValue;
+	emifregs emif_addr;
+	u32 val;
+
+	emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
+
+	/*
+	 * Check for an ECC where all bytes are 0xFF.  If this is the case, we
+	 * will assume we are looking at an erased page and we should ignore the
+	 * ECC.
+	 */
+	for (i = 0; i < 10; i++) {
+		if (read_ecc[i] != 0xFF)
+			break;
+	}
+	if (i == 10)
+		return 0;
+
+	/* Convert 8 bit in to 10 bit */
+	pspare = (unsigned short *)&read_ecc[2];
+	pspare1 = (unsigned short *)&read_ecc[0];
+	/* Take 10 bits from 0th and 1st bytes */
+	ecc_10bit[0] = (*pspare1) & 0x3FF;	/* 10 */
+	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
+	ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
+	    | (((pspare[0]) << 6) & 0x3C0);	/* 6 + 4 */
+	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
+	ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF;	/* 10 */
+	/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
+	ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
+	    | ((((pspare[1])) << 2) & 0x3FC);	/* 2 + 8 */
+	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
+	ecc_10bit[4] = ((pspare[1]) >> 8)
+	    | ((((pspare[2])) << 8) & 0x300);	/* 8 + 2 */
+	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
+	ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF;	/* 10 */
+	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
+	ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
+	    | ((((pspare[3])) << 4) & 0x3F0);	/* 4 + 6 */
+	/*Take 2 bits from 8th byte and 8 bits from 9th byte */
+	ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF;	/* 10 */
+
+	/*
+	 * Write the parity values in the NAND Flash 4-bit ECC Load register.
+	 * Write each parity value one at a time starting from 4bit_ecc_val8
+	 * to 4bit_ecc_val1.
+	 */
+	for (i = 7; i >= 0; i--)
+		emif_addr->NAND4BITECCLOAD = ecc_10bit[i];
+
+	/*
+	 * Perform a dummy read to the EMIF Revision Code and Status register.
+	 * This is required to ensure time for syndrome calculation after
+	 * writing the ECC values in previous step.
+	 */
+
+	val = emif_addr->NANDFSR;
+
+	/*
+	 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
+	 * A syndrome value of 0 means no bit errors. If the syndrome is
+	 * non-zero then go further otherwise return.
+	 */
+	nand_davinci_4bit_readecc(mtd, hw_4ecc);
+
+	if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
+	    hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
+		return 0;
+
+	/*
+	 * Clear any previous address calculation by doing a dummy read of an
+	 * error address register.
+	 */
+	val = emif_addr->NANDERRADD1;
+
+	/*
+	 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
+	 * register to 1.
+	 */
+	emif_addr->NANDFCR |= 1 << 13;
+
+	/*
+	 * Wait for the corr_state field (bits 8 to 11)in the
+	 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
+	 */
+
+	do {
+		iserror = emif_addr->NANDFSR;
+		iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
+		iserror = iserror >> 8;
+	} while ((ECC_STATE_NO_ERR != iserror) &&
+		 (ECC_STATE_TOO_MANY_ERRS != iserror) &&
+		 (ECC_STATE_ERR_CORR_COMP_P != iserror) &&
+		 (ECC_STATE_ERR_CORR_COMP_N != iserror));
+
+
+	/*
+	 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
+	 * corrected (five or more errors).  The number of errors
+	 * calculated (err_num field) differs from the number of errors
+	 * searched.  ECC_STATE_ERR_CORR_COMP_P (0x2) means error
+	 * correction complete (errors on bit 8 or 9).
+	 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
+	 * complete (error exists).
+	 */
+
+	udelay (this->chip_delay);
+	udelay (this->chip_delay);
+	udelay (this->chip_delay);
+	udelay (this->chip_delay);
+
+	if (iserror == ECC_STATE_NO_ERR || iserror == 5)
+		return 0;
+	else if (iserror == ECC_STATE_TOO_MANY_ERRS)
+		return -1;
+
+	numErrors = ((emif_addr->NANDFSR >> 16) & 0x3) + 1;
+
+	/* Read the error address, error value and correct */
+	for (i = 0; i < numErrors; i++) {
+		if (i > 1) {
+			errorAddress =
+			    ((emif_addr->NANDERRADD2 >>
+			      (16 * (i & 1))) & 0x3FF);
+			errorAddress = ((512 + 7) - errorAddress);
+			errorValue =
+			    ((emif_addr->NANDERRVAL2 >>
+			      (16 * (i & 1))) & 0xFF);
+		} else {
+			errorAddress =
+			    ((emif_addr->NANDERRADD1 >>
+			      (16 * (i & 1))) & 0x3FF);
+			errorAddress = ((512 + 7) - errorAddress);
+			errorValue =
+			    ((emif_addr->NANDERRVAL1 >>
+			      (16 * (i & 1))) & 0xFF);
+		}
+		/* xor the corrupt data with error value */
+		if (errorAddress < 512)
+			page_data[errorAddress] ^= errorValue;
+	}
+
+	return numErrors;
+}
+
+static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
+					  uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+	int r;
+
+	/*
+	 * dat points to 512 bytes of data.  read_ecc points to the start of the
+	 * ECC code exactly...  The calc_ecc pointer is not needed since
+	 * our caclulated ECC is already latched in the hardware ECC generator.
+	 */
+	r = nand_davinci_4bit_compare_ecc(mtd, read_ecc, dat);
+
+	return r;
+}
+
+static int
+davinci_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *nand,
+				   uint8_t *buf, int page)
+{
+	int i, eccsize = nand->ecc.size;
+	int eccbytes = nand->ecc.bytes;
+	int eccsteps = nand->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *oob = nand->oob_poi;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		nand->ecc.hwctl(mtd, NAND_ECC_READ);
+		nand->read_buf(mtd, p, eccsize);
+
+		nand->ecc.hwctl(mtd, NAND_ECC_READSYN);
+
+		if (nand->ecc.prepad) {
+			nand->read_buf(mtd, oob, nand->ecc.prepad);
+			oob += nand->ecc.prepad;
+		}
+
+		nand->read_buf(mtd, oob, eccbytes);
+		stat = nand->ecc.correct(mtd, p, oob, NULL);
+
+		if (stat == -1)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+
+		oob += eccbytes;
+
+		if (nand->ecc.postpad) {
+			nand->read_buf(mtd, oob, nand->ecc.postpad);
+			oob += nand->ecc.postpad;
+		}
+	}
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - nand->oob_poi);
+	if (i)
+		nand->read_buf(mtd, oob, i);
+
+	return 0;
+}
+
+static void davinci_write_page_syndrome(struct mtd_info *mtd,
+				    struct nand_chip *nand, const uint8_t *buf)
+{
+	int i, eccsize = nand->ecc.size;
+	int eccbytes = nand->ecc.bytes;
+	int eccsteps = nand->ecc.steps;
+	const uint8_t *p = buf;
+	uint8_t *oob = nand->oob_poi;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+
+		nand->ecc.hwctl(mtd, NAND_ECC_WRITE);
+		nand->write_buf(mtd, p, eccsize);
+
+		/* Calculate ECC without prepad */
+		nand->ecc.calculate(mtd, p, oob + nand->ecc.prepad);
+
+		if (nand->ecc.prepad) {
+			nand->write_buf(mtd, oob, nand->ecc.prepad);
+			oob += nand->ecc.prepad;
+		}
+		nand->write_buf(mtd, oob, eccbytes);
+		oob += eccbytes;
+
+		if (nand->ecc.postpad) {
+			nand->write_buf(mtd, oob, nand->ecc.postpad);
+			oob += nand->ecc.postpad;
+		}
+	}
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - nand->oob_poi);
+	if (i)
+		nand->write_buf(mtd, oob, i);
+}
+
+static int
+davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+				   uint8_t *buf, int page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	chip->cmdfunc (mtd, NAND_CMD_READOOB, 0x0, page & chip->pagemask);
+
+	chip->read_buf(mtd, oob, mtd->oobsize);
+
+	chip->cmdfunc (mtd, NAND_CMD_READ0, 0x0, page & chip->pagemask);
+
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		chip->read_buf(mtd, p, eccsize);
+
+		chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
+
+		if (chip->ecc.prepad)
+			oob += chip->ecc.prepad;
+
+		stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+		if (stat == -1)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - chip->oob_poi);
+	if (i)
+		chip->read_buf(mtd, oob, i);
+
+	return 0;
+}
+
+static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
+				    struct nand_chip *chip, const uint8_t *buf)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+	int offset = 0;
+	const uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+
+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+		chip->write_buf(mtd, p, eccsize);
+
+		/* Calculate ECC without prepad */
+		chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
+
+		if (chip->ecc.prepad) {
+			offset = ((chip->ecc.steps - eccsteps) * chunk);
+			memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
+		}
+
+
+		offset = (((chip->ecc.steps - eccsteps) * chunk) + chip->ecc.prepad);
+		memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			offset = (((chip->ecc.steps - eccsteps) * chunk) +
+				  (chip->ecc.prepad + eccbytes));
+			memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	/* Write the sparebytes into the page once
+	 * all eccsteps have been covered
+	 */
+	for (i = 0; i < mtd->oobsize; i++)
+		writeb(davinci_ecc_buf[i], chip->IO_ADDR_W);
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - chip->oob_poi);
+	if (i)
+		chip->write_buf(mtd, oob, i);
+}
+
+static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
+				   struct nand_chip *chip, int page)
+{
+	int pos, status = 0;
+	const uint8_t *bufpoi = chip->oob_poi;
+
+	pos = mtd->writesize;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
+
+	chip->write_buf(mtd, bufpoi, mtd->oobsize);
+
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -1 : 0;
+}
+
+static int davinci_std_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+				  int page, int sndcmd)
+{
+	uint8_t *buf = chip->oob_poi;
+	uint8_t *bufpoi = buf;
+
+	chip->cmdfunc (mtd, NAND_CMD_READOOB, 0x0, page & chip->pagemask);
+
+	chip->read_buf(mtd, bufpoi, mtd->oobsize);
+
+	return 1;
+}
+
+#endif
+
 static int nand_davinci_dev_ready(struct mtd_info *mtd)
 {
 	emifregs	emif_addr;
@@ -459,6 +990,29 @@ int board_nand_init(struct nand_chip *nand)
 	nand->ecc.mode = NAND_ECC_SOFT;
 #endif /* CONFIG_SYS_NAND_HW_ECC */
 
+#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC
+	nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+	nand->ecc.size = 512;
+	nand->ecc.bytes = 10;
+	nand->ecc.prepad = 6;
+	nand->bbt_td = &nand_davinci_bbt_main_descr;
+	nand->bbt_md = &nand_davinci_bbt_mirror_descr;
+	nand->ecc.layout = &nand_davinci_4bit_layout;
+	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
+	nand->ecc.correct = nand_davinci_4bit_correct_data;
+	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
+#ifdef CFG_DAVINCI_STD_NAND_LAYOUT
+	nand->options |= NAND_USE_FLASH_BBT;
+	nand->ecc.read_page = davinci_std_read_page_syndrome;
+	nand->ecc.write_page = davinci_std_write_page_syndrome;
+	nand->ecc.read_oob = davinci_std_read_oob_syndrome;
+	nand->ecc.write_oob = davinci_std_write_oob_syndrome;
+#else
+	nand->ecc.read_page = davinci_read_page_syndrome;
+	nand->ecc.write_page = davinci_write_page_syndrome;
+	nand->options |= NAND_USE_FLASH_BBT | NAND_USE_DATA_ADJACENT_OOB;
+#endif
+#endif
 	/* Set address of hardware control function */
 	nand->cmd_ctrl = nand_davinci_hwcontrol;
 
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 94a65d4e72..22e4a4c292 100644..100755
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -459,11 +459,12 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 {
 	struct nand_chip *chip = mtd->priv;
 
+#if 0
 	if (!(chip->options & NAND_BBT_SCANNED)) {
 		chip->options |= NAND_BBT_SCANNED;
 		chip->scan_bbt(mtd);
 	}
-
+#endif
 	if (!chip->bbt)
 		return chip->block_bad(mtd, ofs, getchip);
 
@@ -876,10 +877,41 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
  * @buf:	buffer to store read data
  */
 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-			      uint8_t *buf)
+			      uint8_t *buf, int page)
 {
-	chip->read_buf(mtd, buf, mtd->writesize);
-	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	if (!(chip->options & NAND_USE_DATA_ADJACENT_OOB)) {
+		chip->read_buf(mtd, buf, mtd->writesize);
+		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	} else {
+		for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+
+			chip->read_buf(mtd, p, eccsize);
+
+			if (chip->ecc.prepad) {
+				chip->read_buf(mtd, oob, chip->ecc.prepad);
+				oob += chip->ecc.prepad;
+			}
+
+			chip->read_buf(mtd, oob, eccbytes);
+			oob += eccbytes;
+
+			if (chip->ecc.postpad) {
+				chip->read_buf(mtd, oob, chip->ecc.postpad);
+				oob += chip->ecc.postpad;
+			}
+		}
+
+		/* Calculate remaining oob bytes */
+		i = mtd->oobsize - (oob - chip->oob_poi);
+		if (i)
+			chip->read_buf(mtd, oob, i);
+	}
 	return 0;
 }
 
@@ -890,7 +922,7 @@ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  * @buf:	buffer to store read data
  */
 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf)
+				uint8_t *buf, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -900,7 +932,7 @@ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 	uint8_t *ecc_code = chip->buffers->ecccode;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
 
-	chip->ecc.read_page_raw(mtd, chip, buf);
+	chip->ecc.read_page_raw(mtd, chip, buf, page);
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
@@ -1013,7 +1045,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint3
  * Not for syndrome calculating ecc controllers which need a special oob layout
  */
 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf)
+				uint8_t *buf, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1058,7 +1090,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  * we need a special oob layout and handling.
  */
 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
-				   uint8_t *buf)
+				   uint8_t *buf, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1200,11 +1232,11 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 
 			/* Now read the page into the buffer */
 			if (unlikely(ops->mode == MTD_OOB_RAW))
-				ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
+				ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, realpage);
 			else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
 				ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
 			else
-				ret = chip->ecc.read_page(mtd, chip, bufpoi);
+				ret = chip->ecc.read_page(mtd, chip, bufpoi, realpage);
 			if (ret < 0)
 				break;
 
@@ -1612,8 +1644,39 @@ static int nand_read_oob(struct mtd_info *mtd, loff_t from,
 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 				const uint8_t *buf)
 {
-	chip->write_buf(mtd, buf, mtd->writesize);
-	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	const uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	if (!(chip->options & NAND_USE_DATA_ADJACENT_OOB)) {
+		chip->write_buf(mtd, buf, mtd->writesize);
+		chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	} else {
+		for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+
+			chip->write_buf(mtd, p, eccsize);
+
+			if (chip->ecc.prepad) {
+				chip->write_buf(mtd, oob, chip->ecc.prepad);
+				oob += chip->ecc.prepad;
+			}
+
+			chip->write_buf(mtd, oob, eccbytes);
+			oob += eccbytes;
+
+			if (chip->ecc.postpad) {
+				chip->write_buf(mtd, oob, chip->ecc.postpad);
+				oob += chip->ecc.postpad;
+			}
+		}
+
+		/* Calculate remaining oob bytes */
+		i = mtd->oobsize - (oob - chip->oob_poi);
+		if (i)
+			chip->write_buf(mtd, oob, i);
+	}
 }
 
 /**
@@ -2586,7 +2649,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 	if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
 		chip->cmdfunc = nand_command_lp;
 
-	MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
+	printk("NAND device: Manufacturer ID:"
 	          " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
 	          nand_manuf_ids[maf_idx].name, type->name);
 
@@ -2843,8 +2906,13 @@ int nand_scan_tail(struct mtd_info *mtd)
 	mtd->ecclayout = chip->ecc.layout;
 
 	/* Check, if we should skip the bad block table scan */
-	if (chip->options & NAND_SKIP_BBTSCAN)
+	if (chip->options & NAND_SKIP_BBTSCAN) {
 		chip->options |= NAND_BBT_SCANNED;
+		return 0;
+	}
+
+	chip->scan_bbt(mtd);
+	chip->options |= NAND_BBT_SCANNED;
 
 	return 0;
 }
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index d68a315f19..3da92a9efa 100644..100755
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -737,6 +737,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 		if (res < 0)
 			goto outerr;
 
+		udelay(100000);
 		res = scan_write_bbt(mtd, to, len, buf, &buf[len]);
 		if (res < 0)
 			goto outerr;
@@ -976,6 +977,8 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 		printk(KERN_ERR "nand_scan_bbt: Out of memory\n");
 		return -ENOMEM;
 	}
+	/* Clear the memory bad block table */
+	memset(this->bbt, 0x00, len);
 
 	/* If no primary table decriptor is given, scan the device
 	 * to build a memory based bad block table
@@ -1106,7 +1109,7 @@ static struct nand_bbt_descr smallpage_flashbased = {
 };
 
 static struct nand_bbt_descr largepage_flashbased = {
-	.options = NAND_BBT_SCAN2NDPAGE,
+	.options = 0,/*NAND_BBT_SCAN2NDPAGE*/
 	.offs = 0,
 	.len = 2,
 	.pattern = scan_ff_pattern
diff --git a/include/asm-arm/arch-da8xx/emif_defs.h b/include/asm-arm/arch-da8xx/emif_defs.h
index 646fc77469..c91e30c8fc 100644
--- a/include/asm-arm/arch-da8xx/emif_defs.h
+++ b/include/asm-arm/arch-da8xx/emif_defs.h
@@ -55,6 +55,16 @@ typedef struct {
 	dv_reg		NANDF2ECC;
 	dv_reg		NANDF3ECC;
 	dv_reg		NANDF4ECC;
+	u_int8_t	RSVD2[60];
+	dv_reg		NAND4BITECCLOAD;
+	dv_reg		NAND4BITECC1;
+	dv_reg		NAND4BITECC2;
+	dv_reg		NAND4BITECC3;
+	dv_reg		NAND4BITECC4;
+	dv_reg		NANDERRADD1;
+	dv_reg		NANDERRADD2;
+	dv_reg		NANDERRVAL1;
+	dv_reg		NANDERRVAL2;
 } emif_registers;
 
 typedef emif_registers	*emifregs;
diff --git a/include/configs/da830_evm.h b/include/configs/da830_evm.h
index 1e6b94adfb..c4cbe9d58d 100644
--- a/include/configs/da830_evm.h
+++ b/include/configs/da830_evm.h
@@ -128,7 +128,9 @@
 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 #define CONFIG_CLE_MASK			0x10
 #define CONFIG_ALE_MASK			0x8
-#define CONFIG_SYS_NAND_HW_ECC
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_4BIT_HW_ECC
+#define CFG_DAVINCI_STD_NAND_LAYOUT
 #define CONFIG_SYS_NAND_LARGEPAGE
 /* Max number of NAND devices */
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 59e64dcb7a..0404b0961a 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -214,6 +214,8 @@ struct page_layout_item {
 #define NAND_USE_FLASH_BBT	0x00010000
 /* This option skips the bbt scan during initialization. */
 #define NAND_SKIP_BBTSCAN	0x00020000
+/* This option uses the bbt method with OOB data adjacent to the data */
+#define NAND_USE_DATA_ADJACENT_OOB 0x00080000
 /* This option is defined if the board driver allocates its own buffers
    (e.g. because it needs them DMA-coherent */
 #define NAND_OWN_BUFFERS	0x00040000
@@ -285,13 +287,13 @@ struct nand_ecc_ctrl {
 					   uint8_t *calc_ecc);
 	int			(*read_page_raw)(struct mtd_info *mtd,
 						 struct nand_chip *chip,
-						 uint8_t *buf);
+						 uint8_t *buf, int page);
 	void			(*write_page_raw)(struct mtd_info *mtd,
 						  struct nand_chip *chip,
 						  const uint8_t *buf);
 	int			(*read_page)(struct mtd_info *mtd,
 					     struct nand_chip *chip,
-					     uint8_t *buf);
+					     uint8_t *buf, int page);
 	int			(*read_subpage)(struct mtd_info *mtd,
 					     struct nand_chip *chip,
 					     uint32_t offs, uint32_t len,