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authorSudhakar Rajashekara <x0096290@linux-psp-server.(none)>2009-03-26 10:11:28 -0400
committerJustin Waters <justin.waters@timesys.com>2009-09-09 14:03:22 -0400
commitd6292d79e4748444b44c3db12f8f45b29092592d (patch)
tree634b817aa33c57abc56294c7f2592040d8408fea
parent472656e548484cdc0bb56c368efce43c97d0ef5f (diff)
Fix for 1 Bit hardware ECC.
Signed-off-by: Sudhakar Rajashekara <x0096290@linux-psp-server.(none)>
-rw-r--r--board/da8xx/da8xx-evm/da830.c4
-rw-r--r--cpu/arm926ejs/da8xx/nand.c7
-rw-r--r--include/configs/da8xx_evm.h4
3 files changed, 9 insertions, 6 deletions
diff --git a/board/da8xx/da8xx-evm/da830.c b/board/da8xx/da8xx-evm/da830.c
index 8d6a2b9e9a..cde51932db 100644
--- a/board/da8xx/da8xx-evm/da830.c
+++ b/board/da8xx/da8xx-evm/da830.c
@@ -129,7 +129,7 @@ int board_init(void)
lpsc_on(DAVINCI_LPSC_GPIO);
/* Pin Muxing support */
-
+
#ifdef CONFIG_SPI_FLASH
/* SPI0 */
REG(PINMUX7) &= 0x00000FFF;
@@ -146,7 +146,7 @@ int board_init(void)
#endif
/* Async EMIF */
-#if defined(CFG_USE_NAND) || defined(CFG_USE_NOR)
+#if defined(CONFG_SYS_USE_NAND) || defined(CONFIG_SYS_USE_NOR)
REG(PINMUX13) &= 0x00FFFFFF;
REG(PINMUX13) |= 0x11000000;
REG(PINMUX14) = 0x11111111;
diff --git a/cpu/arm926ejs/da8xx/nand.c b/cpu/arm926ejs/da8xx/nand.c
index 014e2b0c11..c3a309c1b2 100644
--- a/cpu/arm926ejs/da8xx/nand.c
+++ b/cpu/arm926ejs/da8xx/nand.c
@@ -121,6 +121,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
emifregs emif_addr;
int dummy;
+ int region = 2;
emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
@@ -129,7 +130,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
dummy = emif_addr->NANDF3ECC;
dummy = emif_addr->NANDF4ECC;
- emif_addr->NANDFCR |= (1 << 8);
+ emif_addr->NANDFCR |= (1 << (8 + region - 1)) | (1 << (region - 1));
}
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
@@ -177,7 +178,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
region++;
}
#else
- const int region = 1;
+ const int region = 2;
tmp = nand_davinci_readecc(mtd, region);
@@ -422,7 +423,7 @@ static void nand_flash_init(void)
emif_regs->AB2CR = acfg2;
emif_regs->AB3CR = acfg3;
emif_regs->AB4CR = acfg4;
- emif_regs->NANDFCR = 0x00000101;
+ emif_regs->NANDFCR = 0x00000202;
}
int board_nand_init(struct nand_chip *nand)
diff --git a/include/configs/da8xx_evm.h b/include/configs/da8xx_evm.h
index 4659126572..42f0a073c0 100644
--- a/include/configs/da8xx_evm.h
+++ b/include/configs/da8xx_evm.h
@@ -30,6 +30,7 @@
/* Board */
/*=======*/
#define CFG_USE_SPIFLASH
+#undef CONFIG_SYS_USE_NAND
#define CPU_TYPE cpu_is_da830() ? 1 : 0
#ifdef CONFIG_DA830_EVM
@@ -121,7 +122,8 @@
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_CLE_MASK 0x10
#define CONFIG_ALE_MASK 0x8
-#define CONFIG_NAND_HW_ECC
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */