U-Boot: cleanup white space issues

Signed-off-by: Sekhar Nori <nsekhar@ti.com>

2 files changed, 133 insertions, 133 deletions

diff --git a/cpu/arm926ejs/da8xx/clock.c b/cpu/arm926ejs/da8xx/clock.c
index a98d016e9b..795aacfe10 100644
--- a/cpu/arm926ejs/da8xx/clock.c
+++ b/cpu/arm926ejs/da8xx/clock.c
@@ -23,47 +23,47 @@
 #include <asm/arch/hardware.h>
 
 unsigned int sysdiv[9] = {
-    PLL_DIV1, PLL_DIV2, PLL_DIV3, PLL_DIV4, PLL_DIV5, PLL_DIV6, 
-    PLL_DIV7, PLL_DIV8, PLL_DIV9 };
+	PLL_DIV1, PLL_DIV2, PLL_DIV3, PLL_DIV4, PLL_DIV5, PLL_DIV6, 
+	PLL_DIV7, PLL_DIV8, PLL_DIV9 };
 
 int clk_get(unsigned int id)
 {
-    int pll_out = CFG_OSCIN_FREQ;
-    int pre_div;
-    int pllm;
-    int post_div;
-    volatile unsigned int pll_base;
+	int pll_out = CFG_OSCIN_FREQ;
+	int pre_div;
+	int pllm;
+	int post_div;
+	volatile unsigned int pll_base;
 
-    if(id == AUXCLK) 
-        goto out;
+	if(id == AUXCLK) 
+		goto out;
 
-    if ((id >> 16) == 1)
+	if ((id >> 16) == 1)
 	pll_base = DAVINCI_PLL_CNTRL1_BASE;
-    else
+	else
 	pll_base = DAVINCI_PLL_CNTRL0_BASE;
 
-    id &= 0xFF;
+	id &= 0xFF;
 
-    pre_div = (REG(pll_base + PLL_PREDIV) & 0xff) + 1;
-    pllm = REG(pll_base + PLL_PLLM)  + 1;
-    post_div = (REG(pll_base + PLL_POSTDIV) & 0xff) + 1;
+	pre_div = (REG(pll_base + PLL_PREDIV) & 0xff) + 1;
+	pllm = REG(pll_base + PLL_PLLM) + 1;
+	post_div = (REG(pll_base + PLL_POSTDIV) & 0xff) + 1;
 
 
-    /* Lets keep this simple. Combining operations can result in 
-     * unexpected approximations
-     */
-    pll_out /= pre_div;
-    pll_out *= pllm;
+	/* Lets keep this simple. Combining operations can result in 
+	 * unexpected approximations
+	 */
+	pll_out /= pre_div;
+	pll_out *= pllm;
 
-    if(id == PLLM) 
-        goto out;
-    
-    pll_out /= post_div;
+	if(id == PLLM) 
+		goto out;
 	
-    if(id == PLLC) 
-        goto out;
-  
-   pll_out /= (REG(pll_base + sysdiv[id - 1]) & 0xff) + 1;
+	pll_out /= post_div;
+	
+	if(id == PLLC) 
+		goto out;
+
+	pll_out /= (REG(pll_base + sysdiv[id - 1]) & 0xff) + 1;
 
 out:
 	return pll_out;	
diff --git a/include/asm-arm/arch-da8xx/hardware.h b/include/asm-arm/arch-da8xx/hardware.h
index 877950c6af..ec47ff49d4 100644
--- a/include/asm-arm/arch-da8xx/hardware.h
+++ b/include/asm-arm/arch-da8xx/hardware.h
@@ -22,7 +22,7 @@
  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  NO  EVENT  SHALL   THE AUTHOR  BE	LIABLE FOR ANY   DIRECT, INDIRECT,
  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
@@ -54,9 +54,9 @@
 #define DAVINCI_WDOG_BASE			(0x01c21000)
 #define DAVINCI_PLL_CNTRL0_BASE			(0x01c11000)
 #define DAVINCI_PLL_CNTRL1_BASE			(0x01e1a000)
-#define DAVINCI_PSC0_BASE 			(0x01c10000)
+#define DAVINCI_PSC0_BASE			(0x01c10000)
 #define DAVINCI_BOOTCFG_BASE			(0x01c14000)
-#define DAVINCI_PSC1_BASE 			(0x01e27000)
+#define DAVINCI_PSC1_BASE			(0x01e27000)
 #define DAVINCI_SPI0_BASE			(0x01c41000)
 #define DAVINCI_SPI1_BASE			(0x01e12000)
 #define DAVINCI_GPIO_BASE			(0x01e26000)
@@ -75,132 +75,132 @@
 #define DAVINCI_INTC_BASE			(0xfffee000)
 
 /* software identifiers for clock ids */
-#define PLL0_SYSCLK2				(0x2)
-#define PLL0_SYSCLK4				(0x4)
-#define PLL0_SYSCLK6				(0x6)
-#define PLL1_SYSCLK2				((1 << 16) | 0x2)
-#define ASYNC3					get_async3_src()
+#define PLL0_SYSCLK2	(0x2)
+#define PLL0_SYSCLK4	(0x4)
+#define PLL0_SYSCLK6	(0x6)
+#define PLL1_SYSCLK2	((1 << 16) | 0x2)
+#define ASYNC3		get_async3_src()
 
 /* special clocks */
-#define PLLM					(0xFF + 1)
-#define PLLC					(0xFF + 2)
-#define AUXCLK					(0xFF + 3)
+#define PLLM		(0xFF + 1)
+#define PLLC		(0xFF + 2)
+#define AUXCLK		(0xFF + 3)
 
-#define PLL0_PLLM				PLLM
-#define PLL0_PLLC				PLLC
-#define PLL1_PLLM				((1 << 16) | PLLM)
-#define PLL1_PLLC				((1 << 16) | PLLC)
+#define PLL0_PLLM	PLLM
+#define PLL0_PLLC	PLLC
+#define PLL1_PLLM	((1 << 16) | PLLM)
+#define PLL1_PLLC	((1 << 16) | PLLC)
 
 /* Clock IDs */
-#define DAVINCI_AUXCLK_CLKID			AUXCLK
-#define DAVINCI_MDIO_CLKID			PLL0_SYSCLK4
-#define DAVINCI_SPI0_CLKID			PLL0_SYSCLK2
-#define DAVINCI_UART0_CLKID			PLL0_SYSCLK2
-#define DAVINCI_UART2_CLKID			(cpu_is_da830() ? PLL0_SYSCLK2 : ASYNC3)
-#define DAVINCI_ARM_CLKID			PLL0_SYSCLK6
+#define DAVINCI_AUXCLK_CLKID	AUXCLK
+#define DAVINCI_MDIO_CLKID	PLL0_SYSCLK4
+#define DAVINCI_SPI0_CLKID	PLL0_SYSCLK2
+#define DAVINCI_UART0_CLKID	PLL0_SYSCLK2
+#define DAVINCI_UART2_CLKID	(cpu_is_da830() ? PLL0_SYSCLK2 : ASYNC3)
+#define DAVINCI_ARM_CLKID	PLL0_SYSCLK6
 
 /* Power and Sleep Controller (PSC) Domains */
-#define DAVINCI_GPSC_ARMDOMAIN		0
-#define DAVINCI_GPSC_DSPDOMAIN		1
+#define DAVINCI_GPSC_ARMDOMAIN	0
+#define DAVINCI_GPSC_DSPDOMAIN	1
 
 /* LPSCs in PSC0 */
-#define DAVINCI_LPSC_TPCC		0
-#define DAVINCI_LPSC_TPTC0		1
-#define DAVINCI_LPSC_TPTC1		2
-#define DAVINCI_LPSC_AEMIF		3
-#define DAVINCI_LPSC_SPI0		4
-#define DAVINCI_LPSC_MMC_SD		5
-#define DAVINCI_LPSC_AINTC		6
+#define DAVINCI_LPSC_TPCC	0
+#define DAVINCI_LPSC_TPTC0	1
+#define DAVINCI_LPSC_TPTC1	2
+#define DAVINCI_LPSC_AEMIF	3
+#define DAVINCI_LPSC_SPI0	4
+#define DAVINCI_LPSC_MMC_SD	5
+#define DAVINCI_LPSC_AINTC	6
 #define DAVINCI_LPSC_ARM_RAM_ROM	7
 #define DAVINCI_LPSC_SECCTL_KEYMGR	8
-#define DAVINCI_LPSC_UART0		9
-#define DAVINCI_LPSC_SCR0		10
-#define DAVINCI_LPSC_SCR1		11
-#define DAVINCI_LPSC_SCR2		12
-#define DAVINCI_LPSC_DMAX		13
-#define DAVINCI_LPSC_ARM		14
-#define DAVINCI_LPSC_GEM		15
+#define DAVINCI_LPSC_UART0	9
+#define DAVINCI_LPSC_SCR0	10
+#define DAVINCI_LPSC_SCR1	11
+#define DAVINCI_LPSC_SCR2	12
+#define DAVINCI_LPSC_DMAX	13
+#define DAVINCI_LPSC_ARM	14
+#define DAVINCI_LPSC_GEM	15
 
 /* for LPSCs in PSC1, 32 + actual id is being used for differentiation */
-#define DAVINCI_LPSC_USB11	    (32 + 1)
-#define DAVINCI_LPSC_USB20      (32 + 2)
-#define DAVINCI_LPSC_GPIO		(32 + 3)
-#define DAVINCI_LPSC_UHPI		(32 + 4)
-#define DAVINCI_LPSC_EMAC       (32 + 5)
+#define DAVINCI_LPSC_USB11	(32 + 1)
+#define DAVINCI_LPSC_USB20	(32 + 2)
+#define DAVINCI_LPSC_GPIO	(32 + 3)
+#define DAVINCI_LPSC_UHPI	(32 + 4)
+#define DAVINCI_LPSC_EMAC	(32 + 5)
 #define DAVINCI_LPSC_DDR_EMIF	(32 + 6)
-#define DAVINCI_LPSC_McASP0     (32 + 7)
-#define DAVINCI_LPSC_McASP1     (32 + 8)
-#define DAVINCI_LPSC_McASP2     (32 + 9)
-#define DAVINCI_LPSC_SPI1   	(32 + 10)
-#define DAVINCI_LPSC_I2C1   	(32 + 11)
-#define DAVINCI_LPSC_UART1   	(32 + 12)
-#define DAVINCI_LPSC_UART2   	(32 + 13)
-#define DAVINCI_LPSC_LCDC   	(32 + 16)
-#define DAVINCI_LPSC_ePWM   	(32 + 17)
-#define DAVINCI_LPSC_eCAP   	(32 + 20)
-#define DAVINCI_LPSC_eQEP   	(32 + 21)
-#define DAVINCI_LPSC_SCR_P0   	(32 + 22)
-#define DAVINCI_LPSC_SCR_P1   	(32 + 23)
-#define DAVINCI_LPSC_CR_P3   	(32 + 26)
-#define DAVINCI_LPSC_L3_CBA_RAM   (32 + 31)
+#define DAVINCI_LPSC_McASP0	(32 + 7)
+#define DAVINCI_LPSC_McASP1	(32 + 8)
+#define DAVINCI_LPSC_McASP2	(32 + 9)
+#define DAVINCI_LPSC_SPI1	(32 + 10)
+#define DAVINCI_LPSC_I2C1	(32 + 11)
+#define DAVINCI_LPSC_UART1	(32 + 12)
+#define DAVINCI_LPSC_UART2	(32 + 13)
+#define DAVINCI_LPSC_LCDC	(32 + 16)
+#define DAVINCI_LPSC_ePWM	(32 + 17)
+#define DAVINCI_LPSC_eCAP	(32 + 20)
+#define DAVINCI_LPSC_eQEP	(32 + 21)
+#define DAVINCI_LPSC_SCR_P0	(32 + 22)
+#define DAVINCI_LPSC_SCR_P1	(32 + 23)
+#define DAVINCI_LPSC_CR_P3	(32 + 26)
+#define DAVINCI_LPSC_L3_CBA_RAM	(32 + 31)
 
 /* Some PSC defines */
 
-#define PSC0_MDCTL			(DAVINCI_PSC0_BASE + 0xa00)
-#define PSC0_MDSTAT			(DAVINCI_PSC0_BASE + 0x800)
-#define PSC0_PTCMD			(DAVINCI_PSC0_BASE + 0x120)
-#define PSC0_PTSTAT			(DAVINCI_PSC0_BASE + 0x128)
+#define PSC0_MDCTL	(DAVINCI_PSC0_BASE + 0xa00)
+#define PSC0_MDSTAT	(DAVINCI_PSC0_BASE + 0x800)
+#define PSC0_PTCMD	(DAVINCI_PSC0_BASE + 0x120)
+#define PSC0_PTSTAT	(DAVINCI_PSC0_BASE + 0x128)
 
-#define PSC1_MDCTL			(DAVINCI_PSC1_BASE + 0xa00)
-#define PSC1_MDSTAT			(DAVINCI_PSC1_BASE + 0x800)
-#define PSC1_PTCMD			(DAVINCI_PSC1_BASE + 0x120)
-#define PSC1_PTSTAT			(DAVINCI_PSC1_BASE + 0x128)
+#define PSC1_MDCTL	(DAVINCI_PSC1_BASE + 0xa00)
+#define PSC1_MDSTAT	(DAVINCI_PSC1_BASE + 0x800)
+#define PSC1_PTCMD	(DAVINCI_PSC1_BASE + 0x120)
+#define PSC1_PTSTAT	(DAVINCI_PSC1_BASE + 0x128)
 
 /* Some PLL defines */
-#define PLL_PLLCTL			(0x100)
-#define PLL_PLLM			(0x110)
-#define PLL_PREDIV			(0x114)
-#define PLL_POSTDIV			(0x128)
-#define PLL_DIV1			(0x118)
-#define PLL_DIV2			(0x11c)
-#define PLL_DIV3			(0x120)
-#define PLL_DIV4			(0x160)
-#define PLL_DIV5			(0x164)
-#define PLL_DIV6			(0x168)
-#define PLL_DIV7			(0x16c)
-#define PLL_DIV8			(0x170)
-#define PLL_DIV9			(0x114)
+#define PLL_PLLCTL	(0x100)
+#define PLL_PLLM	(0x110)
+#define PLL_PREDIV	(0x114)
+#define PLL_POSTDIV	(0x128)
+#define PLL_DIV1	(0x118)
+#define PLL_DIV2	(0x11c)
+#define PLL_DIV3	(0x120)
+#define PLL_DIV4	(0x160)
+#define PLL_DIV5	(0x164)
+#define PLL_DIV6	(0x168)
+#define PLL_DIV7	(0x16c)
+#define PLL_DIV8	(0x170)
+#define PLL_DIV9	(0x114)
 
 /* Boot config */
-#define JTAG_ID_REG	    (DAVINCI_BOOTCFG_BASE + 0x18)
-#define PINMUX0             (DAVINCI_BOOTCFG_BASE + 0x120)
-#define PINMUX1             (DAVINCI_BOOTCFG_BASE + 0x124)
-#define PINMUX2             (DAVINCI_BOOTCFG_BASE + 0x128)
-#define PINMUX3             (DAVINCI_BOOTCFG_BASE + 0x12c)
-#define PINMUX4             (DAVINCI_BOOTCFG_BASE + 0x130)
-#define PINMUX5             (DAVINCI_BOOTCFG_BASE + 0x134)
-#define PINMUX6             (DAVINCI_BOOTCFG_BASE + 0x138)
-#define PINMUX7             (DAVINCI_BOOTCFG_BASE + 0x13c)
-#define PINMUX8             (DAVINCI_BOOTCFG_BASE + 0x140)
-#define PINMUX9             (DAVINCI_BOOTCFG_BASE + 0x144)
-#define PINMUX10            (DAVINCI_BOOTCFG_BASE + 0x148)
-#define PINMUX11            (DAVINCI_BOOTCFG_BASE + 0x14c)
-#define PINMUX12            (DAVINCI_BOOTCFG_BASE + 0x150)
-#define PINMUX13            (DAVINCI_BOOTCFG_BASE + 0x154)
-#define PINMUX14            (DAVINCI_BOOTCFG_BASE + 0x158)
-#define PINMUX15            (DAVINCI_BOOTCFG_BASE + 0x15C)
-#define PINMUX16            (DAVINCI_BOOTCFG_BASE + 0x160)
-#define PINMUX17            (DAVINCI_BOOTCFG_BASE + 0x164)
-#define PINMUX18            (DAVINCI_BOOTCFG_BASE + 0x168)
-#define PINMUX19            (DAVINCI_BOOTCFG_BASE + 0x16c)
-#define SUSPSRC             (DAVINCI_BOOTCFG_BASE + 0x170)
-#define CFGCHIP0            (DAVINCI_BOOTCFG_BASE + 0x17c)
-#define CFGCHIP3	    (DAVINCI_BOOTCFG_BASE + 0x188)
+#define JTAG_ID_REG	(DAVINCI_BOOTCFG_BASE + 0x18)
+#define PINMUX0		(DAVINCI_BOOTCFG_BASE + 0x120)
+#define PINMUX1		(DAVINCI_BOOTCFG_BASE + 0x124)
+#define PINMUX2		(DAVINCI_BOOTCFG_BASE + 0x128)
+#define PINMUX3		(DAVINCI_BOOTCFG_BASE + 0x12c)
+#define PINMUX4		(DAVINCI_BOOTCFG_BASE + 0x130)
+#define PINMUX5		(DAVINCI_BOOTCFG_BASE + 0x134)
+#define PINMUX6		(DAVINCI_BOOTCFG_BASE + 0x138)
+#define PINMUX7		(DAVINCI_BOOTCFG_BASE + 0x13c)
+#define PINMUX8		(DAVINCI_BOOTCFG_BASE + 0x140)
+#define PINMUX9		(DAVINCI_BOOTCFG_BASE + 0x144)
+#define PINMUX10	(DAVINCI_BOOTCFG_BASE + 0x148)
+#define PINMUX11	(DAVINCI_BOOTCFG_BASE + 0x14c)
+#define PINMUX12	(DAVINCI_BOOTCFG_BASE + 0x150)
+#define PINMUX13	(DAVINCI_BOOTCFG_BASE + 0x154)
+#define PINMUX14	(DAVINCI_BOOTCFG_BASE + 0x158)
+#define PINMUX15	(DAVINCI_BOOTCFG_BASE + 0x15C)
+#define PINMUX16	(DAVINCI_BOOTCFG_BASE + 0x160)
+#define PINMUX17	(DAVINCI_BOOTCFG_BASE + 0x164)
+#define PINMUX18	(DAVINCI_BOOTCFG_BASE + 0x168)
+#define PINMUX19	(DAVINCI_BOOTCFG_BASE + 0x16c)
+#define SUSPSRC		(DAVINCI_BOOTCFG_BASE + 0x170)
+#define CFGCHIP0	(DAVINCI_BOOTCFG_BASE + 0x17c)
+#define CFGCHIP3	(DAVINCI_BOOTCFG_BASE + 0x188)
 
 /* Interrupt controller */
-#define INTC_GLB_EN			(DAVINCI_INTC_BASE + 0x10)
-#define INTC_HINT_EN		(DAVINCI_INTC_BASE + 0x1500)
-#define INTC_EN_CLR0		(DAVINCI_INTC_BASE + 0x380)
+#define INTC_GLB_EN	(DAVINCI_INTC_BASE + 0x10)
+#define INTC_HINT_EN	(DAVINCI_INTC_BASE + 0x1500)
+#define INTC_EN_CLR0	(DAVINCI_INTC_BASE + 0x380)
 
 
 #ifndef __ASSEMBLY__