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authorDaniel Schaeffer <daniel.schaeffer@timesys.com>2009-10-08 13:39:34 -0400
committerDaniel Schaeffer <daniel.schaeffer@timesys.com>2009-10-08 13:39:34 -0400
commit0381be360308c4f5b03c05b676eddbbead46a877 (patch)
tree8d92419e8ced5636062fe124e2d3c37999e45128
parent2ccd89c1bd6ab9a832c3b74ba559d9a6e9219ae1 (diff)
This patch originally from LogicPD OMAP35x Release 1.6.1 Original Patch Name: u-boot-2009.03-lv-som-12-isp1760.patch
-rw-r--r--board/omap3/lv_som/lv_som.c42
-rw-r--r--include/asm-arm/arch-omap3/cpu.h1
-rw-r--r--include/configs/omap3_lv_som.h8
3 files changed, 47 insertions, 4 deletions
diff --git a/board/omap3/lv_som/lv_som.c b/board/omap3/lv_som/lv_som.c
index ebcedcc01b..927f7fd5ff 100644
--- a/board/omap3/lv_som/lv_som.c
+++ b/board/omap3/lv_som/lv_som.c
@@ -57,7 +57,7 @@ int board_init(void)
-// GPMC settings for LV SOM
+// GPMC settings for LV SOM Ethernet chip
#define LV_SOM_NET_GPMC_CONFIG1 0x00001000
#define LV_SOM_NET_GPMC_CONFIG2 0x00080802
#define LV_SOM_NET_GPMC_CONFIG3 0x00000000
@@ -77,6 +77,27 @@ u32 gpmc_enet[] = {
LV_SOM_NET_GPMC_CONFIG6,
};
+
+// GPMC settings for LV SOM 1760 chip
+# define LV_SOM_ISP1760_GPMC_CONFIG1 0x00001200
+# define LV_SOM_ISP1760_GPMC_CONFIG2 0x00090901
+# define LV_SOM_ISP1760_GPMC_CONFIG3 0x00091001
+# define LV_SOM_ISP1760_GPMC_CONFIG4 0x07031002
+# define LV_SOM_ISP1760_GPMC_CONFIG5 0x00080c0a
+# define LV_SOM_ISP1760_GPMC_CONFIG6 0x08030200
+
+#define LV_SOM_ISP1760_BASE 0x1c000000
+
+u32 gpmc_isp1760[] = {
+ LV_SOM_ISP1760_GPMC_CONFIG1,
+ LV_SOM_ISP1760_GPMC_CONFIG2,
+ LV_SOM_ISP1760_GPMC_CONFIG3,
+ LV_SOM_ISP1760_GPMC_CONFIG4,
+ LV_SOM_ISP1760_GPMC_CONFIG5,
+ LV_SOM_ISP1760_GPMC_CONFIG6,
+};
+
+
#define LV_SOM_STNOR_ASYNC_GPMC_CONFIG1 0x00001211
#define LV_SOM_STNOR_ASYNC_GPMC_CONFIG2 0x00080901
#define LV_SOM_STNOR_ASYNC_GPMC_CONFIG3 0x00020201
@@ -137,6 +158,22 @@ static void setup_net_chip(void)
}
+/******************************************************************************
+ * Routine: setup_1760_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * IXP1760 hardware.
+ *****************************************************************************/
+static void setup_1760_chip(void)
+{
+ // gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
+ gpmc_csx_t *gpmc_cs1_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
+ // ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+
+ // Configure the Ethernet(CS 1) at 0x08000000, 16MB in size
+ enable_gpmc_config(gpmc_isp1760, gpmc_cs1_base, LV_SOM_ISP1760_BASE, GPMC_SIZE_16M);
+
+}
+
/* These are bit definitions for the RCR register of the NOR flash */
/* 28FxxxP30 device. This register sets the bus configration for reads. */
/* settings, located on address pins A[15:0]. */
@@ -223,6 +260,9 @@ int misc_init_r(void)
setup_net_chip();
#endif
+ /* Setup access to the isp1760 chip on CS6 */
+ setup_1760_chip();
+
fix_flash_sync();
/* Switch to Hardware ECC mode */
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
index 0074cbe022..c2f27be03d 100644
--- a/include/asm-arm/arch-omap3/cpu.h
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -90,6 +90,7 @@ typedef struct ctrl_id {
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
#define GPMC_CONFIG_CS1_BASE (GPMC_BASE + GPMC_CONFIG_CS1)
#define GPMC_CONFIG_CS2_BASE (GPMC_BASE + GPMC_CONFIG_CS2)
+#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
#define GPMC_CONFIG_WP 0x10
#define GPMC_CONFIG_WIDTH 0x30
diff --git a/include/configs/omap3_lv_som.h b/include/configs/omap3_lv_som.h
index b49cda6e3d..128f6dd703 100644
--- a/include/configs/omap3_lv_som.h
+++ b/include/configs/omap3_lv_som.h
@@ -183,13 +183,15 @@
"consoledev=ttyS0\0" \
"rootpath=/opt/nfs-exports/ltib-omap\0" \
"ramdisksize=89000\0" \
+ "kernelimage=uImage\0" \
"nfsoptions=,wsize=1500,rsize=1500\0" \
- "nfsboot=setenv bootargs display=${display} console=${consoledev},${baudrate} root=/dev/nfs rw nfsroot=${serverip}:${rootpath}${nfsoptions} ip=dhcp ${otherbootargs};tftpboot ${loadaddr} uImage;bootm ${loadaddr}\0" \
- "ramboot=setenv bootargs display=${display} console=${consoledev},${baudrate} root=/dev/ram rw ramdisk_size=${ramdisksize} ${otherbootargs};tftpboot ${loadaddr} uImage;tftpboot ${rootfsaddr} rootfs.ext2.gz.uboot;bootm ${loadaddr} ${rootfsaddr}\0" \
+ "nfsboot=setenv bootargs display=${display} console=${consoledev},${baudrate} root=/dev/nfs rw nfsroot=${serverip}:${rootpath}${nfsoptions} ip=dhcp ${otherbootargs};tftpboot ${loadaddr} ${kernelimage};bootm ${loadaddr}\0" \
+ "ramboot=setenv bootargs display=${display} console=${consoledev},${baudrate} root=/dev/ram rw ramdisk_size=${ramdisksize} ${otherbootargs};tftpboot ${loadaddr} ${kernelimage};tftpboot ${rootfsaddr} rootfs.ext2.gz.uboot;bootm ${loadaddr} ${rootfsaddr}\0" \
"xipboot=setenv bootargs display=${display} console=${consoledev},${baudrate} root=/dev/ram rw ramdisk_size=${ramdisksize} ${otherbootargs};bootm ${loadaddr} ${rootfsaddr}\0" \
"rootdevice=/dev/mtdblock4\0" \
"rootfstype=yaffs\0" \
- "mtdboot=setenv bootargs display=${display} console=${consoledev},${baudrate} root=${rootdevice} rootfstype=${rootfstype} rw ${otherbootargs};bootm ${loadaddr}\0"
+ "mtdboot=setenv bootargs display=${display} console=${consoledev},${baudrate} root=${rootdevice} rootfstype=${rootfstype} rw ${otherbootargs};bootm ${loadaddr}\0" \
+ "sdmtdboot=setenv bootargs display=${display} console=${consoledev},${baudrate} root=${rootdevice} rootfstype=${rootfstype} rw ${otherbootargs};mmcinit;fatload mmc0 ${loadaddr} ${kernelimage}; bootm ${loadaddr}\0"
#define CONFIG_BOOTCOMMAND "run xipboot"