diff options
| author | Scott Sweeny <scott.sweeny@timesys.com> | 2009-04-29 17:30:12 -0400 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2009-04-29 17:30:12 -0400 |
| commit | dec5cb99069550cd4492831ce760ff34f1c0d700 (patch) | |
| tree | 7acf4ee25fb96b988e420dff2f09d982c625ad8e | |
| parent | cbde860985ba134e0ce5891ed99838568d5ff6c7 (diff) | |
Put DPLL5 into low-power stop mode
This patch originally from LogicPD OMAP35x Release 1.5.0
Original Patch Name: u-boot-1.1.4-omap3430-lv-som-09-dpll5-stop.patch
| -rw-r--r-- | board/omap3430lv_som/clock.c | 6 | ||||
| -rw-r--r-- | include/asm-arm/arch-omap3/cpu.h | 2 |
2 files changed, 8 insertions, 0 deletions
diff --git a/board/omap3430lv_som/clock.c b/board/omap3430lv_som/clock.c index e919f5fd71..fa714c5a96 100644 --- a/board/omap3430lv_som/clock.c +++ b/board/omap3430lv_som/clock.c @@ -259,6 +259,10 @@ void prcm_init(void) sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); + + // Put DPLL5 into low-power stop mode + sr32(CM_CLKEN2_PLL, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST2_CKGEN, LDELAY); /* Getting the base address to MPU DPLL param table*/ dpll_param_p = (dpll_param *)get_mpu_dpll_param(); @@ -352,3 +356,5 @@ void per_clocks_enable(void) #endif sdelay(1000); } + + diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index 28a29c0afe..252f4af2bc 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -183,7 +183,9 @@ #define CM_CLKSEL_WKUP 0x48004c40 #define CM_IDLEST_WKUP 0x48004c20 #define CM_CLKEN_PLL 0x48004d00 +#define CM_CLKEN2_PLL 0x48004d04 #define CM_IDLEST_CKGEN 0x48004d20 +#define CM_IDLEST2_CKGEN 0x48004d24 #define CM_CLKSEL1_PLL 0x48004d40 #define CM_CLKSEL2_PLL 0x48004d44 #define CM_CLKSEL3_PLL 0x48004d48 |