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| author | Scott Sweeny <scott.sweeny@timesys.com> | 2009-05-06 10:20:41 -0400 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2009-05-06 10:20:41 -0400 |
| commit | 369c2ec9d5ff1460dbd4fe1bb229b37ec0bee11c (patch) | |
| tree | 40a8d904a059fea44255495cdbfaf68a3947cb0b | |
| parent | 8ba9e7bb7fc8406a1013334e4cba40a3ae6606c8 (diff) | |
CS dumping improvements
This patch originally from LogicPD OMAP35x Release 1.5.0
Original Patch Name: u-boot-1.1.4-omap3430-lv-som-32-dump-cs.patch
| -rw-r--r-- | board/omap3430lv_som/mem.c | 40 | ||||
| -rw-r--r-- | include/configs/omap3530lv_som.h | 3 |
2 files changed, 36 insertions, 7 deletions
diff --git a/board/omap3430lv_som/mem.c b/board/omap3430lv_som/mem.c index 39f8083376..b33b151b2c 100644 --- a/board/omap3430lv_som/mem.c +++ b/board/omap3430lv_som/mem.c @@ -379,16 +379,42 @@ void enable_gpmc_config(u32 * gpmc_config, u32 gpmc_base, u32 base, u32 size) void gpmc_dump_config(int cs) { u32 gpmc_base = GPMC_CONFIG_CS0 + (cs * GPMC_CONFIG_WIDTH); - - printf("CS %d: [%08x] %08x %08x %08x %08x %08x %08x %08x\n", - cs, __raw_readl(GPMC_CONFIG), + u32 config7; + u32 base, len; + + config7 = __raw_readl(GPMC_CONFIG7 + gpmc_base); + if (config7 & (1<<6)) { + len = (((config7 >> 7 & 0xf) ^ 0xf) + 1) << 24; + base = (config7 & 0x3F) << 24; + printf("%d:%08x %08x %08x %08x %08x %08x %03x %08x-%08x\n", + cs, __raw_readl(GPMC_CONFIG1 + gpmc_base), __raw_readl(GPMC_CONFIG2 + gpmc_base), __raw_readl(GPMC_CONFIG3 + gpmc_base), __raw_readl(GPMC_CONFIG4 + gpmc_base), __raw_readl(GPMC_CONFIG5 + gpmc_base), __raw_readl(GPMC_CONFIG6 + gpmc_base), - __raw_readl(GPMC_CONFIG7 + gpmc_base)); + config7, base, base+len-1); + } +} + +#if defined (CFG_OMAP_DUMP_GPMC) +void do_dump_cs (cmd_tbl_t *cmdtp, int flah, int argc, char *argv[]) +{ + int i; + printf("CS: GPMC_CONFIG [%08x]\n", __raw_readl(GPMC_CONFIG)); + printf("CS: GPMC_IRQENABLE [%08x]\n", __raw_readl(GPMC_IRQENABLE)); + printf("CS: GPMC_TIMEOUT_CONTROL [%08x]\n", __raw_readl(GPMC_TIMEOUT_CONTROL)); + for (i=0; i<8; ++i) + gpmc_dump_config(i); + + return 0; } +U_BOOT_CMD( + dump_cs, 1, 1, do_dump_cs, + "dump_cs - display OMAP Chip Select registers\n", + "\n - display active OMAP Chip Select registers\n" +); +#endif /***************************************************** * gpmc_init(): init gpmc bus * Init GPMC for x16, MuxMode (SDRAM in x32). @@ -503,7 +529,7 @@ void fix_flash_sync() /* CS 2 - Check if NOR is in sync, and if not, then put flash into sync mode, and GPMC into sync */ - gpmc_dump_config(2); + // gpmc_dump_config(2); gpmc_base = GPMC_CONFIG_CS0 + (2 * GPMC_CONFIG_WIDTH); config = __raw_readl(GPMC_CONFIG1 + gpmc_base); if (!(config & TYPE_READTYPE)) { @@ -522,7 +548,7 @@ void fix_flash_sync() enable_gpmc_config(gpmc_config, gpmc_base, FLASH_BASE, GPMC_SIZE_64M); // Second, tell flash to go into sync mode. - gpmc_dump_config(2); + // gpmc_dump_config(2); // 1st NOR cycle, send read config register setup 0x60 *(volatile u16 *)FLASH_BASE = 0x0060; @@ -540,7 +566,7 @@ void fix_flash_sync() // And lastly, set the WAIT1 polarity high __raw_writel(__raw_readl(GPMC_CONFIG) | 0x200, GPMC_CONFIG); - gpmc_dump_config(2); + // gpmc_dump_config(2); } #endif diff --git a/include/configs/omap3530lv_som.h b/include/configs/omap3530lv_som.h index e69c7796be..9f1411bcba 100644 --- a/include/configs/omap3530lv_som.h +++ b/include/configs/omap3530lv_som.h @@ -388,4 +388,7 @@ extern void board_get_nth_enetaddr (unsigned char *enetaddr, int which); #define NAND_WAIT_READY(nand) udelay(10) +// Extra CFGs for debug +#define CFG_OMAP_DUMP_GPMC // Add dump_gpmc + #endif /* __CONFIG_H */ |