From 9b8c081249f6b9754bcde2602fa1c3094ae3b2a6 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 13 Nov 2017 14:41:42 +0100 Subject: linux-toradex-mainline: apalis tk1 mainline, update to 4.14 Update to latest Linux LTS 4.14. Signed-off-by: Marcel Ziswiler Acked-by: Dominik Sliwa (cherry picked from commit 7bcd5eac4e92b1f372835e9f44066f6dd337bd61) --- ...oradex_apalis_tk1_t30-customize-defconfig.patch | 84 + ...tk1-fix-pcie-clock-and-reset-not-conformi.patch | 153 ++ ...3-igb-integrate-tools-only-device-support.patch | 75 + ...tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch | 137 ++ ...ra-apalis-tk1-hack-to-make-sd1-functional.patch | 53 + ...ra_defconfig-snapd-squashfs-configuration.patch | 36 + ...apalis-tk1-support-v1.2-hardware-revision.patch | 2425 ++++++++++++++++++++ ...fix-pcie-reset-for-reliable-gigabit-ether.patch | 140 ++ .../linux/linux-toradex-mainline_4.14.bb | 74 + 9 files changed, 3177 insertions(+) create mode 100644 recipes-kernel/linux/linux-toradex-mainline-4.14/0001-toradex_apalis_tk1_t30-customize-defconfig.patch create mode 100644 recipes-kernel/linux/linux-toradex-mainline-4.14/0002-apalis_t30-tk1-fix-pcie-clock-and-reset-not-conformi.patch create mode 100644 recipes-kernel/linux/linux-toradex-mainline-4.14/0003-igb-integrate-tools-only-device-support.patch create mode 100644 recipes-kernel/linux/linux-toradex-mainline-4.14/0004-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch create mode 100644 recipes-kernel/linux/linux-toradex-mainline-4.14/0005-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch create mode 100644 recipes-kernel/linux/linux-toradex-mainline-4.14/0006-tegra_defconfig-snapd-squashfs-configuration.patch create mode 100644 recipes-kernel/linux/linux-toradex-mainline-4.14/0007-ARM-tegra-apalis-tk1-support-v1.2-hardware-revision.patch create mode 100644 recipes-kernel/linux/linux-toradex-mainline-4.14/0008-apalis-tk1-fix-pcie-reset-for-reliable-gigabit-ether.patch create mode 100644 recipes-kernel/linux/linux-toradex-mainline_4.14.bb diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.14/0001-toradex_apalis_tk1_t30-customize-defconfig.patch b/recipes-kernel/linux/linux-toradex-mainline-4.14/0001-toradex_apalis_tk1_t30-customize-defconfig.patch new file mode 100644 index 0000000..fc3904b --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline-4.14/0001-toradex_apalis_tk1_t30-customize-defconfig.patch @@ -0,0 +1,84 @@ +From 8d39626d07718220b426e9be045df8ed9d1fd707 Mon Sep 17 00:00:00 2001 +Message-Id: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +From: Dominik Sliwa +Date: Thu, 15 Dec 2016 10:40:06 +0100 +Subject: [PATCH 1/8] toradex_apalis_tk1_t30: customize defconfig + +--- + arch/arm/configs/tegra_defconfig | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig +index 6678f29..cb97ea2 100644 +--- a/arch/arm/configs/tegra_defconfig ++++ b/arch/arm/configs/tegra_defconfig +@@ -104,9 +104,21 @@ CONFIG_USB_PEGASUS=y + CONFIG_USB_USBNET=y + CONFIG_USB_NET_SMSC75XX=y + CONFIG_USB_NET_SMSC95XX=y ++CONFIG_ATH9K=m ++CONFIG_ATH9K_CHANNEL_CONTEXT=y ++CONFIG_ATH9K_HTC=m ++CONFIG_ATH10K=m ++CONFIG_ATH10K_PCI=m ++# CONFIG_WLAN_VENDOR_ATMEL is not set + CONFIG_BRCMFMAC=m ++CONFIG_IWLWIFI=m ++CONFIG_IWLDVM=m ++CONFIG_IWLMVM=m + CONFIG_RT2X00=y + CONFIG_RT2800USB=m ++CONFIG_RTL_CARDS=m ++CONFIG_RTL8192CU=m ++CONFIG_RSI_91X=m + CONFIG_INPUT_JOYDEV=y + CONFIG_INPUT_EVDEV=y + CONFIG_KEYBOARD_GPIO=y +@@ -180,6 +192,7 @@ CONFIG_USB_GSPCA=y + CONFIG_DRM=y + CONFIG_DRM_NOUVEAU=m + CONFIG_DRM_TEGRA=y ++CONFIG_DRM_TEGRA_STAGING=y + CONFIG_DRM_PANEL_SIMPLE=y + # CONFIG_LCD_CLASS_DEVICE is not set + # CONFIG_BACKLIGHT_GENERIC is not set +@@ -213,7 +226,7 @@ CONFIG_SND_SOC_TEGRA_MAX98090=y + CONFIG_SND_SOC_TEGRA_SGTL5000=y + CONFIG_USB=y + CONFIG_USB_XHCI_HCD=y +-CONFIG_USB_XHCI_TEGRA=y ++CONFIG_USB_XHCI_TEGRA=m + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_TEGRA=y + CONFIG_USB_ACM=y +@@ -227,11 +240,9 @@ CONFIG_MMC_BLOCK_MINORS=16 + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_PLTFM=y + CONFIG_MMC_SDHCI_TEGRA=y +-CONFIG_NEW_LEDS=y + CONFIG_LEDS_CLASS=y + CONFIG_LEDS_GPIO=y + CONFIG_LEDS_PWM=y +-CONFIG_LEDS_TRIGGERS=y + CONFIG_LEDS_TRIGGER_TIMER=y + CONFIG_LEDS_TRIGGER_ONESHOT=y + CONFIG_LEDS_TRIGGER_HEARTBEAT=y +@@ -251,6 +262,7 @@ CONFIG_RTC_DRV_TEGRA=y + CONFIG_DMADEVICES=y + CONFIG_TEGRA20_APB_DMA=y + CONFIG_STAGING=y ++CONFIG_R8188EU=m + CONFIG_MFD_NVEC=y + CONFIG_KEYBOARD_NVEC=y + CONFIG_SERIO_NVEC_PS2=y +@@ -279,6 +291,7 @@ CONFIG_EXT3_FS=y + CONFIG_EXT3_FS_POSIX_ACL=y + CONFIG_EXT3_FS_SECURITY=y + # CONFIG_DNOTIFY is not set ++CONFIG_AUTOFS4_FS=y + CONFIG_VFAT_FS=y + CONFIG_TMPFS=y + CONFIG_TMPFS_POSIX_ACL=y +-- +2.9.5 + diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.14/0002-apalis_t30-tk1-fix-pcie-clock-and-reset-not-conformi.patch b/recipes-kernel/linux/linux-toradex-mainline-4.14/0002-apalis_t30-tk1-fix-pcie-clock-and-reset-not-conformi.patch new file mode 100644 index 0000000..9c4436d --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline-4.14/0002-apalis_t30-tk1-fix-pcie-clock-and-reset-not-conformi.patch @@ -0,0 +1,153 @@ +From fc37cb5b5f68acc1548ebdc7750d5e04dd616bde Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +References: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +From: Marcel Ziswiler +Date: Thu, 15 Dec 2016 10:24:58 +0100 +Subject: [PATCH 2/8] apalis_t30/tk1: fix pcie clock and reset not conforming + to specification + +Fix PCIe clock and reset not conforming to specification by moving PCIe +reset handling including the PLX PEX 8605 errata 5 workaround from the +board platform data into the right places timing wise in the PCIe driver +itself. + +Also add a kernel command line argument to allow using the Apalis GPIO7 +as a regular GPIO rather than for above mentioned PLX PEX 8605 +workaround: + +pex_perst=0 + +Signed-off-by: Marcel Ziswiler +Acked-by: Dominik Sliwa +(cherry picked from toradex_tk1_l4t_r21.5 commit +3e2259b04c2e2c029f742e9dda06a3a2739977d4) +(cherry picked from tegra commit +a2f63805703b43d55d91ae17f10d0049bf0f625e) +--- + drivers/pci/host/pci-tegra.c | 88 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 88 insertions(+) + +diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c +index 1987fec..5c7916b 100644 +--- a/drivers/pci/host/pci-tegra.c ++++ b/drivers/pci/host/pci-tegra.c +@@ -51,6 +51,34 @@ + #include + #include + ++//#define CONFIG_MACH_APALIS_T30 ++#define CONFIG_MACH_APALIS_TK1 ++#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_APALIS_TK1) ++#include ++ ++#include "../../../include/dt-bindings/gpio/tegra-gpio.h" ++ ++#ifdef CONFIG_MACH_APALIS_T30 ++#define APALIS_GPIO7 TEGRA_GPIO(S, 7) ++ ++#define LAN_RESET_N -1 ++ ++#define PEX_PERST_N APALIS_GPIO7 ++ ++#define RESET_MOCI_N TEGRA_GPIO(I, 4) ++#endif ++ ++#ifdef CONFIG_MACH_APALIS_TK1 ++#define APALIS_GPIO7 TEGRA_GPIO(DD, 1) ++ ++#define LAN_RESET_N TEGRA_GPIO(S, 2) ++ ++#define PEX_PERST_N APALIS_GPIO7 ++ ++#define RESET_MOCI_N TEGRA_GPIO(U, 4) ++#endif ++#endif ++ + #define INT_PCI_MSI_NR (8 * 32) + + /* register definitions */ +@@ -323,6 +351,26 @@ struct tegra_pcie_bus { + unsigned int nr; + }; + ++#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_APALIS_TK1) ++/* To disable the PCIe switch reset errata workaround */ ++int g_pex_perst = 1; ++ ++/* To disable the PCIe switch reset errata workaround */ ++static int __init disable_pex_perst(char *s) ++{ ++ if (!(*s) || !strcmp(s, "0")) ++ g_pex_perst = 0; ++ ++ return 0; ++} ++__setup("pex_perst=", disable_pex_perst); ++#endif /* CONFIG_MACH_APALIS_T30 || CONFIG_MACH_APALIS_TK1 */ ++ ++static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys) ++{ ++ return sys->private_data; ++} ++ + static inline void afi_writel(struct tegra_pcie *pcie, u32 value, + unsigned long offset) + { +@@ -526,6 +574,27 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) + unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); + unsigned long value; + ++#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_APALIS_TK1) ++ /* ++ * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation ++ * Board ++ */ ++ if (g_pex_perst) ++ gpio_request(PEX_PERST_N, "PEX_PERST_N"); ++ gpio_request(RESET_MOCI_N, "RESET_MOCI_N"); ++ if (g_pex_perst) ++ gpio_direction_output(PEX_PERST_N, 0); ++ gpio_direction_output(RESET_MOCI_N, 0); ++ ++#ifdef CONFIG_MACH_APALIS_TK1 ++ /* Reset I210 Gigabit Ethernet Controller */ ++ if (LAN_RESET_N) { ++ gpio_request(LAN_RESET_N, "LAN_RESET_N"); ++ gpio_direction_output(LAN_RESET_N, 0); ++ } ++#endif /* CONFIG_MACH_APALIS_TK1 */ ++#endif /* CONFIG_MACH_APALIS_T30 || CONFIG_MACH_APALIS_TK1 */ ++ + /* pulse reset signal */ + value = afi_readl(port->pcie, ctrl); + value &= ~AFI_PEX_CTRL_RST; +@@ -536,6 +605,25 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) + value = afi_readl(port->pcie, ctrl); + value |= AFI_PEX_CTRL_RST; + afi_writel(port->pcie, value, ctrl); ++ ++#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_APALIS_TK1) ++ /* Must be asserted for 100 ms after power and clocks are stable */ ++ if (g_pex_perst) ++ gpio_set_value(PEX_PERST_N, 1); ++ /* ++ * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until ++ * 900 us After PEX_PERST# De-assertion ++ */ ++ if (g_pex_perst) ++ mdelay(1); ++ gpio_set_value(RESET_MOCI_N, 1); ++ ++#ifdef CONFIG_MACH_APALIS_TK1 ++ /* Release I210 Gigabit Ethernet Controller Reset */ ++ if (LAN_RESET_N) ++ gpio_set_value(LAN_RESET_N, 1); ++#endif /* CONFIG_MACH_APALIS_TK1 */ ++#endif /* CONFIG_MACH_APALIS_T30 || CONFIG_MACH_APALIS_TK1 */ + } + + static void tegra_pcie_port_enable(struct tegra_pcie_port *port) +-- +2.9.5 + diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.14/0003-igb-integrate-tools-only-device-support.patch b/recipes-kernel/linux/linux-toradex-mainline-4.14/0003-igb-integrate-tools-only-device-support.patch new file mode 100644 index 0000000..7ff1c96 --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline-4.14/0003-igb-integrate-tools-only-device-support.patch @@ -0,0 +1,75 @@ +From 3facf94b99d303357bb7d2188174eae38401f294 Mon Sep 17 00:00:00 2001 +Message-Id: <3facf94b99d303357bb7d2188174eae38401f294.1510580437.git.marcel.ziswiler@toradex.com> +In-Reply-To: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +References: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +From: Marcel Ziswiler +Date: Thu, 15 Dec 2016 10:55:11 +0100 +Subject: [PATCH 3/8] igb: integrate tools only device support + +Springville/i211 with a blank Flash/iNVM use different PCI IDs. Extend +the driver to load despite i210/i211 data sheets claiming tools only, +not for driver. + +Signed-off-by: Marcel Ziswiler +Acked-by: Dominik Sliwa + +(cherry picked from toradex_tk1_l4t_r21.5 commit +783780c43fd4e1473fb64790c8b9e0adb2be04a3) +(cherry picked from tegra commit +2c7123458270c9b3ec9b5ed668f9d55a7f8dbad9) +--- + drivers/net/ethernet/intel/igb/e1000_82575.c | 2 ++ + drivers/net/ethernet/intel/igb/e1000_hw.h | 2 ++ + drivers/net/ethernet/intel/igb/igb_main.c | 2 ++ + 3 files changed, 6 insertions(+) + +diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c +index c37cc8b..d38d8a7 100644 +--- a/drivers/net/ethernet/intel/igb/e1000_82575.c ++++ b/drivers/net/ethernet/intel/igb/e1000_82575.c +@@ -625,6 +625,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) + case E1000_DEV_ID_I350_SGMII: + mac->type = e1000_i350; + break; ++ case E1000_DEV_ID_I210_TOOLS_ONLY: + case E1000_DEV_ID_I210_COPPER: + case E1000_DEV_ID_I210_FIBER: + case E1000_DEV_ID_I210_SERDES: +@@ -633,6 +634,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) + case E1000_DEV_ID_I210_SERDES_FLASHLESS: + mac->type = e1000_i210; + break; ++ case E1000_DEV_ID_I211_TOOLS_ONLY: + case E1000_DEV_ID_I211_COPPER: + mac->type = e1000_i211; + break; +diff --git a/drivers/net/ethernet/intel/igb/e1000_hw.h b/drivers/net/ethernet/intel/igb/e1000_hw.h +index 6c9485a..a3827f1 100644 +--- a/drivers/net/ethernet/intel/igb/e1000_hw.h ++++ b/drivers/net/ethernet/intel/igb/e1000_hw.h +@@ -58,6 +58,8 @@ struct e1000_hw; + #define E1000_DEV_ID_I350_FIBER 0x1522 + #define E1000_DEV_ID_I350_SERDES 0x1523 + #define E1000_DEV_ID_I350_SGMII 0x1524 ++#define E1000_DEV_ID_I210_TOOLS_ONLY 0x1531 ++#define E1000_DEV_ID_I211_TOOLS_ONLY 0x1532 + #define E1000_DEV_ID_I210_COPPER 0x1533 + #define E1000_DEV_ID_I210_FIBER 0x1536 + #define E1000_DEV_ID_I210_SERDES 0x1537 +diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c +index ea69af2..a060fc2 100644 +--- a/drivers/net/ethernet/intel/igb/igb_main.c ++++ b/drivers/net/ethernet/intel/igb/igb_main.c +@@ -77,7 +77,9 @@ static const struct pci_device_id igb_pci_tbl[] = { + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_TOOLS_ONLY), board_82575 }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_TOOLS_ONLY), board_82575 }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, +-- +2.9.5 + diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.14/0004-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch b/recipes-kernel/linux/linux-toradex-mainline-4.14/0004-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch new file mode 100644 index 0000000..0613617 --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline-4.14/0004-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch @@ -0,0 +1,137 @@ +From d912735d53757d9b525ee7f016020400be458867 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +References: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +From: Marcel Ziswiler +Date: Thu, 15 Dec 2016 10:55:54 +0100 +Subject: [PATCH 4/8] apalis_t30/tk1: igb: no nvm and Ethernet MAC address + handling + +Only warn rather than fail on NVM validation failures on Apalis T30 and +Apalis TK1. + +Revise Ethernet MAC address assignment: should now handle up to two +instances of custom user MACs (2nd one with a 0x100000 offset). This +way customer does not have to worry about NVM on a secondary Ethernet +on the carrier board and still gets a valid official MAC address from +us (e.g. analogous to how we did it on our Protea carrier board). + +Use the Toradex OUI as default MAC address if no valid one is +encountered. + +Tested on samples of Apalis T30 2GB V1.0B, V1.0C, V1.1A, Apalis T30 1GB +V1.0A, V1.1A and Apalis T30 1GB IT V1.1A both with blank NVMs as well +as iNVMs programmed with Intel's defaults. + +Tested on samples of Apalis TK1 2GB V1.0A, V1.0B and V1.1A both with +blank NVMs as well as iNVMs programmed with Intel's defaults. + +Signed-off-by: Marcel Ziswiler +Acked-by: Dominik Sliwa + +(cherry picked from toradex_tk1_l4t_r21.5 commit +70efa60d96c9f05d91d8875eee97446df7f9e877) +(cherry picked from tegra commit +c4c3c7449bdb15c53bfebb0a29c73b24ea810d23) +--- + drivers/net/ethernet/intel/igb/igb_main.c | 60 +++++++++++++++++++++++++++++-- + 1 file changed, 57 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c +index a060fc2..c872c15 100644 +--- a/drivers/net/ethernet/intel/igb/igb_main.c ++++ b/drivers/net/ethernet/intel/igb/igb_main.c +@@ -55,6 +55,7 @@ + #include + #endif + #include ++#include + #include "igb.h" + + #define MAJ 5 +@@ -69,6 +70,9 @@ static const char igb_driver_string[] = + static const char igb_copyright[] = + "Copyright (c) 2007-2014 Intel Corporation."; + ++static char g_mac_addr[ETH_ALEN]; ++static int g_usr_mac = 0; ++ + static const struct e1000_info *igb_info_tbl[] = { + [board_82575] = &e1000_82575_info, + }; +@@ -259,6 +263,37 @@ static int debug = -1; + module_param(debug, int, 0); + MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); + ++/* Retrieve user set MAC address */ ++static int __init setup_igb_mac(char *macstr) ++{ ++ int i, j; ++ unsigned char result, value; ++ ++ for (i = 0; i < ETH_ALEN; i++) { ++ result = 0; ++ ++ if (i != 5 && *(macstr + 2) != ':') ++ return -1; ++ ++ for (j = 0; j < 2; j++) { ++ if (isxdigit(*macstr) && (value = isdigit(*macstr) ? ++ *macstr - '0' : toupper(*macstr) - 'A' + 10) < 16) { ++ result = result * 16 + value; ++ macstr++; ++ } else ++ return -1; ++ } ++ ++ macstr++; ++ g_mac_addr[i] = result; ++ } ++ ++ g_usr_mac = 1; ++ ++ return 0; ++} ++__setup("igb_mac=", setup_igb_mac); ++ + struct igb_reg_info { + u32 ofs; + char *name; +@@ -2521,12 +2556,31 @@ static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + dev_err(&pdev->dev, "NVM Read Error\n"); + } + ++ if (g_usr_mac && (g_usr_mac < 3)) { ++ /* Get user set MAC address */ ++ if (g_usr_mac == 2) { ++ /* 0x100000 offset for 2nd Ethernet MAC */ ++ g_mac_addr[3] += 0x10; ++ if (g_mac_addr[3] < 0x10) ++ dev_warn(&pdev->dev, ++ "MAC addr byte 3 (0x%02x) wrap around" ++ "\n", ++ g_mac_addr[3]); ++ } ++ memcpy(hw->mac.addr, g_mac_addr, ETH_ALEN); ++ g_usr_mac++; ++ } ++ + memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); + + if (!is_valid_ether_addr(netdev->dev_addr)) { +- dev_err(&pdev->dev, "Invalid MAC Address\n"); +- err = -EIO; +- goto err_eeprom; ++ /* Use Toradex OUI as default */ ++ char default_mac_addr[ETH_ALEN] = { ++ 0x0, 0x14, 0x2d, 0x0, 0x0, 0x0 ++ }; ++ dev_warn(&pdev->dev, "using Toradex OUI as default igb MAC\n"); ++ memcpy(hw->mac.addr, default_mac_addr, ETH_ALEN); ++ memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); + } + + igb_set_default_mac_filter(adapter); +-- +2.9.5 + diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.14/0005-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch b/recipes-kernel/linux/linux-toradex-mainline-4.14/0005-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch new file mode 100644 index 0000000..54bae71 --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline-4.14/0005-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch @@ -0,0 +1,53 @@ +From 0a6205b902807ab567285048b5094bdbbca4d262 Mon Sep 17 00:00:00 2001 +Message-Id: <0a6205b902807ab567285048b5094bdbbca4d262.1510580437.git.marcel.ziswiler@toradex.com> +In-Reply-To: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +References: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +From: Marcel Ziswiler +Date: Thu, 15 Dec 2016 10:56:26 +0100 +Subject: [PATCH 5/8] mmc: tegra: apalis-tk1: hack to make sd1 functional + +Disable the external loopback and use the internal loopback as per +SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to +0xfffd according to the TRM. + +Signed-off-by: Marcel Ziswiler +Acked-by: Dominik Sliwa + +(cherry picked from toradex_tk1_l4t_r21.5 commit +fc14b7601e5ca587afd97936ef3fd599f4e9281c) +--- + drivers/mmc/host/sdhci-tegra.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c +index 0cd6fa8..327883d 100644 +--- a/drivers/mmc/host/sdhci-tegra.c ++++ b/drivers/mmc/host/sdhci-tegra.c +@@ -43,6 +43,7 @@ + #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 + #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 + #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 ++#define SDHCI_MISC_CTRL_ENABLE_EXT_LOOPBACK 0x20000 + + #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 + #define SDHCI_AUTO_CAL_START BIT(31) +@@ -181,6 +182,16 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) + clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; + } + ++#define CONFIG_MACH_APALIS_TK1 ++#ifdef CONFIG_MACH_APALIS_TK1 ++ /* ++ * Disable the external loopback and use the internal loopback as per ++ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to ++ * 0xfffd according to the TRM. ++ */ ++ misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_EXT_LOOPBACK; ++#endif /* CONFIG_MACH_APALIS_TK1 */ ++ + sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); + sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); + +-- +2.9.5 + diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.14/0006-tegra_defconfig-snapd-squashfs-configuration.patch b/recipes-kernel/linux/linux-toradex-mainline-4.14/0006-tegra_defconfig-snapd-squashfs-configuration.patch new file mode 100644 index 0000000..c8fa537 --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline-4.14/0006-tegra_defconfig-snapd-squashfs-configuration.patch @@ -0,0 +1,36 @@ +From b05bf63df5d97e6260ea26ca90247613abc38c08 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +References: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +From: Marcel Ziswiler +Date: Sun, 18 Jun 2017 01:23:26 +0200 +Subject: [PATCH 6/8] tegra_defconfig: snapd squashfs configuration + +Prepare for snapd integration. + +Signed-off-by: Marcel Ziswiler +--- + arch/arm/configs/tegra_defconfig | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig +index cb97ea2..cfe997c 100644 +--- a/arch/arm/configs/tegra_defconfig ++++ b/arch/arm/configs/tegra_defconfig +@@ -295,7 +295,12 @@ CONFIG_AUTOFS4_FS=y + CONFIG_VFAT_FS=y + CONFIG_TMPFS=y + CONFIG_TMPFS_POSIX_ACL=y +-CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_ZLIB=y ++CONFIG_SQUASHFS_LZ4=y + CONFIG_SQUASHFS_LZO=y + CONFIG_SQUASHFS_XZ=y + CONFIG_NFS_FS=y +-- +2.9.5 + diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.14/0007-ARM-tegra-apalis-tk1-support-v1.2-hardware-revision.patch b/recipes-kernel/linux/linux-toradex-mainline-4.14/0007-ARM-tegra-apalis-tk1-support-v1.2-hardware-revision.patch new file mode 100644 index 0000000..359cbc0 --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline-4.14/0007-ARM-tegra-apalis-tk1-support-v1.2-hardware-revision.patch @@ -0,0 +1,2425 @@ +From b2fd39d0358d3a8847835ef57cc32f1ab2821e40 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +References: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +From: Marcel Ziswiler +Date: Mon, 2 Oct 2017 09:27:16 +0200 +Subject: [PATCH 7/8] ARM: tegra: apalis-tk1: support v1.2 hardware revision + +Support the V1.2 hardware revision with the following pin muxing +changes: + +Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4 +are now used as DDC pins. + +Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are +now used as USB power enable signals. + +Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power +enable signals are now used as GPIO3 and GPIO4. + +Signed-off-by: Marcel Ziswiler +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 299 ++++ + arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2070 +++++++++++++++++++++++ + 3 files changed, 2370 insertions(+) + create mode 100644 arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts + create mode 100644 arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index faf46ab..8451af8 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -960,6 +960,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ + tegra114-tn7.dtb + dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ + tegra124-apalis-eval.dtb \ ++ tegra124-apalis-v1.2-eval.dtb \ + tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ + tegra124-nyan-blaze.dtb \ +diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +new file mode 100644 +index 0000000..c61eb59 +--- /dev/null ++++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +@@ -0,0 +1,299 @@ ++/* ++ * Copyright 2016-2017 Toradex AG ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include ++#include "tegra124-apalis-v1.2.dtsi" ++ ++/ { ++ model = "Toradex Apalis TK1 on Apalis Evaluation Board"; ++ compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", ++ "toradex,apalis-tk1", "nvidia,tegra124"; ++ ++ aliases { ++ rtc0 = "/i2c@7000c000/rtc@68"; ++ rtc1 = "/i2c@7000d000/pmic@40"; ++ rtc2 = "/rtc@7000e000"; ++ serial0 = &uarta; ++ serial1 = &uartb; ++ serial2 = &uartc; ++ serial3 = &uartd; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ pcie@1003000 { ++ pci@1,0 { ++ status = "okay"; ++ }; ++ }; ++ ++ host1x@50000000 { ++ hdmi@54280000 { ++ status = "okay"; ++ }; ++ }; ++ ++ /* Apalis UART1 */ ++ serial@70006000 { ++ status = "okay"; ++ }; ++ ++ /* Apalis UART2 */ ++ serial@70006040 { ++ status = "okay"; ++ }; ++ ++ /* Apalis UART3 */ ++ serial@70006200 { ++ status = "okay"; ++ }; ++ ++ /* Apalis UART4 */ ++ serial@70006300 { ++ status = "okay"; ++ }; ++ ++ pwm@7000a000 { ++ status = "okay"; ++ }; ++ ++ /* ++ * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier ++ * board) ++ */ ++ i2c@7000c000 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ pcie-switch@58 { ++ compatible = "plx,pex8605"; ++ reg = <0x58>; ++ }; ++ ++ /* M41T0M6 real time clock on carrier board */ ++ rtc@68 { ++ compatible = "st,m41t00"; ++ reg = <0x68>; ++ }; ++ }; ++ ++ /* GEN2_I2C: unused */ ++ ++ /* ++ * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor ++ * on carrier board) ++ */ ++ i2c@7000c500 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ }; ++ ++ /* ++ * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) ++ */ ++ hdmi_ddc: i2c@7000c700 { ++ status = "okay"; ++ }; ++ ++ /* SPI1: Apalis SPI1 */ ++ spi@7000d400 { ++ status = "okay"; ++ spi-max-frequency = <50000000>; ++ ++ spidev0: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ }; ++ }; ++ ++ /* SPI4: Apalis SPI2 */ ++ spi@7000da00 { ++ status = "okay"; ++ spi-max-frequency = <50000000>; ++ ++ spidev1: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ }; ++ }; ++ ++ /* Apalis Serial ATA */ ++ sata@70020000 { ++ status = "okay"; ++ }; ++ ++ hda@70030000 { ++ status = "okay"; ++ }; ++ ++ usb@70090000 { ++ status = "okay"; ++ }; ++ ++ /* Apalis MMC1 */ ++ sdhci@700b0000 { ++ status = "okay"; ++ /* MMC1_CD# */ ++ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ vqmmc-supply = <&vddio_sdmmc1>; ++ }; ++ ++ /* Apalis SD1 */ ++ sdhci@700b0400 { ++ status = "okay"; ++ /* SD1_CD# */ ++ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ vqmmc-supply = <&vddio_sdmmc3>; ++ }; ++ ++ /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ ++ usb@7d000000 { ++ status = "okay"; ++ dr_mode = "otg"; ++ }; ++ ++ usb-phy@7d000000 { ++ status = "okay"; ++ vbus-supply = <®_usbo1_vbus>; ++ }; ++ ++ /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ ++ usb@7d004000 { ++ status = "okay"; ++ }; ++ ++ usb-phy@7d004000 { ++ status = "okay"; ++ vbus-supply = <®_usbh_vbus>; ++ }; ++ ++ /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ ++ usb@7d008000 { ++ status = "okay"; ++ }; ++ ++ usb-phy@7d008000 { ++ status = "okay"; ++ vbus-supply = <®_usbh_vbus>; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ /* BKL1_PWM */ ++ pwms = <&pwm 3 5000000>; ++ brightness-levels = <255 231 223 207 191 159 127 0>; ++ default-brightness-level = <6>; ++ /* BKL1_ON */ ++ enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ wakeup { ++ label = "WAKE1_MICO"; ++ gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ }; ++ }; ++ ++ reg_5v0: regulator-5v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "5V_SW"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ /* USBO1_EN */ ++ reg_usbo1_vbus: regulator-usbo1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_USBO1"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ vin-supply = <®_5v0>; ++ }; ++ ++ /* USBH_EN */ ++ reg_usbh_vbus: regulator-usbh-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ vin-supply = <®_5v0>; ++ }; ++}; ++ ++&gpio { ++ lan_reset_n { ++ gpio-hog; ++ gpios = ; ++ output-high; ++ line-name = "LAN_RESET_N"; ++ }; ++ ++ pex_perst_n { ++ gpio-hog; ++ gpios = ; ++ output-high; ++ line-name = "PEX_PERST_N"; ++ }; ++ ++ reset_moci_ctrl { ++ gpio-hog; ++ gpios = ; ++ output-high; ++ line-name = "RESET_MOCI_CTRL"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +new file mode 100644 +index 0000000..c2b14e69 +--- /dev/null ++++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +@@ -0,0 +1,2070 @@ ++/* ++ * Copyright 2016-2017 Toradex AG ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "tegra124.dtsi" ++#include "tegra124-apalis-emc.dtsi" ++ ++/* ++ * Toradex Apalis TK1 Module Device Tree ++ * Compatible for Revisions 2GB: V1.2A ++ */ ++/ { ++ model = "Toradex Apalis TK1"; ++ compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", ++ "nvidia,tegra124"; ++ ++ memory { ++ reg = <0x0 0x80000000 0x0 0x80000000>; ++ }; ++ ++ pcie@1003000 { ++ status = "okay"; ++ avddio-pex-supply = <&vdd_1v05>; ++ avdd-pex-pll-supply = <&vdd_1v05>; ++ avdd-pll-erefe-supply = <&avdd_1v05>; ++ dvddio-pex-supply = <&vdd_1v05>; ++ hvdd-pex-pll-e-supply = <®_3v3>; ++ hvdd-pex-supply = <®_3v3>; ++ vddio-pex-ctl-supply = <®_3v3>; ++ ++ /* Apalis PCIe (additional lane Apalis type specific) */ ++ pci@1,0 { ++ /* PCIE1_RX/TX and TS_DIFF1/2 */ ++ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, ++ <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; ++ phy-names = "pcie-0", "pcie-1"; ++ }; ++ ++ /* I210 Gigabit Ethernet Controller (On-module) */ ++ pci@2,0 { ++ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; ++ phy-names = "pcie-0"; ++ status = "okay"; ++ }; ++ }; ++ ++ host1x@50000000 { ++ hdmi@54280000 { ++ pll-supply = <®_1v05_avdd_hdmi_pll>; ++ vdd-supply = <®_3v3_avdd_hdmi>; ++ nvidia,ddc-i2c-bus = <&hdmi_ddc>; ++ nvidia,hpd-gpio = ++ <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ gpu@0,57000000 { ++ /* ++ * Node left disabled on purpose - the bootloader will enable ++ * it after having set the VPR up ++ */ ++ vdd-supply = <&vdd_gpu>; ++ }; ++ ++ pinmux: pinmux@70000868 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&state_default>; ++ ++ state_default: pinmux { ++ /* Analogue Audio (On-module) */ ++ dap3_fs_pp0 { ++ nvidia,pins = "dap3_fs_pp0"; ++ nvidia,function = "i2s2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap3_din_pp1 { ++ nvidia,pins = "dap3_din_pp1"; ++ nvidia,function = "i2s2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap3_dout_pp2 { ++ nvidia,pins = "dap3_dout_pp2"; ++ nvidia,function = "i2s2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap3_sclk_pp3 { ++ nvidia,pins = "dap3_sclk_pp3"; ++ nvidia,function = "i2s2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap_mclk1_pw4 { ++ nvidia,pins = "dap_mclk1_pw4"; ++ nvidia,function = "extperiph1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis BKL1_ON */ ++ pbb5 { ++ nvidia,pins = "pbb5"; ++ nvidia,function = "vgp5"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis BKL1_PWM */ ++ pu6 { ++ nvidia,pins = "pu6"; ++ nvidia,function = "pwm3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis CAM1_MCLK */ ++ cam_mclk_pcc0 { ++ nvidia,pins = "cam_mclk_pcc0"; ++ nvidia,function = "vi_alt3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis Digital Audio */ ++ dap2_fs_pa2 { ++ nvidia,pins = "dap2_fs_pa2"; ++ nvidia,function = "hda"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap2_sclk_pa3 { ++ nvidia,pins = "dap2_sclk_pa3"; ++ nvidia,function = "hda"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap2_din_pa4 { ++ nvidia,pins = "dap2_din_pa4"; ++ nvidia,function = "hda"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap2_dout_pa5 { ++ nvidia,pins = "dap2_dout_pa5"; ++ nvidia,function = "hda"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pbb3 { /* DAP1_RESET */ ++ nvidia,pins = "pbb3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ clk3_out_pee0 { ++ nvidia,pins = "clk3_out_pee0"; ++ nvidia,function = "extperiph3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis GPIO */ ++ usb_vbus_en0_pn4 { ++ nvidia,pins = "usb_vbus_en0_pn4"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ usb_vbus_en1_pn5 { ++ nvidia,pins = "usb_vbus_en1_pn5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ pex_l0_rst_n_pdd1 { ++ nvidia,pins = "pex_l0_rst_n_pdd1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pex_l0_clkreq_n_pdd2 { ++ nvidia,pins = "pex_l0_clkreq_n_pdd2"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pex_l1_rst_n_pdd5 { ++ nvidia,pins = "pex_l1_rst_n_pdd5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pex_l1_clkreq_n_pdd6 { ++ nvidia,pins = "pex_l1_clkreq_n_pdd6"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dp_hpd_pff0 { ++ nvidia,pins = "dp_hpd_pff0"; ++ nvidia,function = "dp"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pff2 { ++ nvidia,pins = "pff2"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ ++ nvidia,pins = "owr"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,rcv-sel = ; ++ }; ++ ++ /* Apalis HDMI1_CEC */ ++ hdmi_cec_pee3 { ++ nvidia,pins = "hdmi_cec_pee3"; ++ nvidia,function = "cec"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ ++ /* Apalis HDMI1_HPD */ ++ hdmi_int_pn7 { ++ nvidia,pins = "hdmi_int_pn7"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,rcv-sel = ; ++ }; ++ ++ /* Apalis I2C1 */ ++ gen1_i2c_scl_pc4 { ++ nvidia,pins = "gen1_i2c_scl_pc4"; ++ nvidia,function = "i2c1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ gen1_i2c_sda_pc5 { ++ nvidia,pins = "gen1_i2c_sda_pc5"; ++ nvidia,function = "i2c1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ ++ /* Apalis I2C3 (CAM) */ ++ cam_i2c_scl_pbb1 { ++ nvidia,pins = "cam_i2c_scl_pbb1"; ++ nvidia,function = "i2c3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ cam_i2c_sda_pbb2 { ++ nvidia,pins = "cam_i2c_sda_pbb2"; ++ nvidia,function = "i2c3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ ++ /* Apalis I2C4 (DDC) */ ++ ddc_scl_pv4 { ++ nvidia,pins = "ddc_scl_pv4"; ++ nvidia,function = "i2c4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,rcv-sel = ; ++ }; ++ ddc_sda_pv5 { ++ nvidia,pins = "ddc_sda_pv5"; ++ nvidia,function = "i2c4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,rcv-sel = ; ++ }; ++ ++ /* Apalis MMC1 */ ++ sdmmc1_cd_n_pv3 { /* CD# GPIO */ ++ nvidia,pins = "sdmmc1_wp_n_pv3"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ clk2_out_pw5 { /* D5 GPIO */ ++ nvidia,pins = "clk2_out_pw5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc1_dat3_py4 { ++ nvidia,pins = "sdmmc1_dat3_py4"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc1_dat2_py5 { ++ nvidia,pins = "sdmmc1_dat2_py5"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc1_dat1_py6 { ++ nvidia,pins = "sdmmc1_dat1_py6"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc1_dat0_py7 { ++ nvidia,pins = "sdmmc1_dat0_py7"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc1_clk_pz0 { ++ nvidia,pins = "sdmmc1_clk_pz0"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc1_cmd_pz1 { ++ nvidia,pins = "sdmmc1_cmd_pz1"; ++ nvidia,function = "sdmmc1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ clk2_req_pcc5 { /* D4 GPIO */ ++ nvidia,pins = "clk2_req_pcc5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ ++ nvidia,pins = "sdmmc3_clk_lb_in_pee5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ usb_vbus_en2_pff1 { /* D7 GPIO */ ++ nvidia,pins = "usb_vbus_en2_pff1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis PWM */ ++ ph0 { ++ nvidia,pins = "ph0"; ++ nvidia,function = "pwm0"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ph1 { ++ nvidia,pins = "ph1"; ++ nvidia,function = "pwm1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ph2 { ++ nvidia,pins = "ph2"; ++ nvidia,function = "pwm2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ ++ ph3 { ++ nvidia,pins = "ph3"; ++ nvidia,function = "pwm3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis SATA1_ACT# */ ++ dap1_dout_pn2 { ++ nvidia,pins = "dap1_dout_pn2"; ++ nvidia,function = "gmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis SD1 */ ++ sdmmc3_clk_pa6 { ++ nvidia,pins = "sdmmc3_clk_pa6"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc3_cmd_pa7 { ++ nvidia,pins = "sdmmc3_cmd_pa7"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc3_dat3_pb4 { ++ nvidia,pins = "sdmmc3_dat3_pb4"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc3_dat2_pb5 { ++ nvidia,pins = "sdmmc3_dat2_pb5"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc3_dat1_pb6 { ++ nvidia,pins = "sdmmc3_dat1_pb6"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc3_dat0_pb7 { ++ nvidia,pins = "sdmmc3_dat0_pb7"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc3_cd_n_pv2 { /* CD# GPIO */ ++ nvidia,pins = "sdmmc3_cd_n_pv2"; ++ nvidia,function = "rsvd3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis SPDIF */ ++ spdif_out_pk5 { ++ nvidia,pins = "spdif_out_pk5"; ++ nvidia,function = "spdif"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ spdif_in_pk6 { ++ nvidia,pins = "spdif_in_pk6"; ++ nvidia,function = "spdif"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis SPI1 */ ++ ulpi_clk_py0 { ++ nvidia,pins = "ulpi_clk_py0"; ++ nvidia,function = "spi1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ulpi_dir_py1 { ++ nvidia,pins = "ulpi_dir_py1"; ++ nvidia,function = "spi1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ulpi_nxt_py2 { ++ nvidia,pins = "ulpi_nxt_py2"; ++ nvidia,function = "spi1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ulpi_stp_py3 { ++ nvidia,pins = "ulpi_stp_py3"; ++ nvidia,function = "spi1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis SPI2 */ ++ pg5 { ++ nvidia,pins = "pg5"; ++ nvidia,function = "spi4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pg6 { ++ nvidia,pins = "pg6"; ++ nvidia,function = "spi4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pg7 { ++ nvidia,pins = "pg7"; ++ nvidia,function = "spi4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pi3 { ++ nvidia,pins = "pi3"; ++ nvidia,function = "spi4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis UART1 */ ++ pb1 { /* DCD GPIO */ ++ nvidia,pins = "pb1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pk7 { /* RI GPIO */ ++ nvidia,pins = "pk7"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart1_txd_pu0 { ++ nvidia,pins = "pu0"; ++ nvidia,function = "uarta"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart1_rxd_pu1 { ++ nvidia,pins = "pu1"; ++ nvidia,function = "uarta"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart1_cts_n_pu2 { ++ nvidia,pins = "pu2"; ++ nvidia,function = "uarta"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart1_rts_n_pu3 { ++ nvidia,pins = "pu3"; ++ nvidia,function = "uarta"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart3_cts_n_pa1 { /* DSR GPIO */ ++ nvidia,pins = "uart3_cts_n_pa1"; ++ nvidia,function = "gmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart3_rts_n_pc0 { /* DTR GPIO */ ++ nvidia,pins = "uart3_rts_n_pc0"; ++ nvidia,function = "gmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis UART2 */ ++ uart2_txd_pc2 { ++ nvidia,pins = "uart2_txd_pc2"; ++ nvidia,function = "irda"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart2_rxd_pc3 { ++ nvidia,pins = "uart2_rxd_pc3"; ++ nvidia,function = "irda"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart2_cts_n_pj5 { ++ nvidia,pins = "uart2_cts_n_pj5"; ++ nvidia,function = "uartb"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart2_rts_n_pj6 { ++ nvidia,pins = "uart2_rts_n_pj6"; ++ nvidia,function = "uartb"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis UART3 */ ++ uart3_txd_pw6 { ++ nvidia,pins = "uart3_txd_pw6"; ++ nvidia,function = "uartc"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart3_rxd_pw7 { ++ nvidia,pins = "uart3_rxd_pw7"; ++ nvidia,function = "uartc"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis UART4 */ ++ uart4_rxd_pb0 { ++ nvidia,pins = "pb0"; ++ nvidia,function = "uartd"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ uart4_txd_pj7 { ++ nvidia,pins = "pj7"; ++ nvidia,function = "uartd"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis USBH_EN */ ++ gen2_i2c_sda_pt6 { ++ nvidia,pins = "gen2_i2c_sda_pt6"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ ++ /* Apalis USBH_OC# */ ++ pbb0 { ++ nvidia,pins = "pbb0"; ++ nvidia,function = "vgp6"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis USBO1_EN */ ++ gen2_i2c_scl_pt5 { ++ nvidia,pins = "gen2_i2c_scl_pt5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ ++ /* Apalis USBO1_OC# */ ++ pbb4 { ++ nvidia,pins = "pbb4"; ++ nvidia,function = "vgp4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Apalis WAKE1_MICO */ ++ pex_wake_n_pdd3 { ++ nvidia,pins = "pex_wake_n_pdd3"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* CORE_PWR_REQ */ ++ core_pwr_req { ++ nvidia,pins = "core_pwr_req"; ++ nvidia,function = "pwron"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* CPU_PWR_REQ */ ++ cpu_pwr_req { ++ nvidia,pins = "cpu_pwr_req"; ++ nvidia,function = "cpu"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* DVFS */ ++ dvfs_pwm_px0 { ++ nvidia,pins = "dvfs_pwm_px0"; ++ nvidia,function = "cldvfs"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dvfs_clk_px2 { ++ nvidia,pins = "dvfs_clk_px2"; ++ nvidia,function = "cldvfs"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* eMMC */ ++ sdmmc4_dat0_paa0 { ++ nvidia,pins = "sdmmc4_dat0_paa0"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc4_dat1_paa1 { ++ nvidia,pins = "sdmmc4_dat1_paa1"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc4_dat2_paa2 { ++ nvidia,pins = "sdmmc4_dat2_paa2"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc4_dat3_paa3 { ++ nvidia,pins = "sdmmc4_dat3_paa3"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc4_dat4_paa4 { ++ nvidia,pins = "sdmmc4_dat4_paa4"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc4_dat5_paa5 { ++ nvidia,pins = "sdmmc4_dat5_paa5"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc4_dat6_paa6 { ++ nvidia,pins = "sdmmc4_dat6_paa6"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc4_dat7_paa7 { ++ nvidia,pins = "sdmmc4_dat7_paa7"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc4_clk_pcc4 { ++ nvidia,pins = "sdmmc4_clk_pcc4"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ sdmmc4_cmd_pt7 { ++ nvidia,pins = "sdmmc4_cmd_pt7"; ++ nvidia,function = "sdmmc4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* JTAG_RTCK */ ++ jtag_rtck { ++ nvidia,pins = "jtag_rtck"; ++ nvidia,function = "rtck"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* LAN_DEV_OFF# */ ++ ulpi_data5_po6 { ++ nvidia,pins = "ulpi_data5_po6"; ++ nvidia,function = "ulpi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* LAN_RESET# */ ++ kb_row10_ps2 { ++ nvidia,pins = "kb_row10_ps2"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* LAN_WAKE# */ ++ ulpi_data4_po5 { ++ nvidia,pins = "ulpi_data4_po5"; ++ nvidia,function = "ulpi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* MCU_INT1# */ ++ pk2 { ++ nvidia,pins = "pk2"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* MCU_INT2# */ ++ pj2 { ++ nvidia,pins = "pj2"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* MCU_INT3# */ ++ pi5 { ++ nvidia,pins = "pi5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* MCU_INT4# */ ++ pj0 { ++ nvidia,pins = "pj0"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* MCU_RESET */ ++ pbb6 { ++ nvidia,pins = "pbb6"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* MCU SPI */ ++ gpio_x4_aud_px4 { ++ nvidia,pins = "gpio_x4_aud_px4"; ++ nvidia,function = "spi2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ gpio_x5_aud_px5 { ++ nvidia,pins = "gpio_x5_aud_px5"; ++ nvidia,function = "spi2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ gpio_x6_aud_px6 { /* MCU_CS */ ++ nvidia,pins = "gpio_x6_aud_px6"; ++ nvidia,function = "spi2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ gpio_x7_aud_px7 { ++ nvidia,pins = "gpio_x7_aud_px7"; ++ nvidia,function = "spi2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ gpio_w2_aud_pw2 { /* MCU_CSEZP */ ++ nvidia,pins = "gpio_w2_aud_pw2"; ++ nvidia,function = "spi2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* PMIC_CLK_32K */ ++ clk_32k_in { ++ nvidia,pins = "clk_32k_in"; ++ nvidia,function = "clk"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* PMIC_CPU_OC_INT */ ++ clk_32k_out_pa0 { ++ nvidia,pins = "clk_32k_out_pa0"; ++ nvidia,function = "soc"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* PWR_I2C */ ++ pwr_i2c_scl_pz6 { ++ nvidia,pins = "pwr_i2c_scl_pz6"; ++ nvidia,function = "i2cpwr"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ pwr_i2c_sda_pz7 { ++ nvidia,pins = "pwr_i2c_sda_pz7"; ++ nvidia,function = "i2cpwr"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ nvidia,open-drain = ; ++ }; ++ ++ /* PWR_INT_N */ ++ pwr_int_n { ++ nvidia,pins = "pwr_int_n"; ++ nvidia,function = "pmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* RESET_MOCI_CTRL */ ++ pu4 { ++ nvidia,pins = "pu4"; ++ nvidia,function = "gmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* RESET_OUT_N */ ++ reset_out_n { ++ nvidia,pins = "reset_out_n"; ++ nvidia,function = "reset_out_n"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* SHIFT_CTRL_DIR_IN */ ++ kb_row0_pr0 { ++ nvidia,pins = "kb_row0_pr0"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row1_pr1 { ++ nvidia,pins = "kb_row1_pr1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* Configure level-shifter as output for HDA */ ++ kb_row11_ps3 { ++ nvidia,pins = "kb_row11_ps3"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* SHIFT_CTRL_DIR_OUT */ ++ kb_col5_pq5 { ++ nvidia,pins = "kb_col5_pq5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_col6_pq6 { ++ nvidia,pins = "kb_col6_pq6"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_col7_pq7 { ++ nvidia,pins = "kb_col7_pq7"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* SHIFT_CTRL_OE */ ++ kb_col0_pq0 { ++ nvidia,pins = "kb_col0_pq0"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_col1_pq1 { ++ nvidia,pins = "kb_col1_pq1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_col2_pq2 { ++ nvidia,pins = "kb_col2_pq2"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_col4_pq4 { ++ nvidia,pins = "kb_col4_pq4"; ++ nvidia,function = "kbc"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row2_pr2 { ++ nvidia,pins = "kb_row2_pr2"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ ++ pi6 { ++ nvidia,pins = "pi6"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ /* TOUCH_INT */ ++ gpio_w3_aud_pw3 { ++ nvidia,pins = "gpio_w3_aud_pw3"; ++ nvidia,function = "spi6"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ++ pc7 { /* NC */ ++ nvidia,pins = "pc7"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pg0 { /* NC */ ++ nvidia,pins = "pg0"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pg1 { /* NC */ ++ nvidia,pins = "pg1"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pg2 { /* NC */ ++ nvidia,pins = "pg2"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pg3 { /* NC */ ++ nvidia,pins = "pg3"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pg4 { /* NC */ ++ nvidia,pins = "pg4"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ph4 { /* NC */ ++ nvidia,pins = "ph4"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ph5 { /* NC */ ++ nvidia,pins = "ph5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ph6 { /* NC */ ++ nvidia,pins = "ph6"; ++ nvidia,function = "gmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ph7 { /* NC */ ++ nvidia,pins = "ph7"; ++ nvidia,function = "gmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pi0 { /* NC */ ++ nvidia,pins = "pi0"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pi1 { /* NC */ ++ nvidia,pins = "pi1"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pi2 { /* NC */ ++ nvidia,pins = "pi2"; ++ nvidia,function = "rsvd4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pi4 { /* NC */ ++ nvidia,pins = "pi4"; ++ nvidia,function = "gmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pi7 { /* NC */ ++ nvidia,pins = "pi7"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pk0 { /* NC */ ++ nvidia,pins = "pk0"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pk1 { /* NC */ ++ nvidia,pins = "pk1"; ++ nvidia,function = "rsvd4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pk3 { /* NC */ ++ nvidia,pins = "pk3"; ++ nvidia,function = "gmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pk4 { /* NC */ ++ nvidia,pins = "pk4"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap1_fs_pn0 { /* NC */ ++ nvidia,pins = "dap1_fs_pn0"; ++ nvidia,function = "rsvd4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap1_din_pn1 { /* NC */ ++ nvidia,pins = "dap1_din_pn1"; ++ nvidia,function = "rsvd4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap1_sclk_pn3 { /* NC */ ++ nvidia,pins = "dap1_sclk_pn3"; ++ nvidia,function = "rsvd4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ulpi_data7_po0 { /* NC */ ++ nvidia,pins = "ulpi_data7_po0"; ++ nvidia,function = "ulpi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ulpi_data0_po1 { /* NC */ ++ nvidia,pins = "ulpi_data0_po1"; ++ nvidia,function = "ulpi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ulpi_data1_po2 { /* NC */ ++ nvidia,pins = "ulpi_data1_po2"; ++ nvidia,function = "ulpi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ulpi_data2_po3 { /* NC */ ++ nvidia,pins = "ulpi_data2_po3"; ++ nvidia,function = "ulpi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ulpi_data3_po4 { /* NC */ ++ nvidia,pins = "ulpi_data3_po4"; ++ nvidia,function = "ulpi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ ulpi_data6_po7 { /* NC */ ++ nvidia,pins = "ulpi_data6_po7"; ++ nvidia,function = "ulpi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap4_fs_pp4 { /* NC */ ++ nvidia,pins = "dap4_fs_pp4"; ++ nvidia,function = "rsvd4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap4_din_pp5 { /* NC */ ++ nvidia,pins = "dap4_din_pp5"; ++ nvidia,function = "rsvd3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap4_dout_pp6 { /* NC */ ++ nvidia,pins = "dap4_dout_pp6"; ++ nvidia,function = "rsvd4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap4_sclk_pp7 { /* NC */ ++ nvidia,pins = "dap4_sclk_pp7"; ++ nvidia,function = "rsvd3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_col3_pq3 { /* NC */ ++ nvidia,pins = "kb_col3_pq3"; ++ nvidia,function = "kbc"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row3_pr3 { /* NC */ ++ nvidia,pins = "kb_row3_pr3"; ++ nvidia,function = "kbc"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row4_pr4 { /* NC */ ++ nvidia,pins = "kb_row4_pr4"; ++ nvidia,function = "rsvd3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row5_pr5 { /* NC */ ++ nvidia,pins = "kb_row5_pr5"; ++ nvidia,function = "rsvd3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row6_pr6 { /* NC */ ++ nvidia,pins = "kb_row6_pr6"; ++ nvidia,function = "kbc"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row7_pr7 { /* NC */ ++ nvidia,pins = "kb_row7_pr7"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row8_ps0 { /* NC */ ++ nvidia,pins = "kb_row8_ps0"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row9_ps1 { /* NC */ ++ nvidia,pins = "kb_row9_ps1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row12_ps4 { /* NC */ ++ nvidia,pins = "kb_row12_ps4"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row13_ps5 { /* NC */ ++ nvidia,pins = "kb_row13_ps5"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row14_ps6 { /* NC */ ++ nvidia,pins = "kb_row14_ps6"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row15_ps7 { /* NC */ ++ nvidia,pins = "kb_row15_ps7"; ++ nvidia,function = "rsvd3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row16_pt0 { /* NC */ ++ nvidia,pins = "kb_row16_pt0"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ kb_row17_pt1 { /* NC */ ++ nvidia,pins = "kb_row17_pt1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pu5 { /* NC */ ++ nvidia,pins = "pu5"; ++ nvidia,function = "gmi"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ /* ++ * PCB Version Indication: V1.2 and later have GPIO_PV0 ++ * wired to GND, was NC before ++ */ ++ pv0 { ++ nvidia,pins = "pv0"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pv1 { /* NC */ ++ nvidia,pins = "pv1"; ++ nvidia,function = "rsvd1"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ gpio_x1_aud_px1 { /* NC */ ++ nvidia,pins = "gpio_x1_aud_px1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ gpio_x3_aud_px3 { /* NC */ ++ nvidia,pins = "gpio_x3_aud_px3"; ++ nvidia,function = "rsvd4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pbb7 { /* NC */ ++ nvidia,pins = "pbb7"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pcc1 { /* NC */ ++ nvidia,pins = "pcc1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ pcc2 { /* NC */ ++ nvidia,pins = "pcc2"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ clk3_req_pee1 { /* NC */ ++ nvidia,pins = "clk3_req_pee1"; ++ nvidia,function = "rsvd2"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ dap_mclk1_req_pee2 { /* NC */ ++ nvidia,pins = "dap_mclk1_req_pee2"; ++ nvidia,function = "rsvd4"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ /* ++ * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output ++ * driver enabled aka not tristated and input driver ++ * enabled as well as it features some magic properties ++ * even though the external loopback is disabled and the ++ * internal loopback used as per ++ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 ++ * bits being set to 0xfffd according to the TRM! ++ */ ++ sdmmc3_clk_lb_out_pee4 { /* NC */ ++ nvidia,pins = "sdmmc3_clk_lb_out_pee4"; ++ nvidia,function = "sdmmc3"; ++ nvidia,pull = ; ++ nvidia,tristate = ; ++ nvidia,enable-input = ; ++ }; ++ }; ++ }; ++ ++ serial@70006040 { ++ compatible = "nvidia,tegra124-hsuart"; ++ }; ++ ++ serial@70006200 { ++ compatible = "nvidia,tegra124-hsuart"; ++ }; ++ ++ serial@70006300 { ++ compatible = "nvidia,tegra124-hsuart"; ++ }; ++ ++ hdmi_ddc: i2c@7000c700 { ++ clock-frequency = <10000>; ++ }; ++ ++ /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ ++ i2c@7000d000 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ /* SGTL5000 audio codec */ ++ sgtl5000: codec@a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ VDDA-supply = <®_3v3>; ++ VDDIO-supply = <&vddio_1v8>; ++ clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; ++ }; ++ ++ pmic: pmic@40 { ++ compatible = "ams,as3722"; ++ reg = <0x40>; ++ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; ++ ams,system-power-controller; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&as3722_default>; ++ ++ as3722_default: pinmux { ++ gpio2_7 { ++ pins = "gpio2", /* PWR_EN_+V3.3 */ ++ "gpio7"; /* +V1.6_LPO */ ++ function = "gpio"; ++ bias-pull-up; ++ }; ++ ++ gpio0_1_3_4_5_6 { ++ pins = "gpio0", "gpio1", "gpio3", ++ "gpio4", "gpio5", "gpio6"; ++ bias-high-impedance; ++ }; ++ }; ++ ++ regulators { ++ vsup-sd2-supply = <®_3v3>; ++ vsup-sd3-supply = <®_3v3>; ++ vsup-sd4-supply = <®_3v3>; ++ vsup-sd5-supply = <®_3v3>; ++ vin-ldo0-supply = <&vddio_ddr_1v35>; ++ vin-ldo1-6-supply = <®_3v3>; ++ vin-ldo2-5-7-supply = <&vddio_1v8>; ++ vin-ldo3-4-supply = <®_3v3>; ++ vin-ldo9-10-supply = <®_3v3>; ++ vin-ldo11-supply = <®_3v3>; ++ ++ vdd_cpu: sd0 { ++ regulator-name = "+VDD_CPU_AP"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-min-microamp = <3500000>; ++ regulator-max-microamp = <3500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ams,ext-control = <2>; ++ }; ++ ++ sd1 { ++ regulator-name = "+VDD_CORE"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-min-microamp = <2500000>; ++ regulator-max-microamp = <4000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ams,ext-control = <1>; ++ }; ++ ++ vddio_ddr_1v35: sd2 { ++ regulator-name = ++ "+V1.35_VDDIO_DDR(sd2)"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ sd3 { ++ regulator-name = ++ "+V1.35_VDDIO_DDR(sd3)"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vdd_1v05: sd4 { ++ regulator-name = "+V1.05"; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ }; ++ ++ vddio_1v8: sd5 { ++ regulator-name = "+V1.8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vdd_gpu: sd6 { ++ regulator-name = "+VDD_GPU_AP"; ++ regulator-min-microvolt = <650000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-min-microamp = <3500000>; ++ regulator-max-microamp = <3500000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ avdd_1v05: ldo0 { ++ regulator-name = "+V1.05_AVDD"; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-boot-on; ++ regulator-always-on; ++ ams,ext-control = <1>; ++ }; ++ ++ vddio_sdmmc1: ldo1 { ++ regulator-name = "VDDIO_SDMMC1"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ ldo2 { ++ regulator-name = "+V1.2"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo3 { ++ regulator-name = "+V1.05_RTC"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ ams,enable-tracking; ++ }; ++ ++ /* 1.8V for LVDS, 3.3V for eDP */ ++ ldo4 { ++ regulator-name = "AVDD_LVDS0_PLL"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ ++ /* LDO5 not used */ ++ ++ vddio_sdmmc3: ldo6 { ++ regulator-name = "VDDIO_SDMMC3"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ /* LDO7 not used */ ++ ++ ldo9 { ++ regulator-name = "+V3.3_ETH(ldo9)"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ ldo10 { ++ regulator-name = "+V3.3_ETH(ldo10)"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ ldo11 { ++ regulator-name = "+V1.8_VPP_FUSE"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ }; ++ }; ++ ++ /* ++ * TMP451 temperature sensor ++ * Note: THERM_N directly connected to AS3722 PMIC THERM ++ */ ++ temperature-sensor@4c { ++ compatible = "ti,tmp451"; ++ reg = <0x4c>; ++ interrupt-parent = <&gpio>; ++ interrupts = ; ++ #thermal-sensor-cells = <1>; ++ }; ++ }; ++ ++ /* SPI2: MCU SPI */ ++ spi@7000d600 { ++ status = "okay"; ++ spi-max-frequency = <25000000>; ++ }; ++ ++ pmc@7000e400 { ++ nvidia,invert-interrupt; ++ nvidia,suspend-mode = <1>; ++ nvidia,cpu-pwr-good-time = <500>; ++ nvidia,cpu-pwr-off-time = <300>; ++ nvidia,core-pwr-good-time = <641 3845>; ++ nvidia,core-pwr-off-time = <61036>; ++ nvidia,core-power-req-active-high; ++ nvidia,sys-clock-req-active-high; ++ ++ /* Set power_off bit in ResetControl register of AS3722 PMIC */ ++ i2c-thermtrip { ++ nvidia,i2c-controller-id = <4>; ++ nvidia,bus-addr = <0x40>; ++ nvidia,reg-addr = <0x36>; ++ nvidia,reg-data = <0x2>; ++ }; ++ }; ++ ++ sata@70020000 { ++ phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; ++ phy-names = "sata-0"; ++ avdd-supply = <&vdd_1v05>; ++ hvdd-supply = <®_3v3>; ++ vddio-supply = <&vdd_1v05>; ++ }; ++ ++ usb@70090000 { ++ /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ ++ phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, ++ <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, ++ <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, ++ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, ++ <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; ++ phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; ++ avddio-pex-supply = <&vdd_1v05>; ++ avdd-pll-erefe-supply = <&avdd_1v05>; ++ avdd-pll-utmip-supply = <&vddio_1v8>; ++ avdd-usb-ss-pll-supply = <&vdd_1v05>; ++ avdd-usb-supply = <®_3v3>; ++ dvddio-pex-supply = <&vdd_1v05>; ++ hvdd-usb-ss-pll-e-supply = <®_3v3>; ++ hvdd-usb-ss-supply = <®_3v3>; ++ }; ++ ++ padctl@7009f000 { ++ pads { ++ usb2 { ++ status = "okay"; ++ ++ lanes { ++ usb2-0 { ++ nvidia,function = "xusb"; ++ status = "okay"; ++ }; ++ ++ usb2-1 { ++ nvidia,function = "xusb"; ++ status = "okay"; ++ }; ++ ++ usb2-2 { ++ nvidia,function = "xusb"; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ pcie { ++ status = "okay"; ++ ++ lanes { ++ pcie-0 { ++ nvidia,function = "usb3-ss"; ++ status = "okay"; ++ }; ++ ++ pcie-1 { ++ nvidia,function = "usb3-ss"; ++ status = "okay"; ++ }; ++ ++ pcie-2 { ++ nvidia,function = "pcie"; ++ status = "okay"; ++ }; ++ ++ pcie-3 { ++ nvidia,function = "pcie"; ++ status = "okay"; ++ }; ++ ++ pcie-4 { ++ nvidia,function = "pcie"; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ sata { ++ status = "okay"; ++ ++ lanes { ++ sata-0 { ++ nvidia,function = "sata"; ++ status = "okay"; ++ }; ++ }; ++ }; ++ }; ++ ++ ports { ++ /* USBO1 */ ++ usb2-0 { ++ status = "okay"; ++ mode = "otg"; ++ ++ vbus-supply = <®_usbo1_vbus>; ++ }; ++ ++ /* USBH2 */ ++ usb2-1 { ++ status = "okay"; ++ mode = "host"; ++ ++ vbus-supply = <®_usbh_vbus>; ++ }; ++ ++ /* USBH4 */ ++ usb2-2 { ++ status = "okay"; ++ mode = "host"; ++ ++ vbus-supply = <®_usbh_vbus>; ++ }; ++ ++ usb3-0 { ++ nvidia,usb2-companion = <2>; ++ status = "okay"; ++ }; ++ ++ usb3-1 { ++ nvidia,usb2-companion = <0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ /* eMMC */ ++ sdhci@700b0600 { ++ status = "okay"; ++ bus-width = <8>; ++ non-removable; ++ }; ++ ++ /* CPU DFLL clock */ ++ clock@70110000 { ++ status = "okay"; ++ vdd-cpu-supply = <&vdd_cpu>; ++ nvidia,i2c-fs-rate = <400000>; ++ }; ++ ++ ahub@70300000 { ++ i2s@70301200 { ++ status = "okay"; ++ }; ++ }; ++ ++ clocks { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ clk32k_in: clock@0 { ++ compatible = "fixed-clock"; ++ reg = <0>; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ }; ++ }; ++ ++ cpus { ++ cpu@0 { ++ vdd-cpu-supply = <&vdd_cpu>; ++ }; ++ }; ++ ++ reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { ++ compatible = "regulator-fixed"; ++ regulator-name = "+V1.05_AVDD_HDMI_PLL"; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; ++ vin-supply = <&vdd_1v05>; ++ }; ++ ++ reg_3v3_mxm: regulator-3v3-mxm { ++ compatible = "regulator-fixed"; ++ regulator-name = "+V3.3_MXM"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ reg_3v3: regulator-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "+V3.3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ /* PWR_EN_+V3.3 */ ++ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ vin-supply = <®_3v3_mxm>; ++ }; ++ ++ reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { ++ compatible = "regulator-fixed"; ++ regulator-name = "+V3.3_AVDD_HDMI"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vdd_1v05>; ++ }; ++ ++ sound { ++ compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", ++ "nvidia,tegra-audio-sgtl5000"; ++ nvidia,model = "Toradex Apalis TK1"; ++ nvidia,audio-routing = ++ "Headphone Jack", "HP_OUT", ++ "LINE_IN", "Line In Jack", ++ "MIC_IN", "Mic Jack"; ++ nvidia,i2s-controller = <&tegra_i2s2>; ++ nvidia,audio-codec = <&sgtl5000>; ++ clocks = <&tegra_car TEGRA124_CLK_PLL_A>, ++ <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, ++ <&tegra_car TEGRA124_CLK_EXTERN1>; ++ clock-names = "pll_a", "pll_a_out0", "mclk"; ++ }; ++ ++ thermal-zones { ++ cpu { ++ trips { ++ cpu-shutdown-trip { ++ temperature = <101000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ mem { ++ trips { ++ mem-shutdown-trip { ++ temperature = <101000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gpu { ++ trips { ++ gpu-shutdown-trip { ++ temperature = <101000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++}; +-- +2.9.5 + diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.14/0008-apalis-tk1-fix-pcie-reset-for-reliable-gigabit-ether.patch b/recipes-kernel/linux/linux-toradex-mainline-4.14/0008-apalis-tk1-fix-pcie-reset-for-reliable-gigabit-ether.patch new file mode 100644 index 0000000..50d7407 --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline-4.14/0008-apalis-tk1-fix-pcie-reset-for-reliable-gigabit-ether.patch @@ -0,0 +1,140 @@ +From ea64a271a36553990bb2a6cb40edfd929d8e6e88 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +References: <8d39626d07718220b426e9be045df8ed9d1fd707.1510580437.git.marcel.ziswiler@toradex.com> +From: Marcel Ziswiler +Date: Mon, 13 Nov 2017 14:37:25 +0100 +Subject: [PATCH 8/8] apalis-tk1: fix pcie reset for reliable gigabit ethernet + operation + +It turns out that the current PCIe reset implementation is not quite +working reliably due to some Intel i210 errata. Fix this by making sure +the i210's +V3.3_ETH rail is properly disabled during its reset +sequence. + +Also further improve on the bringing up the PCIe switch as found on the +Apalis Evaluation board. + +Signed-off-by: Marcel Ziswiler +Acked-by: Dominik Sliwa +(downstream commit 7ad9771527d2b1c884beb22d9df28bae899f8d3d) +--- + drivers/pci/host/pci-tegra.c | 72 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 72 insertions(+) + +diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c +index 5c7916b..0c62371 100644 +--- a/drivers/pci/host/pci-tegra.c ++++ b/drivers/pci/host/pci-tegra.c +@@ -71,8 +71,12 @@ + #ifdef CONFIG_MACH_APALIS_TK1 + #define APALIS_GPIO7 TEGRA_GPIO(DD, 1) + ++#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6) ++ + #define LAN_RESET_N TEGRA_GPIO(S, 2) + ++#define LAN_WAKE_N TEGRA_GPIO(O, 5) ++ + #define PEX_PERST_N APALIS_GPIO7 + + #define RESET_MOCI_N TEGRA_GPIO(U, 4) +@@ -329,6 +333,11 @@ struct tegra_pcie { + struct regulator_bulk_data *supplies; + unsigned int num_supplies; + ++#ifdef CONFIG_MACH_APALIS_TK1 ++ struct regulator *regulator_apalis_tk1_ldo9; ++ struct regulator *regulator_apalis_tk1_ldo10; ++#endif /* CONFIG_MACH_APALIS_TK1 */ ++ + const struct tegra_pcie_soc *soc; + struct dentry *debugfs; + }; +@@ -592,6 +601,42 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) + gpio_request(LAN_RESET_N, "LAN_RESET_N"); + gpio_direction_output(LAN_RESET_N, 0); + } ++ ++ /* ++ * Make sure we don't get any back feeding from LAN_WAKE_N resp. ++ * DEV_OFF_N ++ */ ++ gpio_request(LAN_WAKE_N, "LAN_WAKE_N"); ++ gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N"); ++ gpio_direction_output(LAN_WAKE_N, 0); ++ gpio_direction_output(LAN_DEV_OFF_N, 0); ++ ++ /* Make sure LDO9 and LDO10 are initially disabled @ 0V */ ++ if (regulator_is_enabled(port->pcie->regulator_apalis_tk1_ldo9)) ++ regulator_disable(port->pcie->regulator_apalis_tk1_ldo9); ++ if (regulator_is_enabled(port->pcie->regulator_apalis_tk1_ldo10)) ++ regulator_disable(port->pcie->regulator_apalis_tk1_ldo10); ++ ++ mdelay(100); ++ ++ /* Make sure LAN_WAKE_N gets re-configured as a GPIO input */ ++ gpio_direction_input(LAN_WAKE_N); ++ ++ /* Make sure controller gets enabled by disabling DEV_OFF_N */ ++ gpio_set_value(LAN_DEV_OFF_N, 1); ++ ++ /* ++ * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype ++ * V1.0A and sample V1.0B and newer modules ++ */ ++ if (regulator_enable(port->pcie->regulator_apalis_tk1_ldo9) < 0) { ++ pr_err("pcie: couldn't enable regulator i210_vdd3p3_ldo9\n"); ++ return; ++ } ++ if (regulator_enable(port->pcie->regulator_apalis_tk1_ldo10) < 0) { ++ pr_err("pcie: couldn't enable regulator i210_vdd3p3_ldo10\n"); ++ return; ++ } + #endif /* CONFIG_MACH_APALIS_TK1 */ + #endif /* CONFIG_MACH_APALIS_T30 || CONFIG_MACH_APALIS_TK1 */ + +@@ -607,6 +652,10 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) + afi_writel(port->pcie, value, ctrl); + + #if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_APALIS_TK1) ++#ifdef CONFIG_MACH_APALIS_TK1 ++ gpio_set_value(LAN_RESET_N, 1); ++#endif /* CONFIG_MACH_APALIS_TK1 */ ++ + /* Must be asserted for 100 ms after power and clocks are stable */ + if (g_pex_perst) + gpio_set_value(PEX_PERST_N, 1); +@@ -1181,6 +1230,29 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) + return err; + } + ++#ifdef CONFIG_MACH_APALIS_TK1 ++ if (pcie->regulator_apalis_tk1_ldo9 == NULL) { ++ pcie->regulator_apalis_tk1_ldo9 = regulator_get(pcie->dev, "i210_vdd3p3_ldo9"); ++ if (IS_ERR(pcie->regulator_apalis_tk1_ldo9)) { ++ pr_err("pcie: couldn't get regulator i210_vdd3p3_ldo9\n"); ++ pcie->regulator_apalis_tk1_ldo9 = 0; ++ } ++ } ++ ++ if (pcie->regulator_apalis_tk1_ldo10 == NULL) { ++ pcie->regulator_apalis_tk1_ldo10 = regulator_get(pcie->dev, "i210_vdd3p3_ldo10"); ++ if (IS_ERR(pcie->regulator_apalis_tk1_ldo10)) { ++ pr_err("pcie: couldn't get regulator i210_vdd3p3_ldo10\n"); ++ pcie->regulator_apalis_tk1_ldo10 = 0; ++ } ++ } ++ ++ if (pcie->regulator_apalis_tk1_ldo9) ++ err = regulator_enable(pcie->regulator_apalis_tk1_ldo9); ++ if (pcie->regulator_apalis_tk1_ldo10) ++ err = regulator_enable(pcie->regulator_apalis_tk1_ldo10); ++#endif /* CONFIG_MACH_APALIS_TK1 */ ++ + reset_control_deassert(pcie->afi_rst); + + err = clk_prepare_enable(pcie->afi_clk); +-- +2.9.5 + diff --git a/recipes-kernel/linux/linux-toradex-mainline_4.14.bb b/recipes-kernel/linux/linux-toradex-mainline_4.14.bb new file mode 100644 index 0000000..3bd54dc --- /dev/null +++ b/recipes-kernel/linux/linux-toradex-mainline_4.14.bb @@ -0,0 +1,74 @@ +SUMMARY = "Linux Kernel for Toradex Apalis Tegra based modules" +SECTION = "kernel" +LICENSE = "GPLv2" + +FILESEXTRAPATHS_prepend := "${THISDIR}/linux-toradex-mainline-4.14:" + +LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7" + +inherit kernel siteinfo +require recipes-kernel/linux/linux-dtb.inc +include conf/tdx_version.conf + +LINUX_VERSION ?= "4.14" + +LOCALVERSION = "-${PR}" +PR = "${TDX_VER_INT}" + +PV = "${LINUX_VERSION}" +S = "${WORKDIR}/linux-${PV}" +TK1-PATCHES = " \ + file://0001-toradex_apalis_tk1_t30-customize-defconfig.patch \ + file://0002-apalis_t30-tk1-fix-pcie-clock-and-reset-not-conformi.patch \ + file://0003-igb-integrate-tools-only-device-support.patch \ + file://0004-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch \ + file://0005-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch \ + file://0006-tegra_defconfig-snapd-squashfs-configuration.patch \ + file://0007-ARM-tegra-apalis-tk1-support-v1.2-hardware-revision.patch \ + file://0008-apalis-tk1-fix-pcie-reset-for-reliable-gigabit-ether.patch \ +" +SRC_URI = " \ + https://cdn.kernel.org/pub/linux/kernel/v4.x/linux-${PV}.tar.xz \ + ${TK1-PATCHES} \ +" +SRC_URI[md5sum] = "bacdb9ffdcd922aa069a5e1520160e24" +SRC_URI[sha256sum] = "f81d59477e90a130857ce18dc02f4fbe5725854911db1e7ba770c7cd350f96a7" + +# For CI use one could use the following instead (plus patches still of course) +LINUX_VERSION_use-head-next ?= "4.14" +SRCREV_use-head-next = "${AUTOREV}" +PV_use-head-next = "${LINUX_VERSION}+git${SRCPV}" +S_use-head-next = "${WORKDIR}/git" +SRCBRANCH_use-head-next = "linux-4.14.y" +SRC_URI_use-head-next = " \ + git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git;protocol=git;branch=${SRCBRANCH} \ + ${TK1-PATCHES} \ +" + +COMPATIBLE_MACHINE = "(apalis-tk1-mainline|apalis-t30-mainline)" +KERNEL_EXTRA_ARGS = " LOADADDR=0x80008000 " + +# One possibiltiy for changes to the defconfig: +config_script () { + echo "dummy" > /dev/null +} + +do_configure_prepend () { + cd ${S} + export KBUILD_OUTPUT=${B} + oe_runmake ${KERNEL_DEFCONFIG} + + #maybe change some configuration + config_script + + #Add Toradex BSP Version as LOCALVERSION + sed -i -e /CONFIG_LOCALVERSION/d ${B}/.config + echo "CONFIG_LOCALVERSION=\"${LOCALVERSION}\"" >> ${B}/.config + + cd - > /dev/null +} + +do_uboot_mkimage_prepend() { + cd ${B} +} + -- cgit v1.2.3