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[
{
"PublicDescription": "lpddr4 evk board bandwidth usage",
"BriefDescription": "imx8mq: percentage of bandwidth usage for ddr0",
"MetricName": "imx8mq-ddr0-bandwidth-usage",
"MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)",
"MetricGroup": "i.MX8MQ_DDR_MON",
"ScaleUnit": "1e2%",
"SocName": "i.MX8MQ"
},
{
"PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
"BriefDescription": "imx8mq: bytes of all masters read from ddr0",
"MetricName": "imx8mq-ddr0-all-r",
"MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 4",
"MetricGroup": "i.MX8MQ_DDR_MON",
"SocName": "i.MX8MQ"
},
{
"PublicDescription": "Calculate bytes all masters write to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
"BriefDescription": "imx8mq: bytes of all masters write to ddr0",
"MetricName": "imx8mq-ddr0-all-w",
"MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 4",
"MetricGroup": "i.MX8MQ_DDR_MON",
"SocName": "i.MX8MQ"
}
]
|
