From 678708d95daa7d29ad5f49944f1b5385e3f27401 Mon Sep 17 00:00:00 2001 From: Jihoon Bang Date: Tue, 19 Jun 2012 16:12:00 -0700 Subject: WAR: gr3d: limit 3d clock when camera is on As WAR, limit 3d clock frequency and emc clock frequency when camera is on and chip is AP37. 3d clock is set to 361MHz and 437MHz is requested for emc clock with this change. This change allows 3d to request 1.1V in Core instead of 1.3V in AP37. Bug 1001262 Bug 1019309 Change-Id: I9f46f93d8da0fcf5afe05839177bf0d6e43a5840 Signed-off-by: Jihoon Bang Reviewed-on: http://git-master/r/130945 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- include/media/tegra_camera.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/media/tegra_camera.h b/include/media/tegra_camera.h index 9dea1485781d..3c41864cc71f 100644 --- a/include/media/tegra_camera.h +++ b/include/media/tegra_camera.h @@ -2,6 +2,7 @@ * include/linux/tegra_camera.h * * Copyright (C) 2010 Google, Inc. + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -48,6 +49,15 @@ enum StereoCameraMode { StereoCameraMode_Force32 = 0x7FFFFFFF }; +struct tegra_camera_platform_data { + bool limit_3d_emc_clk; +}; + +#if defined(CONFIG_TEGRA_CAMERA) +int is_tegra_camera_on(void); +#else +int is_tegra_camera_on(void) { return 0; } +#endif #define TEGRA_CAMERA_IOCTL_ENABLE _IOWR('i', 1, uint) #define TEGRA_CAMERA_IOCTL_DISABLE _IOWR('i', 2, uint) -- cgit v1.2.3