From daed8f84e1675e9c091ae240d041c458be6f263f Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 17 Jan 2018 15:57:51 +0100 Subject: apalis-imx8qm: take PLX PCIe switch out of reset via GPIO7 The Apalis iMX8 does not make use of the PCIE_CTRL0_PERST_B signal. However, the Apalis Evaluation Board uses GPIO7 as a PCIe reset signal for the PLX PCIe switch. With this the Apalis PCIe port comes up as Gen2 successfully on the Apalis Evaluation board. Signed-off-by: Stefan Agner --- arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index c3a158a4c30e..f9f2afd55afb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -327,6 +327,7 @@ SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x00000021 SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x00000021 + SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021 >; }; @@ -646,7 +647,7 @@ <&pcie_sata_refclk_gate>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi", "pcie_ext"; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; -- cgit v1.2.3